arch/arm/boot/dts/aspeed-g4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2400";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm926ej-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@40000000 {
  46                 device_type = "memory";
  47                 reg = <0x40000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: spi@1e620000 {
  57                         reg = < 0x1e620000 0x94
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2400-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 spi-max-frequency = <50000000>;
  69                                 status = "disabled";
  70                         };
  71                         flash@1 {
  72                                 reg = < 1 >;
  73                                 compatible = "jedec,spi-nor";
  74                                 status = "disabled";
  75                         };
  76                         flash@2 {
  77                                 reg = < 2 >;
  78                                 compatible = "jedec,spi-nor";
  79                                 status = "disabled";
  80                         };
  81                         flash@3 {
  82                                 reg = < 3 >;
  83                                 compatible = "jedec,spi-nor";
  84                                 status = "disabled";
  85                         };
  86                         flash@4 {
  87                                 reg = < 4 >;
  88                                 compatible = "jedec,spi-nor";
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 spi: spi@1e630000 {
  94                         reg = < 0x1e630000 0x18
  95                                 0x30000000 0x10000000 >;
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         compatible = "aspeed,ast2400-spi";
  99                         clocks = <&syscon ASPEED_CLK_AHB>;
 100                         status = "disabled";
 101                         flash@0 {
 102                                 reg = < 0 >;
 103                                 compatible = "jedec,spi-nor";
 104                                 spi-max-frequency = <50000000>;
 105                                 status = "disabled";
 106                         };
 107                 };
 108
 109                 vic: interrupt-controller@1e6c0080 {
 110                         compatible = "aspeed,ast2400-vic";
 111                         interrupt-controller;
 112                         #interrupt-cells = <1>;
 113                         valid-sources = <0xffffffff 0x0007ffff>;
 114                         reg = <0x1e6c0080 0x80>;
 115                 };
 116
 117                 cvic: copro-interrupt-controller@1e6c2000 {
 118                         compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
 119                         valid-sources = <0x7fffffff>;
 120                         reg = <0x1e6c2000 0x80>;
 121                 };
 122
 123                 mac0: ethernet@1e660000 {
 124                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 125                         reg = <0x1e660000 0x180>;
 126                         interrupts = <2>;
 127                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 128                         status = "disabled";
 129                 };
 130
 131                 mac1: ethernet@1e680000 {
 132                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 133                         reg = <0x1e680000 0x180>;
 134                         interrupts = <3>;
 135                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 136                         status = "disabled";
 137                 };
 138
 139                 ehci0: usb@1e6a1000 {
 140                         compatible = "aspeed,ast2400-ehci", "generic-ehci";
 141                         reg = <0x1e6a1000 0x100>;
 142                         interrupts = <5>;
 143                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 144                         pinctrl-names = "default";
 145                         pinctrl-0 = <&pinctrl_usb2h_default>;
 146                         status = "disabled";
 147                 };
 148
 149                 uhci: usb@1e6b0000 {
 150                         compatible = "aspeed,ast2400-uhci", "generic-uhci";
 151                         reg = <0x1e6b0000 0x100>;
 152                         interrupts = <14>;
 153                         #ports = <3>;
 154                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 155                         status = "disabled";
 156                         /*
 157                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 158                          * override if you don't enable EHCI
 159                          */
 160                 };
 161
 162                 vhub: usb-vhub@1e6a0000 {
 163                         compatible = "aspeed,ast2400-usb-vhub";
 164                         reg = <0x1e6a0000 0x300>;
 165                         interrupts = <5>;
 166                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 167                         aspeed,vhub-downstream-ports = <5>;
 168                         aspeed,vhub-generic-endpoints = <15>;
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&pinctrl_usb2d_default>;
 171                         status = "disabled";
 172                 };
 173
 174                 apb {
 175                         compatible = "simple-bus";
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         ranges;
 179
 180                         syscon: syscon@1e6e2000 {
 181                                 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
 182                                 reg = <0x1e6e2000 0x1a8>;
 183                                 #address-cells = <1>;
 184                                 #size-cells = <1>;
 185                                 ranges = <0 0x1e6e2000 0x1000>;
 186                                 #clock-cells = <1>;
 187                                 #reset-cells = <1>;
 188
 189                                 p2a: p2a-control@2c {
 190                                         reg = <0x2c 0x4>;
 191                                         compatible = "aspeed,ast2400-p2a-ctrl";
 192                                         status = "disabled";
 193                                 };
 194
 195                                 silicon-id@7c {
 196                                         compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
 197                                         reg = <0x7c 0x4>;
 198                                 };
 199
 200                                 pinctrl: pinctrl@80 {
 201                                         reg = <0x80 0x18>, <0xa0 0x10>;
 202                                         compatible = "aspeed,ast2400-pinctrl";
 203                                 };
 204                         };
 205
 206                         rng: hwrng@1e6e2078 {
 207                                 compatible = "timeriomem_rng";
 208                                 reg = <0x1e6e2078 0x4>;
 209                                 period = <1>;
 210                                 quality = <100>;
 211                         };
 212
 213                         adc: adc@1e6e9000 {
 214                                 compatible = "aspeed,ast2400-adc";
 215                                 reg = <0x1e6e9000 0xb0>;
 216                                 clocks = <&syscon ASPEED_CLK_APB>;
 217                                 resets = <&syscon ASPEED_RESET_ADC>;
 218                                 #io-channel-cells = <1>;
 219                                 status = "disabled";
 220                         };
 221
 222                         sram: sram@1e720000 {
 223                                 compatible = "mmio-sram";
 224                                 reg = <0x1e720000 0x8000>;      // 32K
 225                         };
 226
 227                         video: video@1e700000 {
 228                                 compatible = "aspeed,ast2400-video-engine";
 229                                 reg = <0x1e700000 0x1000>;
 230                                 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
 231                                          <&syscon ASPEED_CLK_GATE_ECLK>;
 232                                 clock-names = "vclk", "eclk";
 233                                 interrupts = <7>;
 234                                 status = "disabled";
 235                         };
 236
 237                         sdmmc: sd-controller@1e740000 {
 238                                 compatible = "aspeed,ast2400-sd-controller";
 239                                 reg = <0x1e740000 0x100>;
 240                                 #address-cells = <1>;
 241                                 #size-cells = <1>;
 242                                 ranges = <0 0x1e740000 0x10000>;
 243                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
 244                                 status = "disabled";
 245
 246                                 sdhci0: sdhci@100 {
 247                                         compatible = "aspeed,ast2400-sdhci";
 248                                         reg = <0x100 0x100>;
 249                                         interrupts = <26>;
 250                                         sdhci,auto-cmd12;
 251                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 252                                         status = "disabled";
 253                                 };
 254
 255                                 sdhci1: sdhci@200 {
 256                                         compatible = "aspeed,ast2400-sdhci";
 257                                         reg = <0x200 0x100>;
 258                                         interrupts = <26>;
 259                                         sdhci,auto-cmd12;
 260                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 261                                         status = "disabled";
 262                                 };
 263                         };
 264
 265                         gpio: gpio@1e780000 {
 266                                 #gpio-cells = <2>;
 267                                 gpio-controller;
 268                                 compatible = "aspeed,ast2400-gpio";
 269                                 reg = <0x1e780000 0x1000>;
 270                                 interrupts = <20>;
 271                                 gpio-ranges = <&pinctrl 0 0 220>;
 272                                 clocks = <&syscon ASPEED_CLK_APB>;
 273                                 interrupt-controller;
 274                                 #interrupt-cells = <2>;
 275                         };
 276
 277                         timer: timer@1e782000 {
 278                                 /* This timer is a Faraday FTTMR010 derivative */
 279                                 compatible = "aspeed,ast2400-timer";
 280                                 reg = <0x1e782000 0x90>;
 281                                 interrupts = <16 17 18 35 36 37 38 39>;
 282                                 clocks = <&syscon ASPEED_CLK_APB>;
 283                                 clock-names = "PCLK";
 284                         };
 285
 286                         rtc: rtc@1e781000 {
 287                                 compatible = "aspeed,ast2400-rtc";
 288                                 reg = <0x1e781000 0x18>;
 289                                 status = "disabled";
 290                         };
 291
 292                         uart1: serial@1e783000 {
 293                                 compatible = "ns16550a";
 294                                 reg = <0x1e783000 0x20>;
 295                                 reg-shift = <2>;
 296                                 interrupts = <9>;
 297                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 298                                 resets = <&lpc_reset 4>;
 299                                 no-loopback-test;
 300                                 status = "disabled";
 301                         };
 302
 303                         uart5: serial@1e784000 {
 304                                 compatible = "ns16550a";
 305                                 reg = <0x1e784000 0x20>;
 306                                 reg-shift = <2>;
 307                                 interrupts = <10>;
 308                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 309                                 no-loopback-test;
 310                                 status = "disabled";
 311                         };
 312
 313                         wdt1: watchdog@1e785000 {
 314                                 compatible = "aspeed,ast2400-wdt";
 315                                 reg = <0x1e785000 0x1c>;
 316                                 clocks = <&syscon ASPEED_CLK_APB>;
 317                         };
 318
 319                         wdt2: watchdog@1e785020 {
 320                                 compatible = "aspeed,ast2400-wdt";
 321                                 reg = <0x1e785020 0x1c>;
 322                                 clocks = <&syscon ASPEED_CLK_APB>;
 323                         };
 324
 325                         pwm_tacho: pwm-tacho-controller@1e786000 {
 326                                 compatible = "aspeed,ast2400-pwm-tacho";
 327                                 #address-cells = <1>;
 328                                 #size-cells = <0>;
 329                                 reg = <0x1e786000 0x1000>;
 330                                 clocks = <&syscon ASPEED_CLK_24M>;
 331                                 resets = <&syscon ASPEED_RESET_PWM>;
 332                                 status = "disabled";
 333                         };
 334
 335                         vuart: serial@1e787000 {
 336                                 compatible = "aspeed,ast2400-vuart";
 337                                 reg = <0x1e787000 0x40>;
 338                                 reg-shift = <2>;
 339                                 interrupts = <8>;
 340                                 clocks = <&syscon ASPEED_CLK_APB>;
 341                                 no-loopback-test;
 342                                 status = "disabled";
 343                         };
 344
 345                         lpc: lpc@1e789000 {
 346                                 compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
 347                                 reg = <0x1e789000 0x1000>;
 348                                 reg-io-width = <4>;
 349
 350                                 #address-cells = <1>;
 351                                 #size-cells = <1>;
 352                                 ranges = <0x0 0x1e789000 0x1000>;
 353
 354                                 lpc_ctrl: lpc-ctrl@80 {
 355                                         compatible = "aspeed,ast2400-lpc-ctrl";
 356                                         reg = <0x80 0x10>;
 357                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 358                                         status = "disabled";
 359                                 };
 360
 361                                 lpc_snoop: lpc-snoop@90 {
 362                                         compatible = "aspeed,ast2400-lpc-snoop";
 363                                         reg = <0x90 0x8>;
 364                                         interrupts = <8>;
 365                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 366                                         status = "disabled";
 367                                 };
 368
 369                                 lhc: lhc@a0 {
 370                                         compatible = "aspeed,ast2400-lhc";
 371                                         reg = <0xa0 0x24 0xc8 0x8>;
 372                                 };
 373
 374                                 lpc_reset: reset-controller@98 {
 375                                         compatible = "aspeed,ast2400-lpc-reset";
 376                                         reg = <0x98 0x4>;
 377                                         #reset-cells = <1>;
 378                                 };
 379
 380                                 ibt: ibt@140 {
 381                                         compatible = "aspeed,ast2400-ibt-bmc";
 382                                         reg = <0x140 0x18>;
 383                                         interrupts = <8>;
 384                                         status = "disabled";
 385                                 };
 386                         };
 387
 388                         uart2: serial@1e78d000 {
 389                                 compatible = "ns16550a";
 390                                 reg = <0x1e78d000 0x20>;
 391                                 reg-shift = <2>;
 392                                 interrupts = <32>;
 393                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 394                                 resets = <&lpc_reset 5>;
 395                                 no-loopback-test;
 396                                 status = "disabled";
 397                         };
 398
 399                         uart3: serial@1e78e000 {
 400                                 compatible = "ns16550a";
 401                                 reg = <0x1e78e000 0x20>;
 402                                 reg-shift = <2>;
 403                                 interrupts = <33>;
 404                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 405                                 resets = <&lpc_reset 6>;
 406                                 no-loopback-test;
 407                                 status = "disabled";
 408                         };
 409
 410                         uart4: serial@1e78f000 {
 411                                 compatible = "ns16550a";
 412                                 reg = <0x1e78f000 0x20>;
 413                                 reg-shift = <2>;
 414                                 interrupts = <34>;
 415                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 416                                 resets = <&lpc_reset 7>;
 417                                 no-loopback-test;
 418                                 status = "disabled";
 419                         };
 420
 421                         i2c: bus@1e78a000 {
 422                                 compatible = "simple-bus";
 423                                 #address-cells = <1>;
 424                                 #size-cells = <1>;
 425                                 ranges = <0 0x1e78a000 0x1000>;
 426                         };
 427                 };
 428         };
 429 };
 430
 431 &i2c {
 432         i2c_ic: interrupt-controller@0 {
 433                 #interrupt-cells = <1>;
 434                 compatible = "aspeed,ast2400-i2c-ic";
 435                 reg = <0x0 0x40>;
 436                 interrupts = <12>;
 437                 interrupt-controller;
 438         };
 439
 440         i2c0: i2c-bus@40 {
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 #interrupt-cells = <1>;
 444
 445                 reg = <0x40 0x40>;
 446                 compatible = "aspeed,ast2400-i2c-bus";
 447                 clocks = <&syscon ASPEED_CLK_APB>;
 448                 resets = <&syscon ASPEED_RESET_I2C>;
 449                 bus-frequency = <100000>;
 450                 interrupts = <0>;
 451                 interrupt-parent = <&i2c_ic>;
 452                 status = "disabled";
 453                 /* Does not need pinctrl properties */
 454         };
 455
 456         i2c1: i2c-bus@80 {
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 #interrupt-cells = <1>;
 460
 461                 reg = <0x80 0x40>;
 462                 compatible = "aspeed,ast2400-i2c-bus";
 463                 clocks = <&syscon ASPEED_CLK_APB>;
 464                 resets = <&syscon ASPEED_RESET_I2C>;
 465                 bus-frequency = <100000>;
 466                 interrupts = <1>;
 467                 interrupt-parent = <&i2c_ic>;
 468                 status = "disabled";
 469                 /* Does not need pinctrl properties */
 470         };
 471
 472         i2c2: i2c-bus@c0 {
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 #interrupt-cells = <1>;
 476
 477                 reg = <0xc0 0x40>;
 478                 compatible = "aspeed,ast2400-i2c-bus";
 479                 clocks = <&syscon ASPEED_CLK_APB>;
 480                 resets = <&syscon ASPEED_RESET_I2C>;
 481                 bus-frequency = <100000>;
 482                 interrupts = <2>;
 483                 interrupt-parent = <&i2c_ic>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&pinctrl_i2c3_default>;
 486                 status = "disabled";
 487         };
 488
 489         i2c3: i2c-bus@100 {
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 #interrupt-cells = <1>;
 493
 494                 reg = <0x100 0x40>;
 495                 compatible = "aspeed,ast2400-i2c-bus";
 496                 clocks = <&syscon ASPEED_CLK_APB>;
 497                 resets = <&syscon ASPEED_RESET_I2C>;
 498                 bus-frequency = <100000>;
 499                 interrupts = <3>;
 500                 interrupt-parent = <&i2c_ic>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&pinctrl_i2c4_default>;
 503                 status = "disabled";
 504         };
 505
 506         i2c4: i2c-bus@140 {
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 #interrupt-cells = <1>;
 510
 511                 reg = <0x140 0x40>;
 512                 compatible = "aspeed,ast2400-i2c-bus";
 513                 clocks = <&syscon ASPEED_CLK_APB>;
 514                 resets = <&syscon ASPEED_RESET_I2C>;
 515                 bus-frequency = <100000>;
 516                 interrupts = <4>;
 517                 interrupt-parent = <&i2c_ic>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&pinctrl_i2c5_default>;
 520                 status = "disabled";
 521         };
 522
 523         i2c5: i2c-bus@180 {
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 #interrupt-cells = <1>;
 527
 528                 reg = <0x180 0x40>;
 529                 compatible = "aspeed,ast2400-i2c-bus";
 530                 clocks = <&syscon ASPEED_CLK_APB>;
 531                 resets = <&syscon ASPEED_RESET_I2C>;
 532                 bus-frequency = <100000>;
 533                 interrupts = <5>;
 534                 interrupt-parent = <&i2c_ic>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&pinctrl_i2c6_default>;
 537                 status = "disabled";
 538         };
 539
 540         i2c6: i2c-bus@1c0 {
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 #interrupt-cells = <1>;
 544
 545                 reg = <0x1c0 0x40>;
 546                 compatible = "aspeed,ast2400-i2c-bus";
 547                 clocks = <&syscon ASPEED_CLK_APB>;
 548                 resets = <&syscon ASPEED_RESET_I2C>;
 549                 bus-frequency = <100000>;
 550                 interrupts = <6>;
 551                 interrupt-parent = <&i2c_ic>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&pinctrl_i2c7_default>;
 554                 status = "disabled";
 555         };
 556
 557         i2c7: i2c-bus@300 {
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 #interrupt-cells = <1>;
 561
 562                 reg = <0x300 0x40>;
 563                 compatible = "aspeed,ast2400-i2c-bus";
 564                 clocks = <&syscon ASPEED_CLK_APB>;
 565                 resets = <&syscon ASPEED_RESET_I2C>;
 566                 bus-frequency = <100000>;
 567                 interrupts = <7>;
 568                 interrupt-parent = <&i2c_ic>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pinctrl_i2c8_default>;
 571                 status = "disabled";
 572         };
 573
 574         i2c8: i2c-bus@340 {
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 #interrupt-cells = <1>;
 578
 579                 reg = <0x340 0x40>;
 580                 compatible = "aspeed,ast2400-i2c-bus";
 581                 clocks = <&syscon ASPEED_CLK_APB>;
 582                 resets = <&syscon ASPEED_RESET_I2C>;
 583                 bus-frequency = <100000>;
 584                 interrupts = <8>;
 585                 interrupt-parent = <&i2c_ic>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&pinctrl_i2c9_default>;
 588                 status = "disabled";
 589         };
 590
 591         i2c9: i2c-bus@380 {
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 #interrupt-cells = <1>;
 595
 596                 reg = <0x380 0x40>;
 597                 compatible = "aspeed,ast2400-i2c-bus";
 598                 clocks = <&syscon ASPEED_CLK_APB>;
 599                 resets = <&syscon ASPEED_RESET_I2C>;
 600                 bus-frequency = <100000>;
 601                 interrupts = <9>;
 602                 interrupt-parent = <&i2c_ic>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&pinctrl_i2c10_default>;
 605                 status = "disabled";
 606         };
 607
 608         i2c10: i2c-bus@3c0 {
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 #interrupt-cells = <1>;
 612
 613                 reg = <0x3c0 0x40>;
 614                 compatible = "aspeed,ast2400-i2c-bus";
 615                 clocks = <&syscon ASPEED_CLK_APB>;
 616                 resets = <&syscon ASPEED_RESET_I2C>;
 617                 bus-frequency = <100000>;
 618                 interrupts = <10>;
 619                 interrupt-parent = <&i2c_ic>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&pinctrl_i2c11_default>;
 622                 status = "disabled";
 623         };
 624
 625         i2c11: i2c-bus@400 {
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 #interrupt-cells = <1>;
 629
 630                 reg = <0x400 0x40>;
 631                 compatible = "aspeed,ast2400-i2c-bus";
 632                 clocks = <&syscon ASPEED_CLK_APB>;
 633                 resets = <&syscon ASPEED_RESET_I2C>;
 634                 bus-frequency = <100000>;
 635                 interrupts = <11>;
 636                 interrupt-parent = <&i2c_ic>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&pinctrl_i2c12_default>;
 639                 status = "disabled";
 640         };
 641
 642         i2c12: i2c-bus@440 {
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 #interrupt-cells = <1>;
 646
 647                 reg = <0x440 0x40>;
 648                 compatible = "aspeed,ast2400-i2c-bus";
 649                 clocks = <&syscon ASPEED_CLK_APB>;
 650                 resets = <&syscon ASPEED_RESET_I2C>;
 651                 bus-frequency = <100000>;
 652                 interrupts = <12>;
 653                 interrupt-parent = <&i2c_ic>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&pinctrl_i2c13_default>;
 656                 status = "disabled";
 657         };
 658
 659         i2c13: i2c-bus@480 {
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 #interrupt-cells = <1>;
 663
 664                 reg = <0x480 0x40>;
 665                 compatible = "aspeed,ast2400-i2c-bus";
 666                 clocks = <&syscon ASPEED_CLK_APB>;
 667                 resets = <&syscon ASPEED_RESET_I2C>;
 668                 bus-frequency = <100000>;
 669                 interrupts = <13>;
 670                 interrupt-parent = <&i2c_ic>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&pinctrl_i2c14_default>;
 673                 status = "disabled";
 674         };
 675 };
 676
 677 &pinctrl {
 678         pinctrl_acpi_default: acpi_default {
 679                 function = "ACPI";
 680                 groups = "ACPI";
 681         };
 682
 683         pinctrl_adc0_default: adc0_default {
 684                 function = "ADC0";
 685                 groups = "ADC0";
 686         };
 687
 688         pinctrl_adc1_default: adc1_default {
 689                 function = "ADC1";
 690                 groups = "ADC1";
 691         };
 692
 693         pinctrl_adc10_default: adc10_default {
 694                 function = "ADC10";
 695                 groups = "ADC10";
 696         };
 697
 698         pinctrl_adc11_default: adc11_default {
 699                 function = "ADC11";
 700                 groups = "ADC11";
 701         };
 702
 703         pinctrl_adc12_default: adc12_default {
 704                 function = "ADC12";
 705                 groups = "ADC12";
 706         };
 707
 708         pinctrl_adc13_default: adc13_default {
 709                 function = "ADC13";
 710                 groups = "ADC13";
 711         };
 712
 713         pinctrl_adc14_default: adc14_default {
 714                 function = "ADC14";
 715                 groups = "ADC14";
 716         };
 717
 718         pinctrl_adc15_default: adc15_default {
 719                 function = "ADC15";
 720                 groups = "ADC15";
 721         };
 722
 723         pinctrl_adc2_default: adc2_default {
 724                 function = "ADC2";
 725                 groups = "ADC2";
 726         };
 727
 728         pinctrl_adc3_default: adc3_default {
 729                 function = "ADC3";
 730                 groups = "ADC3";
 731         };
 732
 733         pinctrl_adc4_default: adc4_default {
 734                 function = "ADC4";
 735                 groups = "ADC4";
 736         };
 737
 738         pinctrl_adc5_default: adc5_default {
 739                 function = "ADC5";
 740                 groups = "ADC5";
 741         };
 742
 743         pinctrl_adc6_default: adc6_default {
 744                 function = "ADC6";
 745                 groups = "ADC6";
 746         };
 747
 748         pinctrl_adc7_default: adc7_default {
 749                 function = "ADC7";
 750                 groups = "ADC7";
 751         };
 752
 753         pinctrl_adc8_default: adc8_default {
 754                 function = "ADC8";
 755                 groups = "ADC8";
 756         };
 757
 758         pinctrl_adc9_default: adc9_default {
 759                 function = "ADC9";
 760                 groups = "ADC9";
 761         };
 762
 763         pinctrl_bmcint_default: bmcint_default {
 764                 function = "BMCINT";
 765                 groups = "BMCINT";
 766         };
 767
 768         pinctrl_ddcclk_default: ddcclk_default {
 769                 function = "DDCCLK";
 770                 groups = "DDCCLK";
 771         };
 772
 773         pinctrl_ddcdat_default: ddcdat_default {
 774                 function = "DDCDAT";
 775                 groups = "DDCDAT";
 776         };
 777
 778         pinctrl_extrst_default: extrst_default {
 779                 function = "EXTRST";
 780                 groups = "EXTRST";
 781         };
 782
 783         pinctrl_flack_default: flack_default {
 784                 function = "FLACK";
 785                 groups = "FLACK";
 786         };
 787
 788         pinctrl_flbusy_default: flbusy_default {
 789                 function = "FLBUSY";
 790                 groups = "FLBUSY";
 791         };
 792
 793         pinctrl_flwp_default: flwp_default {
 794                 function = "FLWP";
 795                 groups = "FLWP";
 796         };
 797
 798         pinctrl_gpid_default: gpid_default {
 799                 function = "GPID";
 800                 groups = "GPID";
 801         };
 802
 803         pinctrl_gpid0_default: gpid0_default {
 804                 function = "GPID0";
 805                 groups = "GPID0";
 806         };
 807
 808         pinctrl_gpid2_default: gpid2_default {
 809                 function = "GPID2";
 810                 groups = "GPID2";
 811         };
 812
 813         pinctrl_gpid4_default: gpid4_default {
 814                 function = "GPID4";
 815                 groups = "GPID4";
 816         };
 817
 818         pinctrl_gpid6_default: gpid6_default {
 819                 function = "GPID6";
 820                 groups = "GPID6";
 821         };
 822
 823         pinctrl_gpie0_default: gpie0_default {
 824                 function = "GPIE0";
 825                 groups = "GPIE0";
 826         };
 827
 828         pinctrl_gpie2_default: gpie2_default {
 829                 function = "GPIE2";
 830                 groups = "GPIE2";
 831         };
 832
 833         pinctrl_gpie4_default: gpie4_default {
 834                 function = "GPIE4";
 835                 groups = "GPIE4";
 836         };
 837
 838         pinctrl_gpie6_default: gpie6_default {
 839                 function = "GPIE6";
 840                 groups = "GPIE6";
 841         };
 842
 843         pinctrl_i2c10_default: i2c10_default {
 844                 function = "I2C10";
 845                 groups = "I2C10";
 846         };
 847
 848         pinctrl_i2c11_default: i2c11_default {
 849                 function = "I2C11";
 850                 groups = "I2C11";
 851         };
 852
 853         pinctrl_i2c12_default: i2c12_default {
 854                 function = "I2C12";
 855                 groups = "I2C12";
 856         };
 857
 858         pinctrl_i2c13_default: i2c13_default {
 859                 function = "I2C13";
 860                 groups = "I2C13";
 861         };
 862
 863         pinctrl_i2c14_default: i2c14_default {
 864                 function = "I2C14";
 865                 groups = "I2C14";
 866         };
 867
 868         pinctrl_i2c3_default: i2c3_default {
 869                 function = "I2C3";
 870                 groups = "I2C3";
 871         };
 872
 873         pinctrl_i2c4_default: i2c4_default {
 874                 function = "I2C4";
 875                 groups = "I2C4";
 876         };
 877
 878         pinctrl_i2c5_default: i2c5_default {
 879                 function = "I2C5";
 880                 groups = "I2C5";
 881         };
 882
 883         pinctrl_i2c6_default: i2c6_default {
 884                 function = "I2C6";
 885                 groups = "I2C6";
 886         };
 887
 888         pinctrl_i2c7_default: i2c7_default {
 889                 function = "I2C7";
 890                 groups = "I2C7";
 891         };
 892
 893         pinctrl_i2c8_default: i2c8_default {
 894                 function = "I2C8";
 895                 groups = "I2C8";
 896         };
 897
 898         pinctrl_i2c9_default: i2c9_default {
 899                 function = "I2C9";
 900                 groups = "I2C9";
 901         };
 902
 903         pinctrl_lpcpd_default: lpcpd_default {
 904                 function = "LPCPD";
 905                 groups = "LPCPD";
 906         };
 907
 908         pinctrl_lpcpme_default: lpcpme_default {
 909                 function = "LPCPME";
 910                 groups = "LPCPME";
 911         };
 912
 913         pinctrl_lpcrst_default: lpcrst_default {
 914                 function = "LPCRST";
 915                 groups = "LPCRST";
 916         };
 917
 918         pinctrl_lpcsmi_default: lpcsmi_default {
 919                 function = "LPCSMI";
 920                 groups = "LPCSMI";
 921         };
 922
 923         pinctrl_mac1link_default: mac1link_default {
 924                 function = "MAC1LINK";
 925                 groups = "MAC1LINK";
 926         };
 927
 928         pinctrl_mac2link_default: mac2link_default {
 929                 function = "MAC2LINK";
 930                 groups = "MAC2LINK";
 931         };
 932
 933         pinctrl_mdio1_default: mdio1_default {
 934                 function = "MDIO1";
 935                 groups = "MDIO1";
 936         };
 937
 938         pinctrl_mdio2_default: mdio2_default {
 939                 function = "MDIO2";
 940                 groups = "MDIO2";
 941         };
 942
 943         pinctrl_ncts1_default: ncts1_default {
 944                 function = "NCTS1";
 945                 groups = "NCTS1";
 946         };
 947
 948         pinctrl_ncts2_default: ncts2_default {
 949                 function = "NCTS2";
 950                 groups = "NCTS2";
 951         };
 952
 953         pinctrl_ncts3_default: ncts3_default {
 954                 function = "NCTS3";
 955                 groups = "NCTS3";
 956         };
 957
 958         pinctrl_ncts4_default: ncts4_default {
 959                 function = "NCTS4";
 960                 groups = "NCTS4";
 961         };
 962
 963         pinctrl_ndcd1_default: ndcd1_default {
 964                 function = "NDCD1";
 965                 groups = "NDCD1";
 966         };
 967
 968         pinctrl_ndcd2_default: ndcd2_default {
 969                 function = "NDCD2";
 970                 groups = "NDCD2";
 971         };
 972
 973         pinctrl_ndcd3_default: ndcd3_default {
 974                 function = "NDCD3";
 975                 groups = "NDCD3";
 976         };
 977
 978         pinctrl_ndcd4_default: ndcd4_default {
 979                 function = "NDCD4";
 980                 groups = "NDCD4";
 981         };
 982
 983         pinctrl_ndsr1_default: ndsr1_default {
 984                 function = "NDSR1";
 985                 groups = "NDSR1";
 986         };
 987
 988         pinctrl_ndsr2_default: ndsr2_default {
 989                 function = "NDSR2";
 990                 groups = "NDSR2";
 991         };
 992
 993         pinctrl_ndsr3_default: ndsr3_default {
 994                 function = "NDSR3";
 995                 groups = "NDSR3";
 996         };
 997
 998         pinctrl_ndsr4_default: ndsr4_default {
 999                 function = "NDSR4";
1000                 groups = "NDSR4";
1001         };
1002
1003         pinctrl_ndtr1_default: ndtr1_default {
1004                 function = "NDTR1";
1005                 groups = "NDTR1";
1006         };
1007
1008         pinctrl_ndtr2_default: ndtr2_default {
1009                 function = "NDTR2";
1010                 groups = "NDTR2";
1011         };
1012
1013         pinctrl_ndtr3_default: ndtr3_default {
1014                 function = "NDTR3";
1015                 groups = "NDTR3";
1016         };
1017
1018         pinctrl_ndtr4_default: ndtr4_default {
1019                 function = "NDTR4";
1020                 groups = "NDTR4";
1021         };
1022
1023         pinctrl_ndts4_default: ndts4_default {
1024                 function = "NDTS4";
1025                 groups = "NDTS4";
1026         };
1027
1028         pinctrl_nri1_default: nri1_default {
1029                 function = "NRI1";
1030                 groups = "NRI1";
1031         };
1032
1033         pinctrl_nri2_default: nri2_default {
1034                 function = "NRI2";
1035                 groups = "NRI2";
1036         };
1037
1038         pinctrl_nri3_default: nri3_default {
1039                 function = "NRI3";
1040                 groups = "NRI3";
1041         };
1042
1043         pinctrl_nri4_default: nri4_default {
1044                 function = "NRI4";
1045                 groups = "NRI4";
1046         };
1047
1048         pinctrl_nrts1_default: nrts1_default {
1049                 function = "NRTS1";
1050                 groups = "NRTS1";
1051         };
1052
1053         pinctrl_nrts2_default: nrts2_default {
1054                 function = "NRTS2";
1055                 groups = "NRTS2";
1056         };
1057
1058         pinctrl_nrts3_default: nrts3_default {
1059                 function = "NRTS3";
1060                 groups = "NRTS3";
1061         };
1062
1063         pinctrl_oscclk_default: oscclk_default {
1064                 function = "OSCCLK";
1065                 groups = "OSCCLK";
1066         };
1067
1068         pinctrl_pwm0_default: pwm0_default {
1069                 function = "PWM0";
1070                 groups = "PWM0";
1071         };
1072
1073         pinctrl_pwm1_default: pwm1_default {
1074                 function = "PWM1";
1075                 groups = "PWM1";
1076         };
1077
1078         pinctrl_pwm2_default: pwm2_default {
1079                 function = "PWM2";
1080                 groups = "PWM2";
1081         };
1082
1083         pinctrl_pwm3_default: pwm3_default {
1084                 function = "PWM3";
1085                 groups = "PWM3";
1086         };
1087
1088         pinctrl_pwm4_default: pwm4_default {
1089                 function = "PWM4";
1090                 groups = "PWM4";
1091         };
1092
1093         pinctrl_pwm5_default: pwm5_default {
1094                 function = "PWM5";
1095                 groups = "PWM5";
1096         };
1097
1098         pinctrl_pwm6_default: pwm6_default {
1099                 function = "PWM6";
1100                 groups = "PWM6";
1101         };
1102
1103         pinctrl_pwm7_default: pwm7_default {
1104                 function = "PWM7";
1105                 groups = "PWM7";
1106         };
1107
1108         pinctrl_rgmii1_default: rgmii1_default {
1109                 function = "RGMII1";
1110                 groups = "RGMII1";
1111         };
1112
1113         pinctrl_rgmii2_default: rgmii2_default {
1114                 function = "RGMII2";
1115                 groups = "RGMII2";
1116         };
1117
1118         pinctrl_rmii1_default: rmii1_default {
1119                 function = "RMII1";
1120                 groups = "RMII1";
1121         };
1122
1123         pinctrl_rmii2_default: rmii2_default {
1124                 function = "RMII2";
1125                 groups = "RMII2";
1126         };
1127
1128         pinctrl_rom16_default: rom16_default {
1129                 function = "ROM16";
1130                 groups = "ROM16";
1131         };
1132
1133         pinctrl_rom8_default: rom8_default {
1134                 function = "ROM8";
1135                 groups = "ROM8";
1136         };
1137
1138         pinctrl_romcs1_default: romcs1_default {
1139                 function = "ROMCS1";
1140                 groups = "ROMCS1";
1141         };
1142
1143         pinctrl_romcs2_default: romcs2_default {
1144                 function = "ROMCS2";
1145                 groups = "ROMCS2";
1146         };
1147
1148         pinctrl_romcs3_default: romcs3_default {
1149                 function = "ROMCS3";
1150                 groups = "ROMCS3";
1151         };
1152
1153         pinctrl_romcs4_default: romcs4_default {
1154                 function = "ROMCS4";
1155                 groups = "ROMCS4";
1156         };
1157
1158         pinctrl_rxd1_default: rxd1_default {
1159                 function = "RXD1";
1160                 groups = "RXD1";
1161         };
1162
1163         pinctrl_rxd2_default: rxd2_default {
1164                 function = "RXD2";
1165                 groups = "RXD2";
1166         };
1167
1168         pinctrl_rxd3_default: rxd3_default {
1169                 function = "RXD3";
1170                 groups = "RXD3";
1171         };
1172
1173         pinctrl_rxd4_default: rxd4_default {
1174                 function = "RXD4";
1175                 groups = "RXD4";
1176         };
1177
1178         pinctrl_salt1_default: salt1_default {
1179                 function = "SALT1";
1180                 groups = "SALT1";
1181         };
1182
1183         pinctrl_salt2_default: salt2_default {
1184                 function = "SALT2";
1185                 groups = "SALT2";
1186         };
1187
1188         pinctrl_salt3_default: salt3_default {
1189                 function = "SALT3";
1190                 groups = "SALT3";
1191         };
1192
1193         pinctrl_salt4_default: salt4_default {
1194                 function = "SALT4";
1195                 groups = "SALT4";
1196         };
1197
1198         pinctrl_sd1_default: sd1_default {
1199                 function = "SD1";
1200                 groups = "SD1";
1201         };
1202
1203         pinctrl_sd2_default: sd2_default {
1204                 function = "SD2";
1205                 groups = "SD2";
1206         };
1207
1208         pinctrl_sgpmck_default: sgpmck_default {
1209                 function = "SGPMCK";
1210                 groups = "SGPMCK";
1211         };
1212
1213         pinctrl_sgpmi_default: sgpmi_default {
1214                 function = "SGPMI";
1215                 groups = "SGPMI";
1216         };
1217
1218         pinctrl_sgpmld_default: sgpmld_default {
1219                 function = "SGPMLD";
1220                 groups = "SGPMLD";
1221         };
1222
1223         pinctrl_sgpmo_default: sgpmo_default {
1224                 function = "SGPMO";
1225                 groups = "SGPMO";
1226         };
1227
1228         pinctrl_sgpsck_default: sgpsck_default {
1229                 function = "SGPSCK";
1230                 groups = "SGPSCK";
1231         };
1232
1233         pinctrl_sgpsi0_default: sgpsi0_default {
1234                 function = "SGPSI0";
1235                 groups = "SGPSI0";
1236         };
1237
1238         pinctrl_sgpsi1_default: sgpsi1_default {
1239                 function = "SGPSI1";
1240                 groups = "SGPSI1";
1241         };
1242
1243         pinctrl_sgpsld_default: sgpsld_default {
1244                 function = "SGPSLD";
1245                 groups = "SGPSLD";
1246         };
1247
1248         pinctrl_sioonctrl_default: sioonctrl_default {
1249                 function = "SIOONCTRL";
1250                 groups = "SIOONCTRL";
1251         };
1252
1253         pinctrl_siopbi_default: siopbi_default {
1254                 function = "SIOPBI";
1255                 groups = "SIOPBI";
1256         };
1257
1258         pinctrl_siopbo_default: siopbo_default {
1259                 function = "SIOPBO";
1260                 groups = "SIOPBO";
1261         };
1262
1263         pinctrl_siopwreq_default: siopwreq_default {
1264                 function = "SIOPWREQ";
1265                 groups = "SIOPWREQ";
1266         };
1267
1268         pinctrl_siopwrgd_default: siopwrgd_default {
1269                 function = "SIOPWRGD";
1270                 groups = "SIOPWRGD";
1271         };
1272
1273         pinctrl_sios3_default: sios3_default {
1274                 function = "SIOS3";
1275                 groups = "SIOS3";
1276         };
1277
1278         pinctrl_sios5_default: sios5_default {
1279                 function = "SIOS5";
1280                 groups = "SIOS5";
1281         };
1282
1283         pinctrl_siosci_default: siosci_default {
1284                 function = "SIOSCI";
1285                 groups = "SIOSCI";
1286         };
1287
1288         pinctrl_spi1_default: spi1_default {
1289                 function = "SPI1";
1290                 groups = "SPI1";
1291         };
1292
1293         pinctrl_spi1debug_default: spi1debug_default {
1294                 function = "SPI1DEBUG";
1295                 groups = "SPI1DEBUG";
1296         };
1297
1298         pinctrl_spi1passthru_default: spi1passthru_default {
1299                 function = "SPI1PASSTHRU";
1300                 groups = "SPI1PASSTHRU";
1301         };
1302
1303         pinctrl_spics1_default: spics1_default {
1304                 function = "SPICS1";
1305                 groups = "SPICS1";
1306         };
1307
1308         pinctrl_timer3_default: timer3_default {
1309                 function = "TIMER3";
1310                 groups = "TIMER3";
1311         };
1312
1313         pinctrl_timer4_default: timer4_default {
1314                 function = "TIMER4";
1315                 groups = "TIMER4";
1316         };
1317
1318         pinctrl_timer5_default: timer5_default {
1319                 function = "TIMER5";
1320                 groups = "TIMER5";
1321         };
1322
1323         pinctrl_timer6_default: timer6_default {
1324                 function = "TIMER6";
1325                 groups = "TIMER6";
1326         };
1327
1328         pinctrl_timer7_default: timer7_default {
1329                 function = "TIMER7";
1330                 groups = "TIMER7";
1331         };
1332
1333         pinctrl_timer8_default: timer8_default {
1334                 function = "TIMER8";
1335                 groups = "TIMER8";
1336         };
1337
1338         pinctrl_txd1_default: txd1_default {
1339                 function = "TXD1";
1340                 groups = "TXD1";
1341         };
1342
1343         pinctrl_txd2_default: txd2_default {
1344                 function = "TXD2";
1345                 groups = "TXD2";
1346         };
1347
1348         pinctrl_txd3_default: txd3_default {
1349                 function = "TXD3";
1350                 groups = "TXD3";
1351         };
1352
1353         pinctrl_txd4_default: txd4_default {
1354                 function = "TXD4";
1355                 groups = "TXD4";
1356         };
1357
1358         pinctrl_uart6_default: uart6_default {
1359                 function = "UART6";
1360                 groups = "UART6";
1361         };
1362
1363         pinctrl_usbcki_default: usbcki_default {
1364                 function = "USBCKI";
1365                 groups = "USBCKI";
1366         };
1367
1368         pinctrl_usb2h_default: usb2h_default {
1369                 function = "USB2H1";
1370                 groups = "USB2H1";
1371         };
1372
1373         pinctrl_usb2d_default: usb2d_default {
1374                 function = "USB2D1";
1375                 groups = "USB2D1";
1376         };
1377
1378         pinctrl_vgabios_rom_default: vgabios_rom_default {
1379                 function = "VGABIOS_ROM";
1380                 groups = "VGABIOS_ROM";
1381         };
1382
1383         pinctrl_vgahs_default: vgahs_default {
1384                 function = "VGAHS";
1385                 groups = "VGAHS";
1386         };
1387
1388         pinctrl_vgavs_default: vgavs_default {
1389                 function = "VGAVS";
1390                 groups = "VGAVS";
1391         };
1392
1393         pinctrl_vpi18_default: vpi18_default {
1394                 function = "VPI18";
1395                 groups = "VPI18";
1396         };
1397
1398         pinctrl_vpi24_default: vpi24_default {
1399                 function = "VPI24";
1400                 groups = "VPI24";
1401         };
1402
1403         pinctrl_vpi30_default: vpi30_default {
1404                 function = "VPI30";
1405                 groups = "VPI30";
1406         };
1407
1408         pinctrl_vpo12_default: vpo12_default {
1409                 function = "VPO12";
1410                 groups = "VPO12";
1411         };
1412
1413         pinctrl_vpo24_default: vpo24_default {
1414                 function = "VPO24";
1415                 groups = "VPO24";
1416         };
1417
1418         pinctrl_wdtrst1_default: wdtrst1_default {
1419                 function = "WDTRST1";
1420                 groups = "WDTRST1";
1421         };
1422
1423         pinctrl_wdtrst2_default: wdtrst2_default {
1424                 function = "WDTRST2";
1425                 groups = "WDTRST2";
1426         };
1427 };