arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /dts-v1/;
   3 #include "aspeed-g5.dtsi"
   4 #include <dt-bindings/gpio/aspeed-gpio.h>
   5
   6 / {
   7         model = "Ampere Mt. Jade BMC";
   8         compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
   9
  10         aliases {
  11                 /*
  12                  *  i2c bus 50-57 assigned to NVMe slot 0-7
  13                  */
  14                 i2c50 = &nvmeslot_0;
  15                 i2c51 = &nvmeslot_1;
  16                 i2c52 = &nvmeslot_2;
  17                 i2c53 = &nvmeslot_3;
  18                 i2c54 = &nvmeslot_4;
  19                 i2c55 = &nvmeslot_5;
  20                 i2c56 = &nvmeslot_6;
  21                 i2c57 = &nvmeslot_7;
  22
  23                 /*
  24                  *  i2c bus 60-67 assigned to NVMe slot 8-15
  25                  */
  26                 i2c60 = &nvmeslot_8;
  27                 i2c61 = &nvmeslot_9;
  28                 i2c62 = &nvmeslot_10;
  29                 i2c63 = &nvmeslot_11;
  30                 i2c64 = &nvmeslot_12;
  31                 i2c65 = &nvmeslot_13;
  32                 i2c66 = &nvmeslot_14;
  33                 i2c67 = &nvmeslot_15;
  34
  35                 /*
  36                  *  i2c bus 70-77 assigned to NVMe slot 16-23
  37                  */
  38                 i2c70 = &nvmeslot_16;
  39                 i2c71 = &nvmeslot_17;
  40                 i2c72 = &nvmeslot_18;
  41                 i2c73 = &nvmeslot_19;
  42                 i2c74 = &nvmeslot_20;
  43                 i2c75 = &nvmeslot_21;
  44                 i2c76 = &nvmeslot_22;
  45                 i2c77 = &nvmeslot_23;
  46
  47                 /*
  48                  *  i2c bus 80-81 assigned to NVMe M2 slot 0-1
  49                  */
  50                 i2c80 = &nvme_m2_0;
  51                 i2c81 = &nvme_m2_1;
  52         };
  53
  54         chosen {
  55                 stdout-path = &uart5;
  56                 bootargs = "console=ttyS4,115200 earlycon";
  57         };
  58
  59         memory@80000000 {
  60                 reg = <0x80000000 0x20000000>;
  61         };
  62
  63         reserved-memory {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67
  68                 vga_memory: framebuffer@9f000000 {
  69                         no-map;
  70                         reg = <0x9f000000 0x01000000>; /* 16M */
  71                 };
  72
  73                 gfx_memory: framebuffer {
  74                         size = <0x01000000>;
  75                         alignment = <0x01000000>;
  76                         compatible = "shared-dma-pool";
  77                         reusable;
  78                 };
  79
  80                 video_engine_memory: jpegbuffer {
  81                         size = <0x02000000>;    /* 32M */
  82                         alignment = <0x01000000>;
  83                         compatible = "shared-dma-pool";
  84                         reusable;
  85                 };
  86         };
  87
  88         leds {
  89                 compatible = "gpio-leds";
  90
  91                 fault {
  92                         gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
  93                 };
  94
  95                 identify {
  96                         gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
  97                 };
  98         };
  99
 100         gpioA0mux: mux-controller {
 101                 compatible = "gpio-mux";
 102                 #mux-control-cells = <0>;
 103                 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
 104         };
 105
 106         adc0mux: adc0mux {
 107                 compatible = "io-channel-mux";
 108                 io-channels = <&adc 0>;
 109                 #io-channel-cells = <1>;
 110                 io-channel-names = "parent";
 111                 mux-controls = <&gpioA0mux>;
 112                 channels = "s0", "s1";
 113         };
 114
 115         adc1mux: adc1mux {
 116                 compatible = "io-channel-mux";
 117                 io-channels = <&adc 1>;
 118                 #io-channel-cells = <1>;
 119                 io-channel-names = "parent";
 120                 mux-controls = <&gpioA0mux>;
 121                 channels = "s0", "s1";
 122         };
 123
 124         adc2mux: adc2mux {
 125                 compatible = "io-channel-mux";
 126                 io-channels = <&adc 2>;
 127                 #io-channel-cells = <1>;
 128                 io-channel-names = "parent";
 129                 mux-controls = <&gpioA0mux>;
 130                 channels = "s0", "s1";
 131         };
 132
 133         adc3mux: adc3mux {
 134                 compatible = "io-channel-mux";
 135                 io-channels = <&adc 3>;
 136                 #io-channel-cells = <1>;
 137                 io-channel-names = "parent";
 138                 mux-controls = <&gpioA0mux>;
 139                 channels = "s0", "s1";
 140         };
 141
 142         adc4mux: adc4mux {
 143                 compatible = "io-channel-mux";
 144                 io-channels = <&adc 4>;
 145                 #io-channel-cells = <1>;
 146                 io-channel-names = "parent";
 147                 mux-controls = <&gpioA0mux>;
 148                 channels = "s0", "s1";
 149         };
 150
 151         adc5mux: adc5mux {
 152                 compatible = "io-channel-mux";
 153                 io-channels = <&adc 5>;
 154                 #io-channel-cells = <1>;
 155                 io-channel-names = "parent";
 156                 mux-controls = <&gpioA0mux>;
 157                 channels = "s0", "s1";
 158         };
 159
 160         adc6mux: adc6mux {
 161                 compatible = "io-channel-mux";
 162                 io-channels = <&adc 6>;
 163                 #io-channel-cells = <1>;
 164                 io-channel-names = "parent";
 165                 mux-controls = <&gpioA0mux>;
 166                 channels = "s0", "s1";
 167         };
 168
 169         adc7mux: adc7mux {
 170                 compatible = "io-channel-mux";
 171                 io-channels = <&adc 7>;
 172                 #io-channel-cells = <1>;
 173                 io-channel-names = "parent";
 174                 mux-controls = <&gpioA0mux>;
 175                 channels = "s0", "s1";
 176         };
 177
 178         adc8mux: adc8mux {
 179                 compatible = "io-channel-mux";
 180                 io-channels = <&adc 8>;
 181                 #io-channel-cells = <1>;
 182                 io-channel-names = "parent";
 183                 mux-controls = <&gpioA0mux>;
 184                 channels = "s0", "s1";
 185         };
 186
 187         adc9mux: adc9mux {
 188                 compatible = "io-channel-mux";
 189                 io-channels = <&adc 9>;
 190                 #io-channel-cells = <1>;
 191                 io-channel-names = "parent";
 192                 mux-controls = <&gpioA0mux>;
 193                 channels = "s0", "s1";
 194         };
 195
 196         adc10mux: adc10mux {
 197                 compatible = "io-channel-mux";
 198                 io-channels = <&adc 10>;
 199                 #io-channel-cells = <1>;
 200                 io-channel-names = "parent";
 201                 mux-controls = <&gpioA0mux>;
 202                 channels = "s0", "s1";
 203         };
 204
 205         adc11mux: adc11mux {
 206                 compatible = "io-channel-mux";
 207                 io-channels = <&adc 11>;
 208                 #io-channel-cells = <1>;
 209                 io-channel-names = "parent";
 210                 mux-controls = <&gpioA0mux>;
 211                 channels = "s0", "s1";
 212         };
 213
 214         adc12mux: adc12mux {
 215                 compatible = "io-channel-mux";
 216                 io-channels = <&adc 12>;
 217                 #io-channel-cells = <1>;
 218                 io-channel-names = "parent";
 219                 mux-controls = <&gpioA0mux>;
 220                 channels = "s0", "s1";
 221         };
 222
 223         adc13mux: adc13mux {
 224                 compatible = "io-channel-mux";
 225                 io-channels = <&adc 13>;
 226                 #io-channel-cells = <1>;
 227                 io-channel-names = "parent";
 228                 mux-controls = <&gpioA0mux>;
 229                 channels = "s0", "s1";
 230         };
 231
 232         iio-hwmon {
 233                 compatible = "iio-hwmon";
 234                 io-channels = <&adc0mux 0>, <&adc0mux 1>,
 235                         <&adc1mux 0>, <&adc1mux 1>,
 236                         <&adc2mux 0>, <&adc2mux 1>,
 237                         <&adc3mux 0>, <&adc3mux 1>,
 238                         <&adc4mux 0>, <&adc4mux 1>,
 239                         <&adc5mux 0>, <&adc5mux 1>,
 240                         <&adc6mux 0>, <&adc6mux 1>,
 241                         <&adc7mux 0>, <&adc7mux 1>,
 242                         <&adc8mux 0>, <&adc8mux 1>,
 243                         <&adc9mux 0>, <&adc9mux 1>,
 244                         <&adc10mux 0>, <&adc10mux 1>,
 245                         <&adc11mux 0>, <&adc11mux 1>,
 246                         <&adc12mux 0>, <&adc12mux 1>,
 247                         <&adc13mux 0>, <&adc13mux 1>,
 248                         <&adc 14>, <&adc 15>;
 249         };
 250 };
 251
 252 &fmc {
 253         status = "okay";
 254         flash@0 {
 255                 status = "okay";
 256                 m25p,fast-read;
 257                 label = "bmc";
 258                 /* spi-max-frequency = <50000000>; */
 259 #include "openbmc-flash-layout-64.dtsi"
 260         };
 261
 262         flash@1 {
 263                 status = "okay";
 264                 m25p,fast-read;
 265                 label = "alt-bmc";
 266 #include "openbmc-flash-layout-64-alt.dtsi"
 267         };
 268 };
 269
 270 &spi1 {
 271         status = "okay";
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_spi1_default>;
 274
 275         flash@0 {
 276                 status = "okay";
 277                 m25p,fast-read;
 278                 label = "pnor";
 279                 /* spi-max-frequency = <100000000>; */
 280                 partitions {
 281                         compatible = "fixed-partitions";
 282                         #address-cells = <1>;
 283                         #size-cells = <1>;
 284                         uefi@400000 {
 285                                 reg = <0x400000 0x1C00000>;
 286                                 label = "pnor-uefi";
 287                         };
 288                 };
 289         };
 290 };
 291
 292 &uart1 {
 293         status = "okay";
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_txd1_default
 296                          &pinctrl_rxd1_default
 297                          &pinctrl_ncts1_default
 298                          &pinctrl_nrts1_default>;
 299 };
 300
 301 &uart2 {
 302         status = "okay";
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_txd2_default
 305                          &pinctrl_rxd2_default>;
 306 };
 307
 308 &uart3 {
 309         status = "okay";
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_txd3_default
 312                          &pinctrl_rxd3_default>;
 313 };
 314
 315 &uart4 {
 316         status = "okay";
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_txd4_default
 319                          &pinctrl_rxd4_default>;
 320 };
 321
 322 /* The BMC's uart */
 323 &uart5 {
 324         status = "okay";
 325 };
 326
 327 &mac0 {
 328         status = "okay";
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&pinctrl_rmii1_default>;
 331         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
 332                  <&syscon ASPEED_CLK_MAC1RCLK>;
 333         clock-names = "MACCLK", "RCLK";
 334         use-ncsi;
 335 };
 336
 337 &mac1 {
 338         status = "okay";
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
 341 };
 342
 343 &i2c0 {
 344         status = "okay";
 345 };
 346
 347 &i2c1 {
 348         status = "okay";
 349 };
 350
 351 &i2c2 {
 352         status = "okay";
 353 };
 354
 355 &i2c3 {
 356         status = "okay";
 357         eeprom@50 {
 358                 compatible = "microchip,24c64", "atmel,24c64";
 359                 reg = <0x50>;
 360                 pagesize = <32>;
 361         };
 362
 363         inlet_mem2: tmp175@28 {
 364                 compatible = "ti,tmp175";
 365                 reg = <0x28>;
 366         };
 367
 368         inlet_cpu: tmp175@29 {
 369                 compatible = "ti,tmp175";
 370                 reg = <0x29>;
 371         };
 372
 373         inlet_mem1: tmp175@2a {
 374                 compatible = "ti,tmp175";
 375                 reg = <0x2a>;
 376         };
 377
 378         outlet_cpu: tmp175@2b {
 379                 compatible = "ti,tmp175";
 380                 reg = <0x2b>;
 381         };
 382
 383         outlet1: tmp175@2c {
 384                 compatible = "ti,tmp175";
 385                 reg = <0x2c>;
 386         };
 387
 388         outlet2: tmp175@2d {
 389                 compatible = "ti,tmp175";
 390                 reg = <0x2d>;
 391         };
 392 };
 393
 394 &i2c4 {
 395         status = "okay";
 396         rtc@51 {
 397                 compatible = "nxp,pcf85063a";
 398                 reg = <0x51>;
 399         };
 400 };
 401
 402 &i2c5 {
 403         status = "okay";
 404         i2c-mux@70 {
 405                 compatible = "nxp,pca9548";
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 reg = <0x70>;
 409                 i2c-mux-idle-disconnect;
 410
 411                 nvmeslot_0_7: i2c@3 {
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         reg = <0x3>;
 415                 };
 416         };
 417
 418         i2c-mux@71 {
 419                 compatible = "nxp,pca9548";
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 reg = <0x71>;
 423                 i2c-mux-idle-disconnect;
 424
 425                 nvmeslot_8_15: i2c@4 {
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         reg = <0x4>;
 429                 };
 430
 431                 nvmeslot_16_23: i2c@3 {
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         reg = <0x3>;
 435                 };
 436
 437         };
 438
 439         i2c-mux@72 {
 440                 compatible = "nxp,pca9545";
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 reg = <0x72>;
 444                 i2c-mux-idle-disconnect;
 445
 446                 nvme_m2_0: i2c@0 {
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <0x0>;
 450                 };
 451
 452                 nvme_m2_1: i2c@1 {
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         reg = <0x1>;
 456                 };
 457         };
 458 };
 459
 460 &nvmeslot_0_7 {
 461         status = "okay";
 462
 463         i2c-mux@75 {
 464                 compatible = "nxp,pca9548";
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 reg = <0x75>;
 468                 i2c-mux-idle-disconnect;
 469
 470                 nvmeslot_0: i2c@0 {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         reg = <0x0>;
 474                 };
 475                 nvmeslot_1: i2c@1 {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         reg = <0x1>;
 479                 };
 480                 nvmeslot_2: i2c@2 {
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         reg = <0x2>;
 484                 };
 485                 nvmeslot_3: i2c@3 {
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                         reg = <0x3>;
 489                 };
 490                 nvmeslot_4: i2c@4 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <0x4>;
 494                 };
 495                 nvmeslot_5: i2c@5 {
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         reg = <0x5>;
 499                 };
 500                 nvmeslot_6: i2c@6 {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         reg = <0x6>;
 504                 };
 505                 nvmeslot_7: i2c@7 {
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                         reg = <0x7>;
 509                 };
 510
 511         };
 512 };
 513
 514 &nvmeslot_8_15 {
 515         status = "okay";
 516
 517         i2c-mux@75 {
 518                 compatible = "nxp,pca9548";
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 reg = <0x75>;
 522                 i2c-mux-idle-disconnect;
 523
 524                 nvmeslot_8: i2c@0 {
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         reg = <0x0>;
 528                 };
 529                 nvmeslot_9: i2c@1 {
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         reg = <0x1>;
 533                 };
 534                 nvmeslot_10: i2c@2 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         reg = <0x2>;
 538                 };
 539                 nvmeslot_11: i2c@3 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         reg = <0x3>;
 543                 };
 544                 nvmeslot_12: i2c@4 {
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         reg = <0x4>;
 548                 };
 549                 nvmeslot_13: i2c@5 {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         reg = <0x5>;
 553                 };
 554                 nvmeslot_14: i2c@6 {
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         reg = <0x6>;
 558                 };
 559                 nvmeslot_15: i2c@7 {
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         reg = <0x7>;
 563                 };
 564         };
 565 };
 566
 567 &nvmeslot_16_23 {
 568         status = "okay";
 569
 570         i2c-mux@75 {
 571                 compatible = "nxp,pca9548";
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 reg = <0x75>;
 575                 i2c-mux-idle-disconnect;
 576
 577                 nvmeslot_16: i2c@0 {
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         reg = <0x0>;
 581                 };
 582                 nvmeslot_17: i2c@1 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         reg = <0x1>;
 586                 };
 587                 nvmeslot_18: i2c@2 {
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         reg = <0x2>;
 591                 };
 592                 nvmeslot_19: i2c@3 {
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         reg = <0x3>;
 596                 };
 597                 nvmeslot_20: i2c@4 {
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                         reg = <0x4>;
 601                 };
 602                 nvmeslot_21: i2c@5 {
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         reg = <0x5>;
 606                 };
 607                 nvmeslot_22: i2c@6 {
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         reg = <0x6>;
 611                 };
 612                 nvmeslot_23: i2c@7 {
 613                         #address-cells = <1>;
 614                         #size-cells = <0>;
 615                         reg = <0x7>;
 616                 };
 617         };
 618 };
 619
 620 &i2c6 {
 621         status = "okay";
 622         psu@58 {
 623                 compatible = "pmbus";
 624                 reg = <0x58>;
 625         };
 626
 627         psu@59 {
 628                 compatible = "pmbus";
 629                 reg = <0x59>;
 630         };
 631 };
 632
 633 &i2c7 {
 634         status = "okay";
 635 };
 636
 637 &i2c8 {
 638         status = "okay";
 639 };
 640
 641 &i2c9 {
 642         status = "okay";
 643 };
 644
 645 &i2c10 {
 646         status = "okay";
 647         adm1278@10 {
 648                 compatible = "adi,adm1278";
 649                 reg = <0x10>;
 650         };
 651
 652         adm1278@11 {
 653                 compatible = "adi,adm1278";
 654                 reg = <0x11>;
 655         };
 656 };
 657
 658 &gfx {
 659         status = "okay";
 660         memory-region = <&gfx_memory>;
 661 };
 662
 663 &pinctrl {
 664         aspeed,external-nodes = <&gfx &lhc>;
 665 };
 666
 667 &pwm_tacho {
 668         status = "okay";
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
 671                         &pinctrl_pwm4_default &pinctrl_pwm5_default
 672                         &pinctrl_pwm6_default &pinctrl_pwm7_default>;
 673
 674         fan@0 {
 675                 reg = <0x02>;
 676                 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 677         };
 678
 679         fan@1 {
 680                 reg = <0x02>;
 681                 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 682         };
 683
 684         fan@2 {
 685                 reg = <0x03>;
 686                 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 687         };
 688
 689         fan@3 {
 690                 reg = <0x03>;
 691                 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 692         };
 693
 694         fan@4 {
 695                 reg = <0x04>;
 696                 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
 697         };
 698
 699         fan@5 {
 700                 reg = <0x04>;
 701                 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
 702         };
 703
 704         fan@6 {
 705                 reg = <0x05>;
 706                 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
 707         };
 708
 709         fan@7 {
 710                 reg = <0x05>;
 711                 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
 712         };
 713
 714         fan@8 {
 715                 reg = <0x06>;
 716                 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
 717         };
 718
 719         fan@9 {
 720                 reg = <0x06>;
 721                 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
 722         };
 723
 724         fan@10 {
 725                 reg = <0x07>;
 726                 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
 727         };
 728
 729         fan@11 {
 730                 reg = <0x07>;
 731                 aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
 732         };
 733
 734 };
 735
 736 &vhub {
 737         status = "okay";
 738 };
 739
 740 &adc {
 741         status = "okay";
 742 };
 743
 744 &video {
 745         status = "okay";
 746         memory-region = <&video_engine_memory>;
 747 };
 748
 749 &gpio {
 750         gpio-line-names =
 751         /*A0-A7*/       "","","","S0_BMC_SPECIAL_BOOT","","","","",
 752         /*B0-B7*/       "BMC_SELECT_EEPROM","","","",
 753                         "POWER_BUTTON","","","",
 754         /*C0-C7*/       "","","","","","","","",
 755         /*D0-D7*/       "","","","","","","","",
 756         /*E0-E7*/       "","","","","","","","",
 757         /*F0-F7*/       "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
 758                         "S1_DDR_SAVE","","",
 759         /*G0-G7*/       "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","",
 760                         "","",
 761         /*H0-H7*/       "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
 762         /*I0-I7*/       "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
 763                         "","","","","",
 764         /*J0-J7*/       "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
 765                         "","","","",
 766         /*K0-K7*/       "","","","","","","","",
 767         /*L0-L7*/       "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
 768         /*M0-M7*/       "","","","","","","","",
 769         /*N0-N7*/       "","","","","","","","",
 770         /*O0-O7*/       "","","","","","","","",
 771         /*P0-P7*/       "","","","","","","","",
 772         /*Q0-Q7*/       "","","","","","UID_BUTTON","","",
 773         /*R0-R7*/       "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
 774                         "OCP_MAIN_PWREN","RESET_BUTTON","","",
 775         /*S0-S7*/       "","","","","rtc-battery-voltage-read-enable","","","",
 776         /*T0-T7*/       "","","","","","","","",
 777         /*U0-U7*/       "","","","","","","","",
 778         /*V0-V7*/       "","","","","","","","",
 779         /*W0-W7*/       "","","","","","","","",
 780         /*X0-X7*/       "","","","","","","","",
 781         /*Y0-Y7*/       "","","","","","","","",
 782         /*Z0-Z7*/       "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
 783                         "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
 784         /*AA0-AA7*/     "","","","","","","","",
 785         /*AB0-AB7*/     "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
 786                         "S1_BMC_DDR_ADR","","","","",
 787         /*AC0-AC7*/     "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
 788                         "BMC_OCP_PG";
 789
 790         i2c4-o-en-hog {
 791                 gpio-hog;
 792                 gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
 793                 output-high;
 794                 line-name = "BMC_I2C4_O_EN";
 795         };
 796 };