arch/arm/boot/dts/aspeed-ast2600-evb.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 // Copyright 2019 IBM Corp.
   3
   4 /dts-v1/;
   5
   6 #include "aspeed-g6.dtsi"
   7 #include <dt-bindings/gpio/aspeed-gpio.h>
   8
   9 / {
  10         model = "AST2600 EVB";
  11         compatible = "aspeed,ast2600";
  12
  13         aliases {
  14                 serial4 = &uart5;
  15         };
  16
  17         chosen {
  18                 bootargs = "console=ttyS4,115200n8";
  19         };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 reg = <0x80000000 0x80000000>;
  24         };
  25
  26         reserved-memory {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges;
  30
  31                 video_engine_memory: video {
  32                         size = <0x04000000>;
  33                         alignment = <0x01000000>;
  34                         compatible = "shared-dma-pool";
  35                         reusable;
  36                 };
  37
  38                 gfx_memory: framebuffer {
  39                         size = <0x01000000>;
  40                         alignment = <0x01000000>;
  41                         compatible = "shared-dma-pool";
  42                         reusable;
  43                 };
  44         };
  45
  46         vcc_sdhci0: regulator-vcc-sdhci0 {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "SDHCI0 Vcc";
  49                 regulator-min-microvolt = <3300000>;
  50                 regulator-max-microvolt = <3300000>;
  51                 gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53         };
  54
  55         vccq_sdhci0: regulator-vccq-sdhci0 {
  56                 compatible = "regulator-gpio";
  57                 regulator-name = "SDHCI0 VccQ";
  58                 regulator-min-microvolt = <1800000>;
  59                 regulator-max-microvolt = <3300000>;
  60                 gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  61                 gpios-states = <1>;
  62                 states = <3300000 1>,
  63                          <1800000 0>;
  64         };
  65
  66         vcc_sdhci1: regulator-vcc-sdhci1 {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "SDHCI1 Vcc";
  69                 regulator-min-microvolt = <3300000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  72                 enable-active-high;
  73         };
  74
  75         vccq_sdhci1: regulator-vccq-sdhci1 {
  76                 compatible = "regulator-gpio";
  77                 regulator-name = "SDHCI1 VccQ";
  78                 regulator-min-microvolt = <1800000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  81                 gpios-states = <1>;
  82                 states = <3300000 1>,
  83                          <1800000 0>;
  84         };
  85 };
  86
  87 &mdio0 {
  88         status = "okay";
  89
  90         ethphy0: ethernet-phy@0 {
  91                 compatible = "ethernet-phy-ieee802.3-c22";
  92                 reg = <0>;
  93         };
  94 };
  95
  96 &mdio1 {
  97         status = "okay";
  98
  99         ethphy1: ethernet-phy@0 {
 100                 compatible = "ethernet-phy-ieee802.3-c22";
 101                 reg = <0>;
 102         };
 103 };
 104
 105 &mdio2 {
 106         status = "okay";
 107
 108         ethphy2: ethernet-phy@0 {
 109                 compatible = "ethernet-phy-ieee802.3-c22";
 110                 reg = <0>;
 111         };
 112 };
 113
 114 &mdio3 {
 115         status = "okay";
 116
 117         ethphy3: ethernet-phy@0 {
 118                 compatible = "ethernet-phy-ieee802.3-c22";
 119                 reg = <0>;
 120         };
 121 };
 122
 123 &mac0 {
 124         status = "okay";
 125
 126         phy-mode = "rgmii-rxid";
 127         phy-handle = <&ethphy0>;
 128
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_rgmii1_default>;
 131 };
 132
 133
 134 &mac1 {
 135         status = "okay";
 136
 137         phy-mode = "rgmii-rxid";
 138         phy-handle = <&ethphy1>;
 139
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_rgmii2_default>;
 142 };
 143
 144 &mac2 {
 145         status = "okay";
 146
 147         phy-mode = "rgmii";
 148         phy-handle = <&ethphy2>;
 149
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_rgmii3_default>;
 152 };
 153
 154 &mac3 {
 155         status = "okay";
 156
 157         phy-mode = "rgmii";
 158         phy-handle = <&ethphy3>;
 159
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_rgmii4_default>;
 162 };
 163
 164 &emmc_controller {
 165         status = "okay";
 166 };
 167
 168 &emmc {
 169         non-removable;
 170         bus-width = <4>;
 171         max-frequency = <100000000>;
 172         clk-phase-mmc-hs200 = <9>, <225>;
 173 };
 174
 175 &rtc {
 176         status = "okay";
 177 };
 178
 179 &fmc {
 180         status = "okay";
 181         flash@0 {
 182                 status = "okay";
 183                 m25p,fast-read;
 184                 label = "bmc";
 185                 spi-max-frequency = <50000000>;
 186 #include "openbmc-flash-layout-64.dtsi"
 187         };
 188 };
 189
 190 &spi1 {
 191         status = "okay";
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_spi1_default>;
 194
 195         flash@0 {
 196                 status = "okay";
 197                 m25p,fast-read;
 198                 label = "pnor";
 199                 spi-max-frequency = <100000000>;
 200         };
 201 };
 202
 203 &uart5 {
 204         // Workaround for A0
 205         compatible = "snps,dw-apb-uart";
 206 };
 207
 208 &i2c0 {
 209         status = "okay";
 210
 211         temp@2e {
 212                 compatible = "adi,adt7490";
 213                 reg = <0x2e>;
 214         };
 215 };
 216
 217 &i2c1 {
 218         status = "okay";
 219 };
 220
 221 &i2c2 {
 222         status = "okay";
 223 };
 224
 225 &i2c3 {
 226         status = "okay";
 227 };
 228
 229 &i2c4 {
 230         status = "okay";
 231 };
 232
 233 &i2c5 {
 234         status = "okay";
 235 };
 236
 237 &i2c6 {
 238         status = "okay";
 239 };
 240
 241 &i2c7 {
 242         status = "okay";
 243 };
 244
 245 &i2c8 {
 246         status = "okay";
 247 };
 248
 249 &i2c9 {
 250         status = "okay";
 251 };
 252
 253 &i2c12 {
 254         status = "okay";
 255 };
 256
 257 &i2c13 {
 258         status = "okay";
 259 };
 260
 261 &i2c14 {
 262         status = "okay";
 263 };
 264
 265 &i2c15 {
 266         status = "okay";
 267 };
 268
 269 &fsim0 {
 270         status = "okay";
 271 };
 272
 273 &ehci1 {
 274         status = "okay";
 275 };
 276
 277 &uhci {
 278         status = "okay";
 279 };
 280
 281 &sdc {
 282         status = "okay";
 283 };
 284
 285 /*
 286  * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
 287  * toggled by GPIO pins.
 288  * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the
 289  * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to
 290  * a 1.8v and a 3.3v power load switch that provides signal voltage to
 291  * sdhci0 bus.
 292  * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled.
 293  * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal
 294  * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled,
 295  * sdhci0 signal voltage becomes 1.8v.
 296  * AST2600-A2 EVB also supports toggling signal voltage for sdhci1.
 297  * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3
 298  * as power-switch-gpio.
 299  */
 300 &sdhci0 {
 301         status = "okay";
 302         bus-width = <4>;
 303         max-frequency = <100000000>;
 304         sdhci-drive-type = /bits/ 8 <3>;
 305         sdhci-caps-mask = <0x7 0x0>;
 306         sdhci,wp-inverted;
 307         vmmc-supply = <&vcc_sdhci0>;
 308         vqmmc-supply = <&vccq_sdhci0>;
 309         clk-phase-sd-hs = <7>, <200>;
 310 };
 311
 312 &sdhci1 {
 313         status = "okay";
 314         bus-width = <4>;
 315         max-frequency = <100000000>;
 316         sdhci-drive-type = /bits/ 8 <3>;
 317         sdhci-caps-mask = <0x7 0x0>;
 318         sdhci,wp-inverted;
 319         vmmc-supply = <&vcc_sdhci1>;
 320         vqmmc-supply = <&vccq_sdhci1>;
 321         clk-phase-sd-hs = <7>, <200>;
 322 };
 323
 324 &vhub {
 325         status = "okay";
 326         pinctrl-names = "default";
 327 };
 328
 329 &video {
 330         status = "okay";
 331         memory-region = <&video_engine_memory>;
 332 };
 333
 334 &gfx {
 335         status = "okay";
 336         memory-region = <&gfx_memory>;
 337 };