arch/arm/boot/dts/artpec6.dtsi

   1 /*
   2  * Device Tree Source for the Axis ARTPEC-6 SoC
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/dma/nbpfaxi.h>
  45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "axis,artpec6";
  50         interrupt-parent = <&intc>;
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a9";
  59                         reg = <0>;
  60                         next-level-cache = <&pl310>;
  61                 };
  62
  63                 cpu1: cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a9";
  66                         reg = <1>;
  67                         next-level-cache = <&pl310>;
  68                 };
  69         };
  70
  71         syscon: syscon@f8000000 {
  72                 compatible = "axis,artpec6-syscon", "syscon";
  73                 reg = <0xf8000000 0x48>;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-0.2", "arm,psci";
  78                 method = "smc";
  79                 psci_version = <0x84000000>;
  80                 cpu_on = <0x84000003>;
  81                 system_reset = <0x84000009>;
  82         };
  83
  84         scu@faf00000 {
  85                 compatible = "arm,cortex-a9-scu";
  86                 reg = <0xfaf00000 0x58>;
  87         };
  88
  89         /* Main external clock driving CPU and peripherals */
  90         ext_clk: ext_clk {
  91                 #clock-cells = <0>;
  92                 compatible = "fixed-clock";
  93                 clock-frequency = <50000000>;
  94         };
  95
  96         eth_phy_ref_clk: eth_phy_ref_clk {
  97                 #clock-cells = <0>;
  98                 compatible = "fixed-clock";
  99                 clock-frequency = <125000000>;
 100         };
 101
 102         clkctrl: clkctrl@f8000000 {
 103                 #clock-cells = <1>;
 104                 compatible = "axis,artpec6-clkctrl";
 105                 reg = <0xf8000000 0x48>;
 106                 clocks = <&ext_clk>;
 107                 clock-names = "sys_refclk";
 108         };
 109
 110         gtimer@faf00200 {
 111                 compatible = "arm,cortex-a9-global-timer";
 112                 reg = <0xfaf00200 0x20>;
 113                 interrupts = <GIC_PPI 11 0xf01>;
 114                 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
 115         };
 116
 117         timer@faf00600 {
 118                 compatible = "arm,cortex-a9-twd-timer";
 119                 reg = <0xfaf00600 0x20>;
 120                 interrupts = <GIC_PPI 13 0xf04>;
 121                 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
 122                 status = "disabled";
 123         };
 124
 125         intc: interrupt-controller@faf01000 {
 126                 interrupt-controller;
 127                 compatible = "arm,cortex-a9-gic";
 128                 #interrupt-cells = <3>;
 129                 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
 130         };
 131
 132         pl310: cache-controller@faf10000 {
 133                 compatible = "arm,pl310-cache";
 134                 cache-unified;
 135                 cache-level = <2>;
 136                 reg = <0xfaf10000 0x1000>;
 137                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 138                 arm,data-latency = <1 1 1>;
 139                 arm,tag-latency = <1 1 1>;
 140                 arm,filter-ranges = <0x0 0x80000000>;
 141                 arm,double-linefill = <1>;
 142                 arm,double-linefill-incr = <0>;
 143                 arm,double-linefill-wrap = <0>;
 144                 prefetch-data = <1>;
 145                 prefetch-instr = <1>;
 146                 arm,prefetch-offset = <0>;
 147                 arm,prefetch-drop = <1>;
 148         };
 149
 150         pmu {
 151                 compatible = "arm,cortex-a9-pmu";
 152                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 153                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 154                 interrupt-affinity = <&cpu0>, <&cpu1>;
 155         };
 156
 157         /*
 158          * Both pci nodes cannot be enabled at the same time,
 159          * leave the unwanted node as disabled.
 160          */
 161         pcie: pcie@f8050000 {
 162                 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
 163                 reg = <0xf8050000 0x2000
 164                        0xf8040000 0x1000
 165                        0xc0000000 0x2000>;
 166                 reg-names = "dbi", "phy", "config";
 167                 #address-cells = <3>;
 168                 #size-cells = <2>;
 169                 device_type = "pci";
 170                           /* downstream I/O */
 171                 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
 172                           /* non-prefetchable memory */
 173                           0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
 174                 num-lanes = <2>;
 175                 bus-range = <0x00 0xff>;
 176                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 177                 interrupt-names = "msi";
 178                 #interrupt-cells = <1>;
 179                 interrupt-map-mask = <0 0 0 0x7>;
 180                 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 181                                 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 182                                 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 183                                 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 184                 axis,syscon-pcie = <&syscon>;
 185                 status = "disabled";
 186         };
 187
 188         pcie_ep: pcie_ep@f8050000 {
 189                 compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
 190                 reg = <0xf8050000 0x2000
 191                        0xf8051000 0x2000
 192                        0xf8040000 0x1000
 193                        0xc0000000 0x20000000>;
 194                 reg-names = "dbi", "dbi2", "phy", "addr_space";
 195                 num-ib-windows = <6>;
 196                 num-ob-windows = <2>;
 197                 num-lanes = <2>;
 198                 axis,syscon-pcie = <&syscon>;
 199                 status = "disabled";
 200         };
 201
 202         pinctrl: pinctrl@f801d000 {
 203                 compatible = "axis,artpec6-pinctrl";
 204                 reg = <0xf801d000 0x400>;
 205
 206                 pinctrl_uart0: uart0grp {
 207                         function = "uart0";
 208                         groups = "uart0grp2";
 209                         bias-pull-up;
 210                 };
 211                 pinctrl_uart1: uart1grp {
 212                         function = "uart1";
 213                         groups = "uart1grp0";
 214                         bias-pull-up;
 215                 };
 216                 pinctrl_uart2: uart2grp {
 217                         function = "uart2";
 218                         groups = "uart2grp1";
 219                         bias-pull-up;
 220                 };
 221                 pinctrl_uart3: uart3grp {
 222                         function = "uart3";
 223                         groups = "uart3grp0";
 224                         bias-pull-up;
 225                 };
 226         };
 227
 228         amba@0 {
 229                 compatible = "simple-bus";
 230                 #address-cells = <0x1>;
 231                 #size-cells = <0x1>;
 232                 ranges;
 233                 dma-ranges;
 234
 235                 crypto@f4264000 {
 236                         compatible = "axis,artpec6-crypto";
 237                         reg = <0xf4264000 0x4000>;
 238                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 239                 };
 240
 241                 dma0: dma@f8019000 {
 242                         compatible = "renesas,nbpfaxi64dmac8b16";
 243                         reg = <0xf8019000 0x400>;
 244                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
 245                                      <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 253                         interrupt-names = "error",
 254                                           "ch0", "ch1", "ch2", "ch3",
 255                                           "ch4", "ch5", "ch6", "ch7",
 256                                           "ch8", "ch9", "ch10", "ch12",
 257                                           "ch12", "ch13", "ch14", "ch15";
 258                         clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
 259                         #dma-cells = <2>;
 260                         dma-channels = <8>;
 261                         dma-requests = <8>;
 262                 };
 263                 dma1: dma@f8019400 {
 264                         compatible = "renesas,nbpfaxi64dmac8b16";
 265                         reg = <0xf8019400 0x400>;
 266                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
 267                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 268                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 269                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 271                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 275                         interrupt-names = "error",
 276                                           "ch0", "ch1", "ch2", "ch3",
 277                                           "ch4", "ch5", "ch6", "ch7",
 278                                           "ch8", "ch9", "ch10", "ch12",
 279                                           "ch12", "ch13", "ch14", "ch15";
 280                         clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
 281                         #dma-cells = <2>;
 282                         dma-channels = <8>;
 283                         dma-requests = <8>;
 284                 };
 285
 286                 ethernet: ethernet@f8010000 {
 287                         clock-names = "stmmaceth", "ptp_ref";
 288                         clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
 289                                 <&clkctrl ARTPEC6_CLK_PTP_REF>;
 290                         compatible = "snps,dwmac-4.10a", "snps,dwmac";
 291                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 293                         interrupt-names = "macirq", "eth_lpi";
 294                         reg = <0xf8010000 0x4000>;
 295
 296                         snps,axi-config = <&stmmac_axi_setup>;
 297                         snps,mtl-rx-config = <&mtl_rx_setup>;
 298                         snps,mtl-tx-config = <&mtl_tx_setup>;
 299
 300                         snps,txpbl = <8>;
 301                         snps,rxpbl = <2>;
 302                         snps,aal;
 303                         snps,tso;
 304
 305                         status = "disabled";
 306
 307                         stmmac_axi_setup: stmmac-axi-config {
 308                                 snps,wr_osr_lmt = <1>;
 309                                 snps,rd_osr_lmt = <15>;
 310                                 /* If FB is disabled, the AXI master chooses
 311                                  * a burst length of any value less than the
 312                                  * maximum enabled burst length
 313                                  * (all lesser burst length enables are redundant).
 314                                  */
 315                                 snps,blen = <0 0 0 0 16 0 0>;
 316                         };
 317
 318                         mtl_rx_setup: rx-queues-config {
 319                                 snps,rx-queues-to-use = <1>;
 320                                 queue0 {};
 321                         };
 322
 323                         mtl_tx_setup: tx-queues-config {
 324                                 snps,tx-queues-to-use = <2>;
 325                                 queue0 {};
 326                                 queue1 {};
 327                         };
 328                 };
 329
 330                 uart0: serial@f8036000 {
 331                         compatible = "arm,pl011", "arm,primecell";
 332                         reg = <0xf8036000 0x1000>;
 333                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
 335                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
 336                         clock-names = "uart_clk", "apb_pclk";
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&pinctrl_uart0>;
 339                         dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
 340                                <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
 341                         dma-names = "rx", "tx";
 342                         status = "disabled";
 343                 };
 344                 uart1: serial@f8037000 {
 345                         compatible = "arm,pl011", "arm,primecell";
 346                         reg = <0xf8037000 0x1000>;
 347                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
 349                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
 350                         clock-names = "uart_clk", "apb_pclk";
 351                         pinctrl-names = "default";
 352                         pinctrl-0 = <&pinctrl_uart1>;
 353                         dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
 354                                <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
 355                         dma-names = "rx", "tx";
 356                         status = "disabled";
 357                 };
 358                 uart2: serial@f8038000 {
 359                         compatible = "arm,pl011", "arm,primecell";
 360                         reg = <0xf8038000 0x1000>;
 361                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
 363                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
 364                         clock-names = "uart_clk", "apb_pclk";
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&pinctrl_uart2>;
 367                         dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
 368                                <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
 369                         dma-names = "rx", "tx";
 370                         status = "disabled";
 371                 };
 372                 uart3: serial@f8039000 {
 373                         compatible = "arm,pl011", "arm,primecell";
 374                         reg = <0xf8039000 0x1000>;
 375                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
 377                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
 378                         clock-names = "uart_clk", "apb_pclk";
 379                         pinctrl-names = "default";
 380                         pinctrl-0 = <&pinctrl_uart3>;
 381                         dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
 382                                <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
 383                         dma-names = "rx", "tx";
 384                         status = "disabled";
 385                 };
 386         };
 387 };