arch/arm/boot/dts/armada-xp-mv78460.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Marvell Armada XP family SoC
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * Contains definitions specific to the Armada XP MV78460 SoC that are not
  10  * common to all Armada XP SoCs.
  11  */
  12
  13 #include "armada-xp.dtsi"
  14
  15 / {
  16         model = "Marvell Armada XP MV78460 SoC";
  17         compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  18
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23         };
  24
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 enable-method = "marvell,armada-xp-smp";
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "marvell,sheeva-v7";
  34                         reg = <0>;
  35                         clocks = <&cpuclk 0>;
  36                         clock-latency = <1000000>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "marvell,sheeva-v7";
  42                         reg = <1>;
  43                         clocks = <&cpuclk 1>;
  44                         clock-latency = <1000000>;
  45                 };
  46
  47                 cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "marvell,sheeva-v7";
  50                         reg = <2>;
  51                         clocks = <&cpuclk 2>;
  52                         clock-latency = <1000000>;
  53                 };
  54
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "marvell,sheeva-v7";
  58                         reg = <3>;
  59                         clocks = <&cpuclk 3>;
  60                         clock-latency = <1000000>;
  61                 };
  62         };
  63
  64         soc {
  65                 /*
  66                  * MV78460 has 4 PCIe units Gen2.0: Two units can be
  67                  * configured as x4 or quad x1 lanes. Two units are
  68                  * x4/x1.
  69                  */
  70                 pciec: pcie@82000000 {
  71                         compatible = "marvell,armada-xp-pcie";
  72                         status = "disabled";
  73                         device_type = "pci";
  74
  75                         #address-cells = <3>;
  76                         #size-cells = <2>;
  77
  78                         msi-parent = <&mpic>;
  79                         bus-range = <0x00 0xff>;
  80
  81                         ranges =
  82                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  83                                 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  84                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
  85                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
  86                                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
  87                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
  88                                 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
  89                                 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
  90                                 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
  91                                 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
  92                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  93                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
  94                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
  95                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
  96                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
  97                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
  98                                 0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
  99                                 0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 100
 101                                 0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 102                                 0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 103                                 0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 104                                 0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 105                                 0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 106                                 0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 107                                 0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 108                                 0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 109
 110                                 0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 111                                 0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 112
 113                                 0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 114                                 0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 115
 116                         pcie1: pcie@1,0 {
 117                                 device_type = "pci";
 118                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 119                                 reg = <0x0800 0 0 0 0>;
 120                                 #address-cells = <3>;
 121                                 #size-cells = <2>;
 122                                 interrupt-names = "intx";
 123                                 interrupts-extended = <&mpic 58>;
 124                                 #interrupt-cells = <1>;
 125                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 126                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 127                                 bus-range = <0x00 0xff>;
 128                                 interrupt-map-mask = <0 0 0 7>;
 129                                 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
 130                                                 <0 0 0 2 &pcie1_intc 1>,
 131                                                 <0 0 0 3 &pcie1_intc 2>,
 132                                                 <0 0 0 4 &pcie1_intc 3>;
 133                                 marvell,pcie-port = <0>;
 134                                 marvell,pcie-lane = <0>;
 135                                 clocks = <&gateclk 5>;
 136                                 status = "disabled";
 137
 138                                 pcie1_intc: interrupt-controller {
 139                                         interrupt-controller;
 140                                         #interrupt-cells = <1>;
 141                                 };
 142                         };
 143
 144                         pcie2: pcie@2,0 {
 145                                 device_type = "pci";
 146                                 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 147                                 reg = <0x1000 0 0 0 0>;
 148                                 #address-cells = <3>;
 149                                 #size-cells = <2>;
 150                                 interrupt-names = "intx";
 151                                 interrupts-extended = <&mpic 59>;
 152                                 #interrupt-cells = <1>;
 153                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 154                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 155                                 bus-range = <0x00 0xff>;
 156                                 interrupt-map-mask = <0 0 0 7>;
 157                                 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
 158                                                 <0 0 0 2 &pcie2_intc 1>,
 159                                                 <0 0 0 3 &pcie2_intc 2>,
 160                                                 <0 0 0 4 &pcie2_intc 3>;
 161                                 marvell,pcie-port = <0>;
 162                                 marvell,pcie-lane = <1>;
 163                                 clocks = <&gateclk 6>;
 164                                 status = "disabled";
 165
 166                                 pcie2_intc: interrupt-controller {
 167                                         interrupt-controller;
 168                                         #interrupt-cells = <1>;
 169                                 };
 170                         };
 171
 172                         pcie3: pcie@3,0 {
 173                                 device_type = "pci";
 174                                 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 175                                 reg = <0x1800 0 0 0 0>;
 176                                 #address-cells = <3>;
 177                                 #size-cells = <2>;
 178                                 interrupt-names = "intx";
 179                                 interrupts-extended = <&mpic 60>;
 180                                 #interrupt-cells = <1>;
 181                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 182                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 183                                 bus-range = <0x00 0xff>;
 184                                 interrupt-map-mask = <0 0 0 7>;
 185                                 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
 186                                                 <0 0 0 2 &pcie3_intc 1>,
 187                                                 <0 0 0 3 &pcie3_intc 2>,
 188                                                 <0 0 0 4 &pcie3_intc 3>;
 189                                 marvell,pcie-port = <0>;
 190                                 marvell,pcie-lane = <2>;
 191                                 clocks = <&gateclk 7>;
 192                                 status = "disabled";
 193
 194                                 pcie3_intc: interrupt-controller {
 195                                         interrupt-controller;
 196                                         #interrupt-cells = <1>;
 197                                 };
 198                         };
 199
 200                         pcie4: pcie@4,0 {
 201                                 device_type = "pci";
 202                                 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 203                                 reg = <0x2000 0 0 0 0>;
 204                                 #address-cells = <3>;
 205                                 #size-cells = <2>;
 206                                 interrupt-names = "intx";
 207                                 interrupts-extended = <&mpic 61>;
 208                                 #interrupt-cells = <1>;
 209                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 210                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 211                                 bus-range = <0x00 0xff>;
 212                                 interrupt-map-mask = <0 0 0 7>;
 213                                 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
 214                                                 <0 0 0 2 &pcie4_intc 1>,
 215                                                 <0 0 0 3 &pcie4_intc 2>,
 216                                                 <0 0 0 4 &pcie4_intc 3>;
 217                                 marvell,pcie-port = <0>;
 218                                 marvell,pcie-lane = <3>;
 219                                 clocks = <&gateclk 8>;
 220                                 status = "disabled";
 221
 222                                 pcie4_intc: interrupt-controller {
 223                                         interrupt-controller;
 224                                         #interrupt-cells = <1>;
 225                                 };
 226                         };
 227
 228                         pcie5: pcie@5,0 {
 229                                 device_type = "pci";
 230                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 231                                 reg = <0x2800 0 0 0 0>;
 232                                 #address-cells = <3>;
 233                                 #size-cells = <2>;
 234                                 interrupt-names = "intx";
 235                                 interrupts-extended = <&mpic 62>;
 236                                 #interrupt-cells = <1>;
 237                                 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 238                                           0x81000000 0 0 0x81000000 0x5 0 1 0>;
 239                                 bus-range = <0x00 0xff>;
 240                                 interrupt-map-mask = <0 0 0 7>;
 241                                 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
 242                                                 <0 0 0 2 &pcie5_intc 1>,
 243                                                 <0 0 0 3 &pcie5_intc 2>,
 244                                                 <0 0 0 4 &pcie5_intc 3>;
 245                                 marvell,pcie-port = <1>;
 246                                 marvell,pcie-lane = <0>;
 247                                 clocks = <&gateclk 9>;
 248                                 status = "disabled";
 249
 250                                 pcie5_intc: interrupt-controller {
 251                                         interrupt-controller;
 252                                         #interrupt-cells = <1>;
 253                                 };
 254                         };
 255
 256                         pcie6: pcie@6,0 {
 257                                 device_type = "pci";
 258                                 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 259                                 reg = <0x3000 0 0 0 0>;
 260                                 #address-cells = <3>;
 261                                 #size-cells = <2>;
 262                                 interrupt-names = "intx";
 263                                 interrupts-extended = <&mpic 63>;
 264                                 #interrupt-cells = <1>;
 265                                 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 266                                           0x81000000 0 0 0x81000000 0x6 0 1 0>;
 267                                 bus-range = <0x00 0xff>;
 268                                 interrupt-map-mask = <0 0 0 7>;
 269                                 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
 270                                                 <0 0 0 2 &pcie6_intc 1>,
 271                                                 <0 0 0 3 &pcie6_intc 2>,
 272                                                 <0 0 0 4 &pcie6_intc 3>;
 273                                 marvell,pcie-port = <1>;
 274                                 marvell,pcie-lane = <1>;
 275                                 clocks = <&gateclk 10>;
 276                                 status = "disabled";
 277
 278                                 pcie6_intc: interrupt-controller {
 279                                         interrupt-controller;
 280                                         #interrupt-cells = <1>;
 281                                 };
 282                         };
 283
 284                         pcie7: pcie@7,0 {
 285                                 device_type = "pci";
 286                                 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 287                                 reg = <0x3800 0 0 0 0>;
 288                                 #address-cells = <3>;
 289                                 #size-cells = <2>;
 290                                 interrupt-names = "intx";
 291                                 interrupts-extended = <&mpic 64>;
 292                                 #interrupt-cells = <1>;
 293                                 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 294                                           0x81000000 0 0 0x81000000 0x7 0 1 0>;
 295                                 bus-range = <0x00 0xff>;
 296                                 interrupt-map-mask = <0 0 0 7>;
 297                                 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
 298                                                 <0 0 0 2 &pcie7_intc 1>,
 299                                                 <0 0 0 3 &pcie7_intc 2>,
 300                                                 <0 0 0 4 &pcie7_intc 3>;
 301                                 marvell,pcie-port = <1>;
 302                                 marvell,pcie-lane = <2>;
 303                                 clocks = <&gateclk 11>;
 304                                 status = "disabled";
 305
 306                                 pcie7_intc: interrupt-controller {
 307                                         interrupt-controller;
 308                                         #interrupt-cells = <1>;
 309                                 };
 310                         };
 311
 312                         pcie8: pcie@8,0 {
 313                                 device_type = "pci";
 314                                 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 315                                 reg = <0x4000 0 0 0 0>;
 316                                 #address-cells = <3>;
 317                                 #size-cells = <2>;
 318                                 interrupt-names = "intx";
 319                                 interrupts-extended = <&mpic 65>;
 320                                 #interrupt-cells = <1>;
 321                                 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 322                                           0x81000000 0 0 0x81000000 0x8 0 1 0>;
 323                                 bus-range = <0x00 0xff>;
 324                                 interrupt-map-mask = <0 0 0 7>;
 325                                 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
 326                                                 <0 0 0 2 &pcie8_intc 1>,
 327                                                 <0 0 0 3 &pcie8_intc 2>,
 328                                                 <0 0 0 4 &pcie8_intc 3>;
 329                                 marvell,pcie-port = <1>;
 330                                 marvell,pcie-lane = <3>;
 331                                 clocks = <&gateclk 12>;
 332                                 status = "disabled";
 333
 334                                 pcie8_intc: interrupt-controller {
 335                                         interrupt-controller;
 336                                         #interrupt-cells = <1>;
 337                                 };
 338                         };
 339
 340                         pcie9: pcie@9,0 {
 341                                 device_type = "pci";
 342                                 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 343                                 reg = <0x4800 0 0 0 0>;
 344                                 #address-cells = <3>;
 345                                 #size-cells = <2>;
 346                                 interrupt-names = "intx";
 347                                 interrupts-extended = <&mpic 99>;
 348                                 #interrupt-cells = <1>;
 349                                 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 350                                           0x81000000 0 0 0x81000000 0x9 0 1 0>;
 351                                 bus-range = <0x00 0xff>;
 352                                 interrupt-map-mask = <0 0 0 7>;
 353                                 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
 354                                                 <0 0 0 2 &pcie9_intc 1>,
 355                                                 <0 0 0 3 &pcie9_intc 2>,
 356                                                 <0 0 0 4 &pcie9_intc 3>;
 357                                 marvell,pcie-port = <2>;
 358                                 marvell,pcie-lane = <0>;
 359                                 clocks = <&gateclk 26>;
 360                                 status = "disabled";
 361
 362                                 pcie9_intc: interrupt-controller {
 363                                         interrupt-controller;
 364                                         #interrupt-cells = <1>;
 365                                 };
 366                         };
 367
 368                         pcie10: pcie@a,0 {
 369                                 device_type = "pci";
 370                                 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 371                                 reg = <0x5000 0 0 0 0>;
 372                                 #address-cells = <3>;
 373                                 #size-cells = <2>;
 374                                 interrupt-names = "intx";
 375                                 interrupts-extended = <&mpic 103>;
 376                                 #interrupt-cells = <1>;
 377                                 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 378                                           0x81000000 0 0 0x81000000 0xa 0 1 0>;
 379                                 bus-range = <0x00 0xff>;
 380                                 interrupt-map-mask = <0 0 0 7>;
 381                                 interrupt-map = <0 0 0 1 &pcie10_intc 0>,
 382                                                 <0 0 0 2 &pcie10_intc 1>,
 383                                                 <0 0 0 3 &pcie10_intc 2>,
 384                                                 <0 0 0 4 &pcie10_intc 3>;
 385                                 marvell,pcie-port = <3>;
 386                                 marvell,pcie-lane = <0>;
 387                                 clocks = <&gateclk 27>;
 388                                 status = "disabled";
 389
 390                                 pcie10_intc: interrupt-controller {
 391                                         interrupt-controller;
 392                                         #interrupt-cells = <1>;
 393                                 };
 394                         };
 395                 };
 396
 397                 internal-regs {
 398                         gpio0: gpio@18100 {
 399                                 compatible = "marvell,armada-370-gpio",
 400                                              "marvell,orion-gpio";
 401                                 reg = <0x18100 0x40>, <0x181c0 0x08>;
 402                                 reg-names = "gpio", "pwm";
 403                                 ngpios = <32>;
 404                                 gpio-controller;
 405                                 #gpio-cells = <2>;
 406                                 #pwm-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 interrupts = <82>, <83>, <84>, <85>;
 410                                 clocks = <&coreclk 0>;
 411                         };
 412
 413                         gpio1: gpio@18140 {
 414                                 compatible = "marvell,armada-370-gpio",
 415                                              "marvell,orion-gpio";
 416                                 reg = <0x18140 0x40>, <0x181c8 0x08>;
 417                                 reg-names = "gpio", "pwm";
 418                                 ngpios = <32>;
 419                                 gpio-controller;
 420                                 #gpio-cells = <2>;
 421                                 #pwm-cells = <2>;
 422                                 interrupt-controller;
 423                                 #interrupt-cells = <2>;
 424                                 interrupts = <87>, <88>, <89>, <90>;
 425                                 clocks = <&coreclk 0>;
 426                         };
 427
 428                         gpio2: gpio@18180 {
 429                                 compatible = "marvell,armada-370-gpio",
 430                                              "marvell,orion-gpio";
 431                                 reg = <0x18180 0x40>;
 432                                 ngpios = <3>;
 433                                 gpio-controller;
 434                                 #gpio-cells = <2>;
 435                                 interrupt-controller;
 436                                 #interrupt-cells = <2>;
 437                                 interrupts = <91>;
 438                         };
 439
 440                         eth3: ethernet@34000 {
 441                                 compatible = "marvell,armada-xp-neta";
 442                                 reg = <0x34000 0x4000>;
 443                                 interrupts = <14>;
 444                                 clocks = <&gateclk 1>;
 445                                 status = "disabled";
 446                         };
 447                 };
 448         };
 449 };
 450
 451 &pinctrl {
 452         compatible = "marvell,mv78460-pinctrl";
 453 };