GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree Include file for Marvell Armada XP family SoC
4  *
5  * Copyright (C) 2012 Marvell
6  *
7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8  *
9  * Contains definitions specific to the Armada XP MV78230 SoC that are not
10  * common to all Armada XP SoCs.
11  */
12
13 #include "armada-xp.dtsi"
14
15 / {
16         model = "Marvell Armada XP MV78230 SoC";
17         compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
18
19         aliases {
20                 gpio0 = &gpio0;
21                 gpio1 = &gpio1;
22         };
23
24         cpus {
25                 #address-cells = <1>;
26                 #size-cells = <0>;
27                 enable-method = "marvell,armada-xp-smp";
28
29                 cpu@0 {
30                         device_type = "cpu";
31                         compatible = "marvell,sheeva-v7";
32                         reg = <0>;
33                         clocks = <&cpuclk 0>;
34                         clock-latency = <1000000>;
35                 };
36
37                 cpu@1 {
38                         device_type = "cpu";
39                         compatible = "marvell,sheeva-v7";
40                         reg = <1>;
41                         clocks = <&cpuclk 1>;
42                         clock-latency = <1000000>;
43                 };
44         };
45
46         soc {
47                 /*
48                  * MV78230 has 2 PCIe units Gen2.0: One unit can be
49                  * configured as x4 or quad x1 lanes. One unit is
50                  * x1 only.
51                  */
52                 pciec: pcie@82000000 {
53                         compatible = "marvell,armada-xp-pcie";
54                         status = "disabled";
55                         device_type = "pci";
56
57                         #address-cells = <3>;
58                         #size-cells = <2>;
59
60                         msi-parent = <&mpic>;
61                         bus-range = <0x00 0xff>;
62
63                         ranges =
64                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
65                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
66                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
67                                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
68                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
69                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
71                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
73                                 0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74                                 0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
75                                 0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76                                 0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
77                                 0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78                                 0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;
79
80                         pcie1: pcie@1,0 {
81                                 device_type = "pci";
82                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83                                 reg = <0x0800 0 0 0 0>;
84                                 #address-cells = <3>;
85                                 #size-cells = <2>;
86                                 #interrupt-cells = <1>;
87                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
88                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
89                                 bus-range = <0x00 0xff>;
90                                 interrupt-map-mask = <0 0 0 0>;
91                                 interrupt-map = <0 0 0 0 &mpic 58>;
92                                 marvell,pcie-port = <0>;
93                                 marvell,pcie-lane = <0>;
94                                 clocks = <&gateclk 5>;
95                                 status = "disabled";
96                         };
97
98                         pcie2: pcie@2,0 {
99                                 device_type = "pci";
100                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
101                                 reg = <0x1000 0 0 0 0>;
102                                 #address-cells = <3>;
103                                 #size-cells = <2>;
104                                 #interrupt-cells = <1>;
105                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
106                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
107                                 bus-range = <0x00 0xff>;
108                                 interrupt-map-mask = <0 0 0 0>;
109                                 interrupt-map = <0 0 0 0 &mpic 59>;
110                                 marvell,pcie-port = <0>;
111                                 marvell,pcie-lane = <1>;
112                                 clocks = <&gateclk 6>;
113                                 status = "disabled";
114                         };
115
116                         pcie3: pcie@3,0 {
117                                 device_type = "pci";
118                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
119                                 reg = <0x1800 0 0 0 0>;
120                                 #address-cells = <3>;
121                                 #size-cells = <2>;
122                                 #interrupt-cells = <1>;
123                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
124                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
125                                 bus-range = <0x00 0xff>;
126                                 interrupt-map-mask = <0 0 0 0>;
127                                 interrupt-map = <0 0 0 0 &mpic 60>;
128                                 marvell,pcie-port = <0>;
129                                 marvell,pcie-lane = <2>;
130                                 clocks = <&gateclk 7>;
131                                 status = "disabled";
132                         };
133
134                         pcie4: pcie@4,0 {
135                                 device_type = "pci";
136                                 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
137                                 reg = <0x2000 0 0 0 0>;
138                                 #address-cells = <3>;
139                                 #size-cells = <2>;
140                                 #interrupt-cells = <1>;
141                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
142                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
143                                 bus-range = <0x00 0xff>;
144                                 interrupt-map-mask = <0 0 0 0>;
145                                 interrupt-map = <0 0 0 0 &mpic 61>;
146                                 marvell,pcie-port = <0>;
147                                 marvell,pcie-lane = <3>;
148                                 clocks = <&gateclk 8>;
149                                 status = "disabled";
150                         };
151
152                         pcie5: pcie@5,0 {
153                                 device_type = "pci";
154                                 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
155                                 reg = <0x2800 0 0 0 0>;
156                                 #address-cells = <3>;
157                                 #size-cells = <2>;
158                                 #interrupt-cells = <1>;
159                                 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
160                                           0x81000000 0 0 0x81000000 0x5 0 1 0>;
161                                 bus-range = <0x00 0xff>;
162                                 interrupt-map-mask = <0 0 0 0>;
163                                 interrupt-map = <0 0 0 0 &mpic 62>;
164                                 marvell,pcie-port = <1>;
165                                 marvell,pcie-lane = <0>;
166                                 clocks = <&gateclk 9>;
167                                 status = "disabled";
168                         };
169                 };
170
171                 internal-regs {
172                         gpio0: gpio@18100 {
173                                 compatible = "marvell,armada-370-gpio",
174                                              "marvell,orion-gpio";
175                                 reg = <0x18100 0x40>, <0x181c0 0x08>;
176                                 reg-names = "gpio", "pwm";
177                                 ngpios = <32>;
178                                 gpio-controller;
179                                 #gpio-cells = <2>;
180                                 #pwm-cells = <2>;
181                                 interrupt-controller;
182                                 #interrupt-cells = <2>;
183                                 interrupts = <82>, <83>, <84>, <85>;
184                                 clocks = <&coreclk 0>;
185                         };
186
187                         gpio1: gpio@18140 {
188                                 compatible = "marvell,armada-370-gpio",
189                                              "marvell,orion-gpio";
190                                 reg = <0x18140 0x40>, <0x181c8 0x08>;
191                                 reg-names = "gpio", "pwm";
192                                 ngpios = <17>;
193                                 gpio-controller;
194                                 #gpio-cells = <2>;
195                                 #pwm-cells = <2>;
196                                 interrupt-controller;
197                                 #interrupt-cells = <2>;
198                                 interrupts = <87>, <88>, <89>;
199                                 clocks = <&coreclk 0>;
200                         };
201                 };
202         };
203 };
204
205 &pinctrl {
206         compatible = "marvell,mv78230-pinctrl";
207 };