1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell 98dx3236 family SoC
5 * Copyright (C) 2016 Allied Telesis Labs
7 * Contains definitions specific to the 98dx3236 SoC that are not
8 * common to all Armada XP SoCs.
11 #include "armada-370-xp.dtsi"
17 model = "Marvell 98DX3236 SoC";
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,armadaxp-mbus", "simple-bus";
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
50 compatible = "marvell,bootrom";
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
55 * 98DX3236 has 1 x1 PCIe unit Gen2.0
57 pciec: pcie@82000000 {
58 compatible = "marvell,armada-xp-pcie";
66 bus-range = <0x00 0xff>;
69 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
70 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
71 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
75 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
76 reg = <0x0800 0 0 0 0>;
79 interrupt-names = "intx";
80 interrupts-extended = <&mpic 58>;
81 #interrupt-cells = <1>;
82 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
83 0x81000000 0 0 0x81000000 0x1 0 1 0>;
84 bus-range = <0x00 0xff>;
85 interrupt-map-mask = <0 0 0 7>;
86 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
87 <0 0 0 2 &pcie1_intc 1>,
88 <0 0 0 3 &pcie1_intc 2>,
89 <0 0 0 4 &pcie1_intc 3>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
95 pcie1_intc: interrupt-controller {
97 #interrupt-cells = <1>;
103 sdramc: sdramc@1400 {
104 compatible = "marvell,armada-xp-sdram-controller";
105 reg = <0x1400 0x500>;
109 compatible = "marvell,aurora-system-cache";
110 reg = <0x08000 0x1000>;
111 cache-id-part = <0x100>;
118 compatible = "marvell,orion-gpio";
119 reg = <0x18100 0x40>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 interrupts = <82>, <83>, <84>, <85>;
130 compatible = "marvell,orion-gpio";
131 reg = <0x18140 0x40>;
135 gpio2: gpio@18180 { /* rework some properties */
136 compatible = "marvell,orion-gpio";
137 reg = <0x18180 0x40>;
138 ngpios = <1>; /* only gpio #32 */
141 interrupt-controller;
142 #interrupt-cells = <2>;
146 systemc: system-controller@18200 {
147 compatible = "marvell,armada-370-xp-system-controller";
148 reg = <0x18200 0x500>;
151 gateclk: clock-gating-control@18220 {
152 compatible = "marvell,mv98dx3236-gating-clock";
154 clocks = <&coreclk 0>;
158 cpuclk: clock-complex@18700 {
160 compatible = "marvell,mv98dx3236-cpu-clock";
161 reg = <0x18700 0x24>, <0x1c054 0x10>;
162 clocks = <&coreclk 1>;
165 corediv-clock@18740 {
170 compatible = "marvell,armada-xp-cpu-config";
175 compatible = "marvell,armada-xp-neta";
179 compatible = "marvell,armada-xp-neta";
183 compatible = "marvell,orion-xor";
186 clocks = <&gateclk 22>;
202 nand_controller: nand-controller@d0000 {
203 clocks = <&dfx_coredivclk 0>;
207 compatible = "marvell,orion-xor";
210 clocks = <&gateclk 28>;
227 dfx: dfx-server@ac000000 {
228 compatible = "marvell,dfx-server", "simple-bus";
229 #address-cells = <1>;
231 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
232 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
234 coreclk: mvebu-sar@f8204 {
235 compatible = "marvell,mv98dx3236-core-clock";
240 dfx_coredivclk: corediv-clock@f8268 {
241 compatible = "marvell,mv98dx3236-corediv-clock";
245 clock-output-names = "nand";
249 switch: switch@a8000000 {
250 compatible = "simple-bus";
251 #address-cells = <1>;
253 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
255 pp0: packet-processor@0 {
256 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
258 interrupts = <33>, <34>, <35>;
265 /* 25 MHz reference crystal */
267 compatible = "fixed-clock";
269 clock-frequency = <25000000>;
275 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
276 reg = <0x11000 0x100>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_pins>;
282 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
290 compatible = "marvell,armada-xp-timer";
291 clocks = <&coreclk 2>, <&refclk>;
292 clock-names = "nbclk", "fixed";
296 compatible = "marvell,armada-xp-wdt";
297 clocks = <&coreclk 2>, <&refclk>;
298 clock-names = "nbclk", "fixed";
302 reg = <0x20800 0x20>;
306 clocks = <&gateclk 18>;
310 clocks = <&gateclk 19>;
314 compatible = "marvell,98dx3236-pinctrl";
316 nand_pins: nand-pins {
317 marvell,pins = "mpp20", "mpp21", "mpp22",
318 "mpp23", "mpp24", "mpp25",
319 "mpp26", "mpp27", "mpp28",
321 marvell,function = "dev";
325 marvell,pins = "mpp19";
326 marvell,function = "nand";
329 spi0_pins: spi0-pins {
330 marvell,pins = "mpp0", "mpp1",
332 marvell,function = "spi0";
335 i2c0_pins: i2c-pins-0 {
336 marvell,pins = "mpp14", "mpp15";
337 marvell,function = "i2c0";
342 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343 pinctrl-0 = <&spi0_pins>;
344 pinctrl-names = "default";
352 compatible = "marvell,armada-38x-uart";
356 compatible = "marvell,armada-38x-uart";