1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
5 * Copyright (C) 2014 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 38x family SoC";
22 compatible = "marvell,armada380";
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
46 compatible = "marvell,bootrom";
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
101 compatible = "simple-bus";
102 #address-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
106 sdramc: sdramc@1400 {
107 compatible = "marvell,armada-xp-sdram-controller";
108 reg = <0x1400 0x500>;
111 L2: cache-controller@8000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x8000 0x1000>;
116 arm,double-linefill-incr = <0>;
117 arm,double-linefill-wrap = <0>;
118 arm,double-linefill = <0>;
123 compatible = "arm,cortex-a9-scu";
128 compatible = "arm,cortex-a9-global-timer";
130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
131 clocks = <&coreclk 2>;
135 compatible = "arm,cortex-a9-twd-timer";
137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
138 clocks = <&coreclk 2>;
141 gic: interrupt-controller@d000 {
142 compatible = "arm,cortex-a9-gic";
143 #interrupt-cells = <3>;
145 interrupt-controller;
146 reg = <0xd000 0x1000>,
151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
152 reg = <0x11000 0x20>;
153 #address-cells = <1>;
155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&coreclk 0>;
161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
162 reg = <0x11100 0x20>;
163 #address-cells = <1>;
165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&coreclk 0>;
170 uart0: serial@12000 {
171 compatible = "marvell,armada-38x-uart", "ns16550a";
172 reg = <0x12000 0x100>;
174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&coreclk 0>;
180 uart1: serial@12100 {
181 compatible = "marvell,armada-38x-uart", "ns16550a";
182 reg = <0x12100 0x100>;
184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&coreclk 0>;
190 pinctrl: pinctrl@18000 {
191 reg = <0x18000 0x20>;
193 ge0_rgmii_pins: ge-rgmii-pins-0 {
194 marvell,pins = "mpp6", "mpp7", "mpp8",
195 "mpp9", "mpp10", "mpp11",
196 "mpp12", "mpp13", "mpp14",
197 "mpp15", "mpp16", "mpp17";
198 marvell,function = "ge0";
201 ge1_rgmii_pins: ge-rgmii-pins-1 {
202 marvell,pins = "mpp21", "mpp27", "mpp28",
203 "mpp29", "mpp30", "mpp31",
204 "mpp32", "mpp37", "mpp38",
205 "mpp39", "mpp40", "mpp41";
206 marvell,function = "ge1";
209 i2c0_pins: i2c-pins-0 {
210 marvell,pins = "mpp2", "mpp3";
211 marvell,function = "i2c0";
214 mdio_pins: mdio-pins {
215 marvell,pins = "mpp4", "mpp5";
216 marvell,function = "ge";
219 ref_clk0_pins: ref-clk-pins-0 {
220 marvell,pins = "mpp45";
221 marvell,function = "ref";
224 ref_clk1_pins: ref-clk-pins-1 {
225 marvell,pins = "mpp46";
226 marvell,function = "ref";
229 spi0_pins: spi-pins-0 {
230 marvell,pins = "mpp22", "mpp23", "mpp24",
232 marvell,function = "spi0";
235 spi1_pins: spi-pins-1 {
236 marvell,pins = "mpp56", "mpp57", "mpp58",
238 marvell,function = "spi1";
241 nand_pins: nand-pins {
242 marvell,pins = "mpp22", "mpp34", "mpp23",
243 "mpp33", "mpp38", "mpp28",
244 "mpp40", "mpp42", "mpp35",
245 "mpp36", "mpp25", "mpp30",
247 marvell,function = "dev";
251 marvell,pins = "mpp41";
252 marvell,function = "nand";
255 uart0_pins: uart-pins-0 {
256 marvell,pins = "mpp0", "mpp1";
257 marvell,function = "ua0";
260 uart1_pins: uart-pins-1 {
261 marvell,pins = "mpp19", "mpp20";
262 marvell,function = "ua1";
265 sdhci_pins: sdhci-pins {
266 marvell,pins = "mpp48", "mpp49", "mpp50",
267 "mpp52", "mpp53", "mpp54",
268 "mpp55", "mpp57", "mpp58",
270 marvell,function = "sd0";
273 sata0_pins: sata-pins-0 {
274 marvell,pins = "mpp20";
275 marvell,function = "sata0";
278 sata1_pins: sata-pins-1 {
279 marvell,pins = "mpp19";
280 marvell,function = "sata1";
283 sata2_pins: sata-pins-2 {
284 marvell,pins = "mpp47";
285 marvell,function = "sata2";
288 sata3_pins: sata-pins-3 {
289 marvell,pins = "mpp44";
290 marvell,function = "sata3";
294 marvell,pins = "mpp48", "mpp49",
297 marvell,function = "audio";
300 spdif_pins: spdif-pins {
301 marvell,pins = "mpp51";
302 marvell,function = "audio";
307 compatible = "marvell,armada-370-gpio",
308 "marvell,orion-gpio";
309 reg = <0x18100 0x40>, <0x181c0 0x08>;
310 reg-names = "gpio", "pwm";
313 gpio-ranges = <&pinctrl 0 0 32>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&coreclk 0>;
326 compatible = "marvell,armada-370-gpio",
327 "marvell,orion-gpio";
328 reg = <0x18140 0x40>, <0x181c8 0x08>;
329 reg-names = "gpio", "pwm";
332 gpio-ranges = <&pinctrl 0 32 28>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&coreclk 0>;
344 systemc: system-controller@18200 {
345 compatible = "marvell,armada-380-system-controller",
346 "marvell,armada-370-xp-system-controller";
347 reg = <0x18200 0x100>;
350 gateclk: clock-gating-control@18220 {
351 compatible = "marvell,armada-380-gating-clock";
353 clocks = <&coreclk 0>;
358 compatible = "marvell,armada-380-comphy";
359 reg-names = "comphy", "conf";
360 reg = <0x18300 0x100>, <0x18460 4>;
361 #address-cells = <1>;
395 coreclk: mvebu-sar@18600 {
396 compatible = "marvell,armada-380-core-clock";
397 reg = <0x18600 0x04>;
401 mbusc: mbus-controller@20000 {
402 compatible = "marvell,mbus-controller";
403 reg = <0x20000 0x100>, <0x20180 0x20>,
407 mpic: interrupt-controller@20a00 {
408 compatible = "marvell,mpic";
409 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
410 #interrupt-cells = <1>;
412 interrupt-controller;
414 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
418 compatible = "marvell,armada-380-timer",
419 "marvell,armada-xp-timer";
420 reg = <0x20300 0x30>, <0x21040 0x30>;
421 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
422 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
423 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
424 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
427 clocks = <&coreclk 2>, <&refclk>;
428 clock-names = "nbclk", "fixed";
431 watchdog: watchdog@20300 {
432 compatible = "marvell,armada-380-wdt";
433 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
434 clocks = <&coreclk 2>, <&refclk>;
435 clock-names = "nbclk", "fixed";
436 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
437 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
440 cpurst: cpurst@20800 {
441 compatible = "marvell,armada-370-cpu-reset";
442 reg = <0x20800 0x10>;
445 mpcore-soc-ctrl@20d20 {
446 compatible = "marvell,armada-380-mpcore-soc-ctrl";
447 reg = <0x20d20 0x6c>;
450 coherencyfab: coherency-fabric@21010 {
451 compatible = "marvell,armada-380-coherency-fabric";
452 reg = <0x21010 0x1c>;
456 compatible = "marvell,armada-380-pmsu";
457 reg = <0x22000 0x1000>;
461 * As a special exception to the "order by
462 * register address" rule, the eth0 node is
463 * placed here to ensure that it gets
464 * registered as the first interface, since
465 * the network subsystem doesn't allow naming
466 * interfaces using DT aliases. Without this,
467 * the ordering of interfaces is different
468 * from the one used in U-Boot and the
469 * labeling of interfaces on the boards, which
470 * is very confusing for users.
472 eth0: ethernet@70000 {
473 compatible = "marvell,armada-370-neta";
474 reg = <0x70000 0x4000>;
475 interrupts-extended = <&mpic 8>;
476 clocks = <&gateclk 4>;
477 tx-csum-limit = <9800>;
481 eth1: ethernet@30000 {
482 compatible = "marvell,armada-370-neta";
483 reg = <0x30000 0x4000>;
484 interrupts-extended = <&mpic 10>;
485 clocks = <&gateclk 3>;
489 eth2: ethernet@34000 {
490 compatible = "marvell,armada-370-neta";
491 reg = <0x34000 0x4000>;
492 interrupts-extended = <&mpic 12>;
493 clocks = <&gateclk 2>;
498 compatible = "marvell,orion-ehci";
499 reg = <0x58000 0x500>;
500 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gateclk 18>;
506 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
509 clocks = <&gateclk 22>;
513 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
518 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
526 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
529 clocks = <&gateclk 28>;
533 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
538 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
548 compatible = "marvell,orion-mdio";
550 clocks = <&gateclk 4>;
554 compatible = "marvell,armada-38x-crypto";
555 reg = <0x90000 0x10000>;
557 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&gateclk 23>, <&gateclk 21>,
560 <&gateclk 14>, <&gateclk 16>;
561 clock-names = "cesa0", "cesa1",
563 marvell,crypto-srams = <&crypto_sram0>,
565 marvell,crypto-sram-size = <0x800>;
569 compatible = "marvell,armada-380-rtc";
570 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
571 reg-names = "rtc", "rtc-soc";
572 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
576 compatible = "marvell,armada-380-ahci";
577 reg = <0xa8000 0x2000>;
578 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&gateclk 15>;
584 compatible = "marvell,armada-380-neta-bm";
585 reg = <0xc8000 0xac>;
586 clocks = <&gateclk 13>;
587 internal-mem = <&bm_bppi>;
592 compatible = "marvell,armada-380-ahci";
593 reg = <0xe0000 0x2000>;
594 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&gateclk 30>;
599 coredivclk: clock@e4250 {
600 compatible = "marvell,armada-380-corediv-clock";
604 clock-output-names = "nand";
607 thermal: thermal@e8078 {
608 compatible = "marvell,armada380-thermal";
609 reg = <0xe4078 0x4>, <0xe4070 0x8>;
613 nand_controller: nand-controller@d0000 {
614 compatible = "marvell,armada370-nand-controller";
615 reg = <0xd0000 0x54>;
616 #address-cells = <1>;
618 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&coredivclk 0>;
624 compatible = "marvell,armada-380-sdhci";
625 reg-names = "sdhci", "mbus", "conf-sdio3";
626 reg = <0xd8000 0x1000>,
629 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&gateclk 17>;
631 mrvl,clk-delay-cycles = <0x1F>;
635 audio_controller: audio-controller@e8000 {
636 #sound-dai-cells = <1>;
637 compatible = "marvell,armada-380-audio";
638 reg = <0xe8000 0x4000>, <0x18410 0xc>,
640 reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
641 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&gateclk 0>;
643 clock-names = "internal";
648 compatible = "marvell,armada-380-xhci";
649 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
650 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gateclk 9>;
656 compatible = "marvell,armada-380-xhci";
657 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
658 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&gateclk 10>;
664 crypto_sram0: sa-sram0 {
665 compatible = "mmio-sram";
666 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
667 clocks = <&gateclk 23>;
668 #address-cells = <1>;
670 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
673 crypto_sram1: sa-sram1 {
674 compatible = "mmio-sram";
675 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
676 clocks = <&gateclk 21>;
677 #address-cells = <1>;
679 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
683 compatible = "mmio-sram";
684 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
685 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
686 #address-cells = <1>;
688 clocks = <&gateclk 13>;
694 compatible = "marvell,armada-380-spi",
696 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
697 #address-cells = <1>;
700 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&coreclk 0>;
706 compatible = "marvell,armada-380-spi",
708 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
709 #address-cells = <1>;
712 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&coreclk 0>;
719 /* 1 GHz fixed main PLL */
721 compatible = "fixed-clock";
723 clock-frequency = <1000000000>;
726 /* 25 MHz reference crystal */
728 compatible = "fixed-clock";
730 clock-frequency = <25000000>;