1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree file for the Turris Omnia
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include "armada-385.dtsi"
18 model = "Turris Omnia";
19 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
32 device_type = "memory";
33 reg = <0x00000000 0x40000000>; /* 1024 MB */
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
38 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
39 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
40 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
44 /* USB part of the PCIe2/USB 2.0 port */
54 pinctrl-names = "default";
55 pinctrl-0 = <&sdhci_pins>;
93 /* Connected to 88E6176 switch, port 6 */
95 pinctrl-names = "default";
96 pinctrl-0 = <&ge0_rgmii_pins>;
106 /* Connected to 88E6176 switch, port 5 */
108 pinctrl-names = "default";
109 pinctrl-0 = <&ge1_rgmii_pins>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&i2c0_pins>;
132 compatible = "nxp,pca9547";
133 #address-cells = <1>;
139 #address-cells = <1>;
143 /* STM32F0 command interface at address 0x2a */
144 /* leds device (in STM32F0) at address 0x2b */
147 compatible = "atmel,24c64";
150 /* The EEPROM contains data for bootloader.
152 * struct omnia_eeprom {
153 * u32 magic; (=0x0341a034 in LE)
154 * u32 ramsize; (in GiB)
163 #address-cells = <1>;
167 /* routed to PCIe0/mSATA connector (CN7A) */
171 #address-cells = <1>;
175 /* routed to PCIe1/USB2 connector (CN61A) */
179 #address-cells = <1>;
183 /* routed to PCIe2 connector (CN62A) */
187 #address-cells = <1>;
195 #address-cells = <1>;
199 /* ATSHA204A at address 0x64 */
203 #address-cells = <1>;
207 /* exposed on pin header */
211 #address-cells = <1>;
217 * GPIO expander for SFP+ signals and
220 compatible = "nxp,pca9538";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pcawan_pins>;
226 interrupt-parent = <&gpio1>;
227 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&mdio_pins>;
243 compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
245 marvell,reg-init = <3 18 0 0x4985>;
247 /* irq is connected to &pcawan pin 7 */
250 /* Switch MV88E6176 at address 0x10 */
252 compatible = "marvell,mv88e6085";
253 #address-cells = <1>;
260 #address-cells = <1>;
292 phy-mode = "rgmii-id";
304 phy-mode = "rgmii-id";
316 pcawan_pins: pcawan-pins {
317 marvell,pins = "mpp46";
318 marvell,function = "gpio";
321 spi0cs0_pins: spi0cs0-pins {
322 marvell,pins = "mpp25";
323 marvell,function = "spi0";
326 spi0cs2_pins: spi0cs2-pins {
327 marvell,pins = "mpp26";
328 marvell,function = "spi0";
333 pinctrl-names = "default";
334 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
338 compatible = "spansion,s25fl164k", "jedec,spi-nor";
339 #address-cells = <1>;
342 spi-max-frequency = <40000000>;
345 compatible = "fixed-partitions";
346 #address-cells = <1>;
350 reg = <0x0 0x00100000>;
355 reg = <0x00100000 0x00700000>;
356 label = "Rescue system";
361 /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
365 /* Pin header CN10 */
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart0_pins>;
372 /* Pin header CN11 */
373 pinctrl-names = "default";
374 pinctrl-0 = <&uart1_pins>;