arch/arm/boot/dts/armada-385-turris-omnia.dts

   1 /*
   2  * Device Tree file for the Turris Omnia
   3  *
   4  * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
   5  * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is licensed under the terms of the GNU General Public
  13  *     License version 2.  This program is licensed "as is" without
  14  *     any warranty of any kind, whether express or implied.
  15  *
  16  * Or, alternatively,
  17  *
  18  *  b) Permission is hereby granted, free of charge, to any person
  19  *     obtaining a copy of this software and associated documentation
  20  *     files (the "Software"), to deal in the Software without
  21  *     restriction, including without limitation the rights to use,
  22  *     copy, modify, merge, publish, distribute, sublicense, and/or
  23  *     sell copies of the Software, and to permit persons to whom the
  24  *     Software is furnished to do so, subject to the following
  25  *     conditions:
  26  *
  27  *     The above copyright notice and this permission notice shall be
  28  *     included in all copies or substantial portions of the Software.
  29  *
  30  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  31  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  32  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  33  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  34  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  35  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  36  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  37  *     OTHER DEALINGS IN THE SOFTWARE.
  38  */
  39
  40 /*
  41  * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
  42  */
  43
  44 /dts-v1/;
  45
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/input/input.h>
  48 #include "armada-385.dtsi"
  49
  50 / {
  51         model = "Turris Omnia";
  52         compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
  53
  54         chosen {
  55                 stdout-path = &uart0;
  56         };
  57
  58         aliases {
  59                 ethernet0 = &eth0;
  60                 ethernet1 = &eth1;
  61                 ethernet2 = &eth2;
  62         };
  63
  64         memory {
  65                 device_type = "memory";
  66                 reg = <0x00000000 0x40000000>; /* 1024 MB */
  67         };
  68
  69         soc {
  70                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  71                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  72                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  73                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
  74
  75                 internal-regs {
  76
  77                         /* USB part of the PCIe2/USB 2.0 port */
  78                         usb@58000 {
  79                                 status = "okay";
  80                         };
  81
  82                         sata@a8000 {
  83                                 status = "okay";
  84                         };
  85
  86                         sdhci@d8000 {
  87                                 pinctrl-names = "default";
  88                                 pinctrl-0 = <&sdhci_pins>;
  89                                 status = "okay";
  90
  91                                 bus-width = <8>;
  92                                 no-1-8-v;
  93                                 non-removable;
  94                         };
  95
  96                         usb3@f0000 {
  97                                 status = "okay";
  98                         };
  99
 100                         usb3@f8000 {
 101                                 status = "okay";
 102                         };
 103                 };
 104
 105                 pcie {
 106                         status = "okay";
 107
 108                         pcie@1,0 {
 109                                 /* Port 0, Lane 0 */
 110                                 status = "okay";
 111                         };
 112
 113                         pcie@2,0 {
 114                                 /* Port 1, Lane 0 */
 115                                 status = "okay";
 116                         };
 117
 118                         pcie@3,0 {
 119                                 /* Port 2, Lane 0 */
 120                                 status = "okay";
 121                         };
 122                 };
 123         };
 124 };
 125
 126 /* Connected to 88E6176 switch, port 6 */
 127 &eth0 {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&ge0_rgmii_pins>;
 130         status = "okay";
 131         phy-mode = "rgmii";
 132
 133         fixed-link {
 134                 speed = <1000>;
 135                 full-duplex;
 136         };
 137 };
 138
 139 /* Connected to 88E6176 switch, port 5 */
 140 &eth1 {
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&ge1_rgmii_pins>;
 143         status = "okay";
 144         phy-mode = "rgmii";
 145
 146         fixed-link {
 147                 speed = <1000>;
 148                 full-duplex;
 149         };
 150 };
 151
 152 /* WAN port */
 153 &eth2 {
 154         status = "okay";
 155         phy-mode = "sgmii";
 156         phy = <&phy1>;
 157 };
 158
 159 &i2c0 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&i2c0_pins>;
 162         status = "okay";
 163
 164         i2cmux@70 {
 165                 compatible = "nxp,pca9547";
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168                 reg = <0x70>;
 169                 status = "okay";
 170
 171                 i2c@0 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         reg = <0>;
 175
 176                         /* STM32F0 command interface at address 0x2a */
 177                         /* leds device (in STM32F0) at address 0x2b */
 178
 179                         eeprom@54 {
 180                                 compatible = "atmel,24c64";
 181                                 reg = <0x54>;
 182
 183                                 /* The EEPROM contains data for bootloader.
 184                                  * Contents:
 185                                  *      struct omnia_eeprom {
 186                                  *              u32 magic; (=0x0341a034 in LE)
 187                                  *              u32 ramsize; (in GiB)
 188                                  *              char regdomain[4];
 189                                  *              u32 crc32;
 190                                  *      };
 191                                  */
 192                         };
 193                 };
 194
 195                 i2c@1 {
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                         reg = <1>;
 199
 200                         /* routed to PCIe0/mSATA connector (CN7A) */
 201                 };
 202
 203                 i2c@2 {
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         reg = <2>;
 207
 208                         /* routed to PCIe1/USB2 connector (CN61A) */
 209                 };
 210
 211                 i2c@3 {
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         reg = <3>;
 215
 216                         /* routed to PCIe2 connector (CN62A) */
 217                 };
 218
 219                 i2c@4 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         reg = <4>;
 223
 224                         /* routed to SFP+ */
 225                 };
 226
 227                 i2c@5 {
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         reg = <5>;
 231
 232                         /* ATSHA204A at address 0x64 */
 233                 };
 234
 235                 i2c@6 {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <6>;
 239
 240                         /* exposed on pin header */
 241                 };
 242
 243                 i2c@7 {
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         reg = <7>;
 247
 248                         pcawan: gpio@71 {
 249                                 /*
 250                                  * GPIO expander for SFP+ signals and
 251                                  * and phy irq
 252                                  */
 253                                 compatible = "nxp,pca9538";
 254                                 reg = <0x71>;
 255
 256                                 pinctrl-names = "default";
 257                                 pinctrl-0 = <&pcawan_pins>;
 258
 259                                 interrupt-parent = <&gpio1>;
 260                                 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 261
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                         };
 265                 };
 266         };
 267 };
 268
 269 &mdio {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&mdio_pins>;
 272         status = "okay";
 273
 274         phy1: phy@1 {
 275                 status = "okay";
 276                 compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
 277                 reg = <1>;
 278                 marvell,reg-init = <3 18 0 0x4985>;
 279
 280                 /* irq is connected to &pcawan pin 7 */
 281         };
 282
 283         /* Switch MV88E6176 at address 0x10 */
 284         switch@10 {
 285                 compatible = "marvell,mv88e6085";
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 dsa,member = <0 0>;
 289
 290                 reg = <0x10>;
 291
 292                 ports {
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295
 296                         ports@0 {
 297                                 reg = <0>;
 298                                 label = "lan0";
 299                         };
 300
 301                         ports@1 {
 302                                 reg = <1>;
 303                                 label = "lan1";
 304                         };
 305
 306                         ports@2 {
 307                                 reg = <2>;
 308                                 label = "lan2";
 309                         };
 310
 311                         ports@3 {
 312                                 reg = <3>;
 313                                 label = "lan3";
 314                         };
 315
 316                         ports@4 {
 317                                 reg = <4>;
 318                                 label = "lan4";
 319                         };
 320
 321                         ports@5 {
 322                                 reg = <5>;
 323                                 label = "cpu";
 324                                 ethernet = <&eth1>;
 325                                 phy-mode = "rgmii-id";
 326
 327                                 fixed-link {
 328                                         speed = <1000>;
 329                                         full-duplex;
 330                                 };
 331                         };
 332
 333                         ports@6 {
 334                                 reg = <6>;
 335                                 label = "cpu";
 336                                 ethernet = <&eth0>;
 337                                 phy-mode = "rgmii-id";
 338
 339                                 fixed-link {
 340                                         speed = <1000>;
 341                                         full-duplex;
 342                                 };
 343                         };
 344                 };
 345         };
 346 };
 347
 348 &pinctrl {
 349         pcawan_pins: pcawan-pins {
 350                 marvell,pins = "mpp46";
 351                 marvell,function = "gpio";
 352         };
 353
 354         spi0cs0_pins: spi0cs0-pins {
 355                 marvell,pins = "mpp25";
 356                 marvell,function = "spi0";
 357         };
 358
 359         spi0cs2_pins: spi0cs2-pins {
 360                 marvell,pins = "mpp26";
 361                 marvell,function = "spi0";
 362         };
 363 };
 364
 365 &spi0 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
 368         status = "okay";
 369
 370         spi-nor@0 {
 371                 compatible = "spansion,s25fl164k", "jedec,spi-nor";
 372                 #address-cells = <1>;
 373                 #size-cells = <1>;
 374                 reg = <0>;
 375                 spi-max-frequency = <40000000>;
 376
 377                 partitions {
 378                         compatible = "fixed-partitions";
 379                         #address-cells = <1>;
 380                         #size-cells = <1>;
 381
 382                         partition@0 {
 383                                 reg = <0x0 0x00100000>;
 384                                 label = "U-Boot";
 385                         };
 386
 387                         partition@100000 {
 388                                 reg = <0x00100000 0x00700000>;
 389                                 label = "Rescue system";
 390                         };
 391                 };
 392         };
 393
 394         /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
 395 };
 396
 397 &uart0 {
 398         /* Pin header CN10 */
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&uart0_pins>;
 401         status = "okay";
 402 };
 403
 404 &uart1 {
 405         /* Pin header CN11 */
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&uart1_pins>;
 408         status = "okay";
 409 };