arch/arm/boot/dts/armada-385-turris-omnia.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for the Turris Omnia
   4  *
   5  * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
   6  * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
   7  *
   8  * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
   9  */
  10
  11 /dts-v1/;
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15 #include "armada-385.dtsi"
  16
  17 / {
  18         model = "Turris Omnia";
  19         compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
  20
  21         chosen {
  22                 stdout-path = &uart0;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &eth0;
  27                 ethernet1 = &eth1;
  28                 ethernet2 = &eth2;
  29         };
  30
  31         memory {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x40000000>; /* 1024 MB */
  34         };
  35
  36         soc {
  37                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  38                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  39                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  40                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
  41
  42                 internal-regs {
  43
  44                         /* USB part of the PCIe2/USB 2.0 port */
  45                         usb@58000 {
  46                                 status = "okay";
  47                         };
  48
  49                         sata@a8000 {
  50                                 status = "okay";
  51                         };
  52
  53                         sdhci@d8000 {
  54                                 pinctrl-names = "default";
  55                                 pinctrl-0 = <&sdhci_pins>;
  56                                 status = "okay";
  57
  58                                 bus-width = <8>;
  59                                 no-1-8-v;
  60                                 non-removable;
  61                         };
  62
  63                         usb3@f0000 {
  64                                 status = "okay";
  65                         };
  66
  67                         usb3@f8000 {
  68                                 status = "okay";
  69                         };
  70                 };
  71
  72                 pcie {
  73                         status = "okay";
  74
  75                         pcie@1,0 {
  76                                 /* Port 0, Lane 0 */
  77                                 status = "okay";
  78                         };
  79
  80                         pcie@2,0 {
  81                                 /* Port 1, Lane 0 */
  82                                 status = "okay";
  83                         };
  84
  85                         pcie@3,0 {
  86                                 /* Port 2, Lane 0 */
  87                                 status = "okay";
  88                         };
  89                 };
  90         };
  91 };
  92
  93 /* Connected to 88E6176 switch, port 6 */
  94 &eth0 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&ge0_rgmii_pins>;
  97         status = "okay";
  98         phy-mode = "rgmii";
  99
 100         fixed-link {
 101                 speed = <1000>;
 102                 full-duplex;
 103         };
 104 };
 105
 106 /* Connected to 88E6176 switch, port 5 */
 107 &eth1 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&ge1_rgmii_pins>;
 110         status = "okay";
 111         phy-mode = "rgmii";
 112
 113         fixed-link {
 114                 speed = <1000>;
 115                 full-duplex;
 116         };
 117 };
 118
 119 /* WAN port */
 120 &eth2 {
 121         status = "okay";
 122         phy-mode = "sgmii";
 123         phy = <&phy1>;
 124 };
 125
 126 &i2c0 {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&i2c0_pins>;
 129         status = "okay";
 130
 131         i2cmux@70 {
 132                 compatible = "nxp,pca9547";
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135                 reg = <0x70>;
 136                 status = "okay";
 137
 138                 i2c@0 {
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         reg = <0>;
 142
 143                         /* STM32F0 command interface at address 0x2a */
 144                         /* leds device (in STM32F0) at address 0x2b */
 145
 146                         eeprom@54 {
 147                                 compatible = "atmel,24c64";
 148                                 reg = <0x54>;
 149
 150                                 /* The EEPROM contains data for bootloader.
 151                                  * Contents:
 152                                  *      struct omnia_eeprom {
 153                                  *              u32 magic; (=0x0341a034 in LE)
 154                                  *              u32 ramsize; (in GiB)
 155                                  *              char regdomain[4];
 156                                  *              u32 crc32;
 157                                  *      };
 158                                  */
 159                         };
 160                 };
 161
 162                 i2c@1 {
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         reg = <1>;
 166
 167                         /* routed to PCIe0/mSATA connector (CN7A) */
 168                 };
 169
 170                 i2c@2 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <2>;
 174
 175                         /* routed to PCIe1/USB2 connector (CN61A) */
 176                 };
 177
 178                 i2c@3 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         reg = <3>;
 182
 183                         /* routed to PCIe2 connector (CN62A) */
 184                 };
 185
 186                 i2c@4 {
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         reg = <4>;
 190
 191                         /* routed to SFP+ */
 192                 };
 193
 194                 i2c@5 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         reg = <5>;
 198
 199                         /* ATSHA204A at address 0x64 */
 200                 };
 201
 202                 i2c@6 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         reg = <6>;
 206
 207                         /* exposed on pin header */
 208                 };
 209
 210                 i2c@7 {
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         reg = <7>;
 214
 215                         pcawan: gpio@71 {
 216                                 /*
 217                                  * GPIO expander for SFP+ signals and
 218                                  * and phy irq
 219                                  */
 220                                 compatible = "nxp,pca9538";
 221                                 reg = <0x71>;
 222
 223                                 pinctrl-names = "default";
 224                                 pinctrl-0 = <&pcawan_pins>;
 225
 226                                 interrupt-parent = <&gpio1>;
 227                                 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 228
 229                                 gpio-controller;
 230                                 #gpio-cells = <2>;
 231                         };
 232                 };
 233         };
 234 };
 235
 236 &mdio {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&mdio_pins>;
 239         status = "okay";
 240
 241         phy1: phy@1 {
 242                 status = "okay";
 243                 compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
 244                 reg = <1>;
 245                 marvell,reg-init = <3 18 0 0x4985>;
 246
 247                 /* irq is connected to &pcawan pin 7 */
 248         };
 249
 250         /* Switch MV88E6176 at address 0x10 */
 251         switch@10 {
 252                 compatible = "marvell,mv88e6085";
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 dsa,member = <0 0>;
 256
 257                 reg = <0x10>;
 258
 259                 ports {
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262
 263                         ports@0 {
 264                                 reg = <0>;
 265                                 label = "lan0";
 266                         };
 267
 268                         ports@1 {
 269                                 reg = <1>;
 270                                 label = "lan1";
 271                         };
 272
 273                         ports@2 {
 274                                 reg = <2>;
 275                                 label = "lan2";
 276                         };
 277
 278                         ports@3 {
 279                                 reg = <3>;
 280                                 label = "lan3";
 281                         };
 282
 283                         ports@4 {
 284                                 reg = <4>;
 285                                 label = "lan4";
 286                         };
 287
 288                         ports@5 {
 289                                 reg = <5>;
 290                                 label = "cpu";
 291                                 ethernet = <&eth1>;
 292                                 phy-mode = "rgmii-id";
 293
 294                                 fixed-link {
 295                                         speed = <1000>;
 296                                         full-duplex;
 297                                 };
 298                         };
 299
 300                         ports@6 {
 301                                 reg = <6>;
 302                                 label = "cpu";
 303                                 ethernet = <&eth0>;
 304                                 phy-mode = "rgmii-id";
 305
 306                                 fixed-link {
 307                                         speed = <1000>;
 308                                         full-duplex;
 309                                 };
 310                         };
 311                 };
 312         };
 313 };
 314
 315 &pinctrl {
 316         pcawan_pins: pcawan-pins {
 317                 marvell,pins = "mpp46";
 318                 marvell,function = "gpio";
 319         };
 320
 321         spi0cs0_pins: spi0cs0-pins {
 322                 marvell,pins = "mpp25";
 323                 marvell,function = "spi0";
 324         };
 325
 326         spi0cs2_pins: spi0cs2-pins {
 327                 marvell,pins = "mpp26";
 328                 marvell,function = "spi0";
 329         };
 330 };
 331
 332 &spi0 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
 335         status = "okay";
 336
 337         spi-nor@0 {
 338                 compatible = "spansion,s25fl164k", "jedec,spi-nor";
 339                 #address-cells = <1>;
 340                 #size-cells = <1>;
 341                 reg = <0>;
 342                 spi-max-frequency = <40000000>;
 343
 344                 partitions {
 345                         compatible = "fixed-partitions";
 346                         #address-cells = <1>;
 347                         #size-cells = <1>;
 348
 349                         partition@0 {
 350                                 reg = <0x0 0x00100000>;
 351                                 label = "U-Boot";
 352                         };
 353
 354                         partition@100000 {
 355                                 reg = <0x00100000 0x00700000>;
 356                                 label = "Rescue system";
 357                         };
 358                 };
 359         };
 360
 361         /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
 362 };
 363
 364 &uart0 {
 365         /* Pin header CN10 */
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&uart0_pins>;
 368         status = "okay";
 369 };
 370
 371 &uart1 {
 372         /* Pin header CN11 */
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&uart1_pins>;
 375         status = "okay";
 376 };