1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
10 model = "Netgear GS110EMX";
11 compatible = "netgear,gs110emx", "marvell,armada380";
14 /* So that mvebu u-boot can update the MAC addresses */
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
25 pinctrl-names = "default";
28 label = "Factory Default";
29 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_RESTART>;
35 device_type = "memory";
36 reg = <0x00000000 0x08000000>; /* 128 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
49 * If the rtc doesn't work, run "date reset"
62 buffer-manager = <&bm>;
63 phy-mode = "rgmii-id";
64 pinctrl-0 = <&ge0_rgmii_pins>;
65 pinctrl-names = "default";
76 pinctrl-names = "default";
77 pinctrl-0 = <&mdio_pins>;
81 compatible = "marvell,mv88e6190";
83 #interrupt-cells = <2>;
85 interrupt-parent = <&gpio1>;
86 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
87 pinctrl-0 = <&switch_interrupt_pins>;
88 pinctrl-names = "default";
96 switch0phy1: switch0phy1@1 {
100 switch0phy2: switch0phy2@2 {
104 switch0phy3: switch0phy3@3 {
108 switch0phy4: switch0phy4@4 {
112 switch0phy5: switch0phy5@5 {
116 switch0phy6: switch0phy6@6 {
120 switch0phy7: switch0phy7@7 {
124 switch0phy8: switch0phy8@8 {
130 compatible = "marvell,mv88e6xxx-mdio-external";
131 #address-cells = <1>;
134 phy1: ethernet-phy@b {
136 compatible = "ethernet-phy-ieee802.3-c45";
139 phy2: ethernet-phy@c {
141 compatible = "ethernet-phy-ieee802.3-c45";
146 #address-cells = <1>;
163 phy-handle = <&switch0phy1>;
169 phy-handle = <&switch0phy2>;
175 phy-handle = <&switch0phy3>;
181 phy-handle = <&switch0phy4>;
187 phy-handle = <&switch0phy5>;
193 phy-handle = <&switch0phy6>;
199 phy-handle = <&switch0phy7>;
205 phy-handle = <&switch0phy8>;
210 /* 88X3310P external phy */
212 phy-handle = <&phy1>;
218 /* 88X3310P external phy */
220 phy-handle = <&phy2>;
229 front_button_pins: front-button-pins {
230 marvell,pins = "mpp38";
231 marvell,function = "gpio";
234 switch_interrupt_pins: switch-interrupt-pins {
235 marvell,pins = "mpp39";
236 marvell,function = "gpio";
241 pinctrl-0 = <&spi0_pins>;
242 pinctrl-names = "default";
246 #address-cells = <1>;
248 compatible = "jedec,spi-nor";
249 reg = <0>; /* Chip select 0 */
250 spi-max-frequency = <3000000>;
253 compatible = "fixed-partitions";
254 #address-cells = <1>;
260 reg = <0x00000000 0x00100000>;
265 reg = <0x00100000 0x00010000>;
270 reg = <0x00110000 0x00010000>;
275 reg = <0x00120000 0x00900000>;
280 reg = <0x00a20000 0x00300000>;
285 reg = <0x00d20000 0x002e0000>;
292 pinctrl-0 = <&uart0_pins>;
293 pinctrl-names = "default";