2 * Device Tree Include file for Marvell Armada 370 family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
48 * Contains definitions specific to the Armada 370 SoC that are not
49 * common to all Armada SoCs.
52 #include "armada-370-xp.dtsi"
53 /include/ "skeleton.dtsi"
56 model = "Marvell Armada 370 family SoC";
57 compatible = "marvell,armada370", "marvell,armada-370-xp";
66 compatible = "marvell,armada370-mbus", "simple-bus";
69 compatible = "marvell,bootrom";
70 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
74 compatible = "marvell,armada-370-pcie";
82 bus-range = <0x00 0xff>;
85 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
86 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
87 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
88 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
89 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
90 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
94 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
95 reg = <0x0800 0 0 0 0>;
98 #interrupt-cells = <1>;
99 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
100 0x81000000 0 0 0x81000000 0x1 0 1 0>;
101 interrupt-map-mask = <0 0 0 0>;
102 interrupt-map = <0 0 0 0 &mpic 58>;
103 marvell,pcie-port = <0>;
104 marvell,pcie-lane = <0>;
105 clocks = <&gateclk 5>;
111 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
112 reg = <0x1000 0 0 0 0>;
113 #address-cells = <3>;
115 #interrupt-cells = <1>;
116 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
117 0x81000000 0 0 0x81000000 0x2 0 1 0>;
118 interrupt-map-mask = <0 0 0 0>;
119 interrupt-map = <0 0 0 0 &mpic 62>;
120 marvell,pcie-port = <1>;
121 marvell,pcie-lane = <0>;
122 clocks = <&gateclk 9>;
129 compatible = "marvell,aurora-outer-cache";
130 reg = <0x08000 0x1000>;
131 cache-id-part = <0x100>;
138 reg = <0x11000 0x20>;
142 reg = <0x11100 0x20>;
146 compatible = "marvell,orion-gpio";
147 reg = <0x18100 0x40>;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 interrupts = <82>, <83>, <84>, <85>;
157 compatible = "marvell,orion-gpio";
158 reg = <0x18140 0x40>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 interrupts = <87>, <88>, <89>, <90>;
168 compatible = "marvell,orion-gpio";
169 reg = <0x18180 0x40>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
179 * Default UART pinctrl setting without RTS/CTS, can
180 * be overwritten on board level if a different
181 * configuration is used.
183 uart0: serial@12000 {
184 pinctrl-0 = <&uart0_pins>;
185 pinctrl-names = "default";
188 uart1: serial@12100 {
189 pinctrl-0 = <&uart1_pins>;
190 pinctrl-names = "default";
193 system-controller@18200 {
194 compatible = "marvell,armada-370-xp-system-controller";
195 reg = <0x18200 0x100>;
198 gateclk: clock-gating-control@18220 {
199 compatible = "marvell,armada-370-gating-clock";
201 clocks = <&coreclk 0>;
205 coreclk: mvebu-sar@18230 {
206 compatible = "marvell,armada-370-core-clock";
207 reg = <0x18230 0x08>;
212 compatible = "marvell,armada370-thermal";
222 interrupt-controller@20a00 {
223 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
227 compatible = "marvell,armada-370-timer";
228 clocks = <&coreclk 2>;
232 compatible = "marvell,armada-370-wdt";
233 clocks = <&coreclk 2>;
237 compatible = "marvell,armada-370-cpu-reset";
242 compatible = "marvell,armada-370-cpu-config";
246 audio_controller: audio-controller@30000 {
247 #sound-dai-cells = <1>;
248 compatible = "marvell,armada370-audio";
249 reg = <0x30000 0x4000>;
251 clocks = <&gateclk 0>;
252 clock-names = "internal";
257 clocks = <&coreclk 0>;
261 clocks = <&coreclk 0>;
265 compatible = "marvell,orion-xor";
284 compatible = "marvell,orion-xor";
303 compatible = "marvell,armada-370-neta";
307 compatible = "marvell,armada-370-neta";
311 compatible = "marvell,armada-370-crypto";
312 reg = <0x90000 0x10000>;
315 clocks = <&gateclk 23>;
316 clock-names = "cesa0";
317 marvell,crypto-srams = <&crypto_sram>;
318 marvell,crypto-sram-size = <0x7e0>;
322 crypto_sram: sa-sram {
323 compatible = "mmio-sram";
324 reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
326 clocks = <&gateclk 23>;
327 #address-cells = <1>;
329 ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
332 * The Armada 370 has an erratum preventing the use of
333 * the standard workflow for CPU idle support (relying
334 * on the BootROM code to enter/exit idle state).
335 * Reserve some amount of the crypto SRAM to put the
336 * cpuidle workaround.
346 compatible = "marvell,mv88f6710-pinctrl";
348 spi0_pins1: spi0-pins1 {
349 marvell,pins = "mpp33", "mpp34",
351 marvell,function = "spi0";
354 spi0_pins2: spi0_pins2 {
355 marvell,pins = "mpp32", "mpp63",
357 marvell,function = "spi0";
360 spi1_pins: spi1-pins {
361 marvell,pins = "mpp49", "mpp50",
363 marvell,function = "spi1";
366 uart0_pins: uart0-pins {
367 marvell,pins = "mpp0", "mpp1";
368 marvell,function = "uart0";
371 uart1_pins: uart1-pins {
372 marvell,pins = "mpp41", "mpp42";
373 marvell,function = "uart1";
376 sdio_pins1: sdio-pins1 {
377 marvell,pins = "mpp9", "mpp11", "mpp12",
378 "mpp13", "mpp14", "mpp15";
379 marvell,function = "sd0";
382 sdio_pins2: sdio-pins2 {
383 marvell,pins = "mpp47", "mpp48", "mpp49",
384 "mpp50", "mpp51", "mpp52";
385 marvell,function = "sd0";
388 sdio_pins3: sdio-pins3 {
389 marvell,pins = "mpp48", "mpp49", "mpp50",
390 "mpp51", "mpp52", "mpp53";
391 marvell,function = "sd0";
394 i2c0_pins: i2c0-pins {
395 marvell,pins = "mpp2", "mpp3";
396 marvell,function = "i2c0";
399 i2s_pins1: i2s-pins1 {
400 marvell,pins = "mpp5", "mpp6", "mpp7",
401 "mpp8", "mpp9", "mpp10",
403 marvell,function = "audio";
406 i2s_pins2: i2s-pins2 {
407 marvell,pins = "mpp49", "mpp47", "mpp50",
408 "mpp59", "mpp57", "mpp61",
409 "mpp62", "mpp60", "mpp58";
410 marvell,function = "audio";
413 mdio_pins: mdio-pins {
414 marvell,pins = "mpp17", "mpp18";
415 marvell,function = "ge";
418 ge0_rgmii_pins: ge0-rgmii-pins {
419 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
420 "mpp9", "mpp10", "mpp11", "mpp12",
421 "mpp13", "mpp14", "mpp15", "mpp16";
422 marvell,function = "ge0";
425 ge1_rgmii_pins: ge1-rgmii-pins {
426 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
427 "mpp23", "mpp24", "mpp25", "mpp26",
428 "mpp27", "mpp28", "mpp29", "mpp30";
429 marvell,function = "ge1";
434 * Default SPI pinctrl setting, can be overwritten on
435 * board level if a different configuration is used.
438 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
439 pinctrl-0 = <&spi0_pins1>;
440 pinctrl-names = "default";
444 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
445 pinctrl-0 = <&spi1_pins>;
446 pinctrl-names = "default";