arch/arm/boot/dts/armada-370.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Marvell Armada 370 family SoC
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * Contains definitions specific to the Armada 370 SoC that are not
  12  * common to all Armada SoCs.
  13  */
  14
  15 #include "armada-370-xp.dtsi"
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         model = "Marvell Armada 370 family SoC";
  22         compatible = "marvell,armada370", "marvell,armada-370-xp";
  23
  24         aliases {
  25                 gpio0 = &gpio0;
  26                 gpio1 = &gpio1;
  27                 gpio2 = &gpio2;
  28         };
  29
  30         soc {
  31                 compatible = "marvell,armada370-mbus", "simple-bus";
  32
  33                 bootrom {
  34                         compatible = "marvell,bootrom";
  35                         reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  36                 };
  37
  38                 pciec: pcie@82000000 {
  39                         compatible = "marvell,armada-370-pcie";
  40                         status = "disabled";
  41                         device_type = "pci";
  42
  43                         #address-cells = <3>;
  44                         #size-cells = <2>;
  45
  46                         msi-parent = <&mpic>;
  47                         bus-range = <0x00 0xff>;
  48
  49                         ranges =
  50                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  51                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  52                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
  53                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
  54                                 0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
  55                                 0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
  56
  57                         pcie0: pcie@1,0 {
  58                                 device_type = "pci";
  59                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  60                                 reg = <0x0800 0 0 0 0>;
  61                                 #address-cells = <3>;
  62                                 #size-cells = <2>;
  63                                 interrupt-names = "intx";
  64                                 interrupts-extended = <&mpic 58>;
  65                                 #interrupt-cells = <1>;
  66                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  67                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  68                                 bus-range = <0x00 0xff>;
  69                                 interrupt-map-mask = <0 0 0 7>;
  70                                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
  71                                                 <0 0 0 2 &pcie0_intc 1>,
  72                                                 <0 0 0 3 &pcie0_intc 2>,
  73                                                 <0 0 0 4 &pcie0_intc 3>;
  74                                 marvell,pcie-port = <0>;
  75                                 marvell,pcie-lane = <0>;
  76                                 clocks = <&gateclk 5>;
  77                                 status = "disabled";
  78
  79                                 pcie0_intc: interrupt-controller {
  80                                         interrupt-controller;
  81                                         #interrupt-cells = <1>;
  82                                 };
  83                         };
  84
  85                         pcie2: pcie@2,0 {
  86                                 device_type = "pci";
  87                                 assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
  88                                 reg = <0x1000 0 0 0 0>;
  89                                 #address-cells = <3>;
  90                                 #size-cells = <2>;
  91                                 interrupt-names = "intx";
  92                                 interrupts-extended = <&mpic 62>;
  93                                 #interrupt-cells = <1>;
  94                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  95                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
  96                                 bus-range = <0x00 0xff>;
  97                                 interrupt-map-mask = <0 0 0 7>;
  98                                 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
  99                                                 <0 0 0 2 &pcie2_intc 1>,
 100                                                 <0 0 0 3 &pcie2_intc 2>,
 101                                                 <0 0 0 4 &pcie2_intc 3>;
 102                                 marvell,pcie-port = <1>;
 103                                 marvell,pcie-lane = <0>;
 104                                 clocks = <&gateclk 9>;
 105                                 status = "disabled";
 106
 107                                 pcie2_intc: interrupt-controller {
 108                                         interrupt-controller;
 109                                         #interrupt-cells = <1>;
 110                                 };
 111                         };
 112                 };
 113
 114                 internal-regs {
 115                         L2: l2-cache@8000 {
 116                                 compatible = "marvell,aurora-outer-cache";
 117                                 reg = <0x08000 0x1000>;
 118                                 cache-id-part = <0x100>;
 119                                 cache-level = <2>;
 120                                 cache-unified;
 121                                 wt-override;
 122                         };
 123
 124                         gpio0: gpio@18100 {
 125                                 compatible = "marvell,armada-370-gpio",
 126                                              "marvell,orion-gpio";
 127                                 reg = <0x18100 0x40>, <0x181c0 0x08>;
 128                                 reg-names = "gpio", "pwm";
 129                                 ngpios = <32>;
 130                                 gpio-controller;
 131                                 #gpio-cells = <2>;
 132                                 #pwm-cells = <2>;
 133                                 interrupt-controller;
 134                                 #interrupt-cells = <2>;
 135                                 interrupts = <82>, <83>, <84>, <85>;
 136                                 clocks = <&coreclk 0>;
 137                         };
 138
 139                         gpio1: gpio@18140 {
 140                                 compatible = "marvell,armada-370-gpio",
 141                                              "marvell,orion-gpio";
 142                                 reg = <0x18140 0x40>, <0x181c8 0x08>;
 143                                 reg-names = "gpio", "pwm";
 144                                 ngpios = <32>;
 145                                 gpio-controller;
 146                                 #gpio-cells = <2>;
 147                                 #pwm-cells = <2>;
 148                                 interrupt-controller;
 149                                 #interrupt-cells = <2>;
 150                                 interrupts = <87>, <88>, <89>, <90>;
 151                                 clocks = <&coreclk 0>;
 152                         };
 153
 154                         gpio2: gpio@18180 {
 155                                 compatible = "marvell,armada-370-gpio",
 156                                              "marvell,orion-gpio";
 157                                 reg = <0x18180 0x40>;
 158                                 ngpios = <2>;
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                                 interrupt-controller;
 162                                 #interrupt-cells = <2>;
 163                                 interrupts = <91>;
 164                         };
 165
 166
 167                         systemc: system-controller@18200 {
 168                                 compatible = "marvell,armada-370-xp-system-controller";
 169                                 reg = <0x18200 0x100>;
 170                         };
 171
 172                         gateclk: clock-gating-control@18220 {
 173                                 compatible = "marvell,armada-370-gating-clock";
 174                                 reg = <0x18220 0x4>;
 175                                 clocks = <&coreclk 0>;
 176                                 #clock-cells = <1>;
 177                         };
 178
 179                         coreclk: mvebu-sar@18230 {
 180                                 compatible = "marvell,armada-370-core-clock";
 181                                 reg = <0x18230 0x08>;
 182                                 #clock-cells = <1>;
 183                         };
 184
 185                         thermal: thermal@18300 {
 186                                 compatible = "marvell,armada370-thermal";
 187                                 reg = <0x18300 0x4
 188                                         0x18304 0x4>;
 189                                 status = "okay";
 190                         };
 191
 192                         sscg: sscg@18330 {
 193                                 reg = <0x18330 0x4>;
 194                         };
 195
 196                         cpuconf: cpu-config@21000 {
 197                                 compatible = "marvell,armada-370-cpu-config";
 198                                 reg = <0x21000 0x8>;
 199                         };
 200
 201                         audio_controller: audio-controller@30000 {
 202                                 #sound-dai-cells = <1>;
 203                                 compatible = "marvell,armada370-audio";
 204                                 reg = <0x30000 0x4000>;
 205                                 interrupts = <93>;
 206                                 clocks = <&gateclk 0>;
 207                                 clock-names = "internal";
 208                                 status = "disabled";
 209                         };
 210
 211                         xor0: xor@60800 {
 212                                 compatible = "marvell,orion-xor";
 213                                 reg = <0x60800 0x100
 214                                        0x60A00 0x100>;
 215                                 status = "okay";
 216
 217                                 xor00 {
 218                                         interrupts = <51>;
 219                                         dmacap,memcpy;
 220                                         dmacap,xor;
 221                                 };
 222                                 xor01 {
 223                                         interrupts = <52>;
 224                                         dmacap,memcpy;
 225                                         dmacap,xor;
 226                                         dmacap,memset;
 227                                 };
 228                         };
 229
 230                         xor1: xor@60900 {
 231                                 compatible = "marvell,orion-xor";
 232                                 reg = <0x60900 0x100
 233                                        0x60b00 0x100>;
 234                                 status = "okay";
 235
 236                                 xor10 {
 237                                         interrupts = <94>;
 238                                         dmacap,memcpy;
 239                                         dmacap,xor;
 240                                 };
 241                                 xor11 {
 242                                         interrupts = <95>;
 243                                         dmacap,memcpy;
 244                                         dmacap,xor;
 245                                         dmacap,memset;
 246                                 };
 247                         };
 248
 249                         cesa: crypto@90000 {
 250                                 compatible = "marvell,armada-370-crypto";
 251                                 reg = <0x90000 0x10000>;
 252                                 reg-names = "regs";
 253                                 interrupts = <48>;
 254                                 clocks = <&gateclk 23>;
 255                                 clock-names = "cesa0";
 256                                 marvell,crypto-srams = <&crypto_sram>;
 257                                 marvell,crypto-sram-size = <0x7e0>;
 258                         };
 259                 };
 260
 261                 crypto_sram: sa-sram {
 262                         compatible = "mmio-sram";
 263                         reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
 264                         reg-names = "sram";
 265                         clocks = <&gateclk 23>;
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                         ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
 269
 270                         /*
 271                          * The Armada 370 has an erratum preventing the use of
 272                          * the standard workflow for CPU idle support (relying
 273                          * on the BootROM code to enter/exit idle state).
 274                          * Reserve some amount of the crypto SRAM to put the
 275                          * cpuidle workaround.
 276                          */
 277                         idle-sram@0 {
 278                                 reg = <0x0 0x20>;
 279                         };
 280                 };
 281         };
 282 };
 283
 284 /*
 285  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
 286  * board level if a different configuration is used.
 287  */
 288
 289 &uart0 {
 290         pinctrl-0 = <&uart0_pins>;
 291         pinctrl-names = "default";
 292 };
 293
 294 &uart1 {
 295         pinctrl-0 = <&uart1_pins>;
 296         pinctrl-names = "default";
 297 };
 298
 299 &i2c0 {
 300         reg = <0x11000 0x20>;
 301 };
 302
 303 &i2c1 {
 304         reg = <0x11100 0x20>;
 305 };
 306
 307 &mpic {
 308         reg = <0x20a00 0x1d0>, <0x21870 0x58>;
 309 };
 310
 311 &timer {
 312         compatible = "marvell,armada-370-timer";
 313         clocks = <&coreclk 2>;
 314 };
 315
 316 &watchdog {
 317         compatible = "marvell,armada-370-wdt";
 318         clocks = <&coreclk 2>;
 319 };
 320
 321 &usb0 {
 322         clocks = <&coreclk 0>;
 323 };
 324
 325 &usb1 {
 326         clocks = <&coreclk 0>;
 327 };
 328
 329 &eth0 {
 330         compatible = "marvell,armada-370-neta";
 331 };
 332
 333 &eth1 {
 334         compatible = "marvell,armada-370-neta";
 335 };
 336
 337 &pinctrl {
 338         compatible = "marvell,mv88f6710-pinctrl";
 339
 340         spi0_pins1: spi0-pins1 {
 341                 marvell,pins = "mpp33", "mpp34",
 342                                "mpp35", "mpp36";
 343                 marvell,function = "spi0";
 344         };
 345
 346         spi0_pins2: spi0_pins2 {
 347                 marvell,pins = "mpp32", "mpp63",
 348                                "mpp64", "mpp65";
 349                 marvell,function = "spi0";
 350         };
 351
 352         spi1_pins: spi1-pins {
 353                 marvell,pins = "mpp49", "mpp50",
 354                                "mpp51", "mpp52";
 355                 marvell,function = "spi1";
 356         };
 357
 358         uart0_pins: uart0-pins {
 359                 marvell,pins = "mpp0", "mpp1";
 360                 marvell,function = "uart0";
 361         };
 362
 363         uart1_pins: uart1-pins {
 364                 marvell,pins = "mpp41", "mpp42";
 365                 marvell,function = "uart1";
 366         };
 367
 368         sdio_pins1: sdio-pins1 {
 369                 marvell,pins = "mpp9",  "mpp11", "mpp12",
 370                                 "mpp13", "mpp14", "mpp15";
 371                 marvell,function = "sd0";
 372         };
 373
 374         sdio_pins2: sdio-pins2 {
 375                 marvell,pins = "mpp47", "mpp48", "mpp49",
 376                                 "mpp50", "mpp51", "mpp52";
 377                 marvell,function = "sd0";
 378         };
 379
 380         sdio_pins3: sdio-pins3 {
 381                 marvell,pins = "mpp48", "mpp49", "mpp50",
 382                                 "mpp51", "mpp52", "mpp53";
 383                 marvell,function = "sd0";
 384         };
 385
 386         i2c0_pins: i2c0-pins {
 387                 marvell,pins = "mpp2", "mpp3";
 388                 marvell,function = "i2c0";
 389         };
 390
 391         i2s_pins1: i2s-pins1 {
 392                 marvell,pins = "mpp5", "mpp6", "mpp7",
 393                                "mpp8", "mpp9", "mpp10",
 394                                "mpp12", "mpp13";
 395                 marvell,function = "audio";
 396         };
 397
 398         i2s_pins2: i2s-pins2 {
 399                 marvell,pins = "mpp49", "mpp47", "mpp50",
 400                                "mpp59", "mpp57", "mpp61",
 401                                "mpp62", "mpp60", "mpp58";
 402                 marvell,function = "audio";
 403         };
 404
 405         mdio_pins: mdio-pins {
 406                 marvell,pins = "mpp17", "mpp18";
 407                 marvell,function = "ge";
 408         };
 409
 410         ge0_rgmii_pins: ge0-rgmii-pins {
 411                 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
 412                                "mpp9", "mpp10", "mpp11", "mpp12",
 413                                "mpp13", "mpp14", "mpp15", "mpp16";
 414                 marvell,function = "ge0";
 415         };
 416
 417         ge1_rgmii_pins: ge1-rgmii-pins {
 418                 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
 419                                "mpp23", "mpp24", "mpp25", "mpp26",
 420                                "mpp27", "mpp28", "mpp29", "mpp30";
 421                 marvell,function = "ge1";
 422         };
 423 };
 424
 425 /*
 426  * Default SPI pinctrl setting, can be overwritten on
 427  * board level if a different configuration is used.
 428  */
 429 &spi0 {
 430         compatible = "marvell,armada-370-spi", "marvell,orion-spi";
 431         pinctrl-0 = <&spi0_pins1>;
 432         pinctrl-names = "default";
 433 };
 434
 435 &spi1 {
 436         compatible = "marvell,armada-370-spi", "marvell,orion-spi";
 437         pinctrl-0 = <&spi1_pins>;
 438         pinctrl-names = "default";
 439 };