1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell Armada 370 Reference Design board
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
8 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-370.dtsi"
27 model = "Marvell Armada 370 Reference Design";
28 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
31 stdout-path = "serial0:115200n8";
35 device_type = "memory";
36 reg = <0x00000000 0x20000000>; /* 512 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
59 pinctrl-0 = <&ge1_rgmii_pins>;
60 pinctrl-names = "default";
62 phy-mode = "rgmii-id";
70 pinctrl-0 = <&sdio_pins1>;
71 pinctrl-names = "default";
73 /* No CD or WP GPIOs */
86 compatible = "gpio-keys";
90 label = "Software Button";
91 linux,code = <KEY_POWER>;
92 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
97 compatible = "gpio-fan";
98 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
99 gpio-fan,speed-map = <0 0 3000 1>;
100 pinctrl-0 = <&fan_pins>;
101 pinctrl-names = "default";
105 compatible = "gpio-leds";
106 pinctrl-names = "default";
107 pinctrl-0 = <&led_pins>;
110 label = "370rd:green:sw";
111 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
112 default-state = "keep";
121 compatible = "marvell,dsa";
122 #address-cells = <2>;
125 dsa,ethernet = <ð1>;
126 dsa,mii-bus = <&mdio>;
129 #address-cells = <1>;
131 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
164 /* Internal mini-PCIe connector */
170 /* Internal mini-PCIe connector */
178 pinctrl-0 = <&mdio_pins>;
179 pinctrl-names = "default";
180 phy0: ethernet-phy@0 {
185 compatible = "marvell,mv88e6085";
186 #address-cells = <1>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 #address-cells = <1>;
228 #address-cells = <1>;
231 switchphy0: switchphy@0 {
233 interrupt-parent = <&switch>;
234 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
237 switchphy1: switchphy@1 {
239 interrupt-parent = <&switch>;
240 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
243 switchphy2: switchphy@2 {
245 interrupt-parent = <&switch>;
246 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
249 switchphy3: switchphy@3 {
251 interrupt-parent = <&switch>;
252 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
261 marvell,pins = "mpp8";
262 marvell,function = "gpio";
266 marvell,pins = "mpp32";
267 marvell,function = "gpio";
276 label = "pxa3xx_nand-0";
278 marvell,nand-keep-config;
282 compatible = "fixed-partitions";
283 #address-cells = <1>;
292 reg = <0x800000 0x800000>;
295 label = "Filesystem";
296 reg = <0x1000000 0x3f000000>;