2 * Copyright 2015 Linaro Ltd
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5 * of this software and associated documentation files (the "Software"), to deal
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9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
30 model = "ARM RealView PB11MPcore";
31 compatible = "arm,realview-pb11mp";
36 serial0 = &pb11mp_serial0;
37 serial1 = &pb11mp_serial1;
38 serial2 = &pb11mp_serial2;
39 serial3 = &pb11mp_serial3;
43 device_type = "memory";
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
54 enable-method = "arm,realview-smp";
58 compatible = "arm,arm11mpcore";
60 next-level-cache = <&L2>;
65 compatible = "arm,arm11mpcore";
67 next-level-cache = <&L2>;
72 compatible = "arm,arm11mpcore";
74 next-level-cache = <&L2>;
79 compatible = "arm,arm11mpcore";
81 next-level-cache = <&L2>;
85 /* Primary TestChip GIC synthesized with the CPU */
86 intc_tc11mp: interrupt-controller@1f000100 {
87 compatible = "arm,tc11mp-gic";
88 #interrupt-cells = <3>;
91 reg = <0x1f001000 0x1000>,
95 L2: cache-controller {
96 compatible = "arm,l220-cache";
97 reg = <0x1f002000 0x1000>;
98 interrupt-parent = <&intc_tc11mp>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
105 * Override default cache size, sets and
106 * associativity as these may be erroneously set
107 * up by boot loader(s), probably for safety
108 * since th outer sync operation can cause the
109 * cache to hang unless disabled.
111 cache-size = <1048576>; // 1MB
113 cache-line-size = <32>;
116 arm,outer-sync-disable;
120 compatible = "arm,arm11mp-scu";
121 reg = <0x1f000000 0x100>;
125 compatible = "arm,arm11mp-twd-timer";
126 reg = <0x1f000600 0x20>;
127 interrupt-parent = <&intc_tc11mp>;
128 interrupts = <1 13 0xf04>;
132 compatible = "arm,arm11mp-twd-wdt";
133 reg = <0x1f000620 0x20>;
134 interrupt-parent = <&intc_tc11mp>;
135 interrupts = <1 14 0xf04>;
138 /* PMU with one IRQ line per core */
140 compatible = "arm,arm11mpcore-pmu";
141 interrupt-parent = <&intc_tc11mp>;
142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
149 /* The voltage to the MMC card is hardwired at 3.3V */
150 vmmc: regulator-vmmc {
151 compatible = "regulator-fixed";
152 regulator-name = "vmmc";
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
158 veth: regulator-veth {
159 compatible = "regulator-fixed";
160 regulator-name = "veth";
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
166 xtal24mhz: xtal24mhz@24M {
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
172 refclk32khz: refclk32khz {
173 compatible = "fixed-clock";
175 clock-frequency = <32768>;
180 compatible = "fixed-factor-clock";
183 clocks = <&xtal24mhz>;
188 compatible = "fixed-factor-clock";
191 clocks = <&xtal24mhz>;
196 compatible = "fixed-factor-clock";
199 clocks = <&xtal24mhz>;
204 compatible = "fixed-factor-clock";
207 clocks = <&xtal24mhz>;
210 uartclk: uartclk@24M {
212 compatible = "fixed-factor-clock";
215 clocks = <&xtal24mhz>;
218 wdogclk: wdogclk@24M {
220 compatible = "fixed-factor-clock";
223 clocks = <&xtal24mhz>;
226 /* FIXME: this actually hangs off the PLL clocks */
229 compatible = "fixed-clock";
230 clock-frequency = <0>;
234 /* 2 * 32MiB NOR Flash memory */
235 compatible = "arm,versatile-flash", "cfi-flash";
236 reg = <0x40000000 0x04000000>;
239 compatible = "arm,arm-firmware-suite";
244 // 2 * 32MiB NOR Flash memory
245 compatible = "arm,versatile-flash", "cfi-flash";
246 reg = <0x44000000 0x04000000>;
249 compatible = "arm,arm-firmware-suite";
254 compatible = "ti,ths8134a", "ti,ths8134";
255 #address-cells = <1>;
259 #address-cells = <1>;
265 vga_bridge_in: endpoint {
266 remote-endpoint = <&clcd_pads>;
273 vga_bridge_out: endpoint {
274 remote-endpoint = <&vga_con_in>;
282 * This DDC I2C is connected directly to the DVI portions
283 * of the connector, so it's not really working when the
284 * monitor is connected to the VGA connector.
286 compatible = "vga-connector";
287 ddc-i2c-bus = <&i2c1>;
290 vga_con_in: endpoint {
291 remote-endpoint = <&vga_bridge_out>;
297 #address-cells = <1>;
299 compatible = "arm,realview-pb11mp-soc", "simple-bus";
300 regmap = <&pb11mp_syscon>;
303 pb11mp_syscon: syscon@10000000 {
304 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
305 reg = <0x10000000 0x1000>;
306 ranges = <0x0 0x10000000 0x1000>;
307 #address-cells = <1>;
311 compatible = "register-bit-led";
315 label = "versatile:0";
316 linux,default-trigger = "heartbeat";
317 default-state = "on";
320 compatible = "register-bit-led";
324 label = "versatile:1";
325 linux,default-trigger = "mmc0";
326 default-state = "off";
329 compatible = "register-bit-led";
333 label = "versatile:2";
334 linux,default-trigger = "cpu0";
335 default-state = "off";
338 compatible = "register-bit-led";
342 label = "versatile:3";
343 linux,default-trigger = "cpu1";
344 default-state = "off";
347 compatible = "register-bit-led";
351 label = "versatile:4";
352 linux,default-trigger = "cpu2";
353 default-state = "off";
356 compatible = "register-bit-led";
360 label = "versatile:5";
361 linux,default-trigger = "cpu3";
362 default-state = "off";
365 compatible = "register-bit-led";
369 label = "versatile:6";
370 default-state = "off";
373 compatible = "register-bit-led";
377 label = "versatile:7";
378 default-state = "off";
381 oscclk0: clock-controller@c {
382 compatible = "arm,syscon-icst307";
385 lock-offset = <0x20>;
387 clocks = <&xtal24mhz>;
389 oscclk1: clock-controller@10 {
390 compatible = "arm,syscon-icst307";
393 lock-offset = <0x20>;
395 clocks = <&xtal24mhz>;
397 oscclk2: clock-controller@14 {
398 compatible = "arm,syscon-icst307";
401 lock-offset = <0x20>;
403 clocks = <&xtal24mhz>;
405 oscclk3: clock-controller@18 {
406 compatible = "arm,syscon-icst307";
409 lock-offset = <0x20>;
411 clocks = <&xtal24mhz>;
413 oscclk4: clock-controller@1c {
414 compatible = "arm,syscon-icst307";
417 lock-offset = <0x20>;
419 clocks = <&xtal24mhz>;
421 oscclk5: clock-controller@d4 {
422 compatible = "arm,syscon-icst307";
425 lock-offset = <0x20>;
427 clocks = <&xtal24mhz>;
429 oscclk6: clock-controller@d8 {
430 compatible = "arm,syscon-icst307";
433 lock-offset = <0x20>;
435 clocks = <&xtal24mhz>;
439 sp810_syscon: sysctl@10001000 {
440 compatible = "arm,sp810", "arm,primecell";
441 reg = <0x10001000 0x1000>;
442 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
443 clock-names = "refclk", "timclk", "apb_pclk";
445 clock-output-names = "timerclk0",
449 assigned-clocks = <&sp810_syscon 0>,
453 assigned-clock-parents = <&timclk>,
460 #address-cells = <1>;
462 compatible = "arm,versatile-i2c";
463 reg = <0x10002000 0x1000>;
466 compatible = "dallas,ds1338";
471 aaci: aaci@10004000 {
472 compatible = "arm,pl041", "arm,primecell";
473 reg = <0x10004000 0x1000>;
474 interrupt-parent = <&intc_tc11mp>;
475 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
477 clock-names = "apb_pclk";
480 mci: mmcsd@10005000 {
481 compatible = "arm,pl18x", "arm,primecell";
482 reg = <0x10005000 0x1000>;
483 interrupt-parent = <&intc_tc11mp>;
484 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
485 <0 15 IRQ_TYPE_LEVEL_HIGH>;
486 /* Due to frequent FIFO overruns, use just 500 kHz */
487 max-frequency = <500000>;
491 clocks = <&mclk>, <&pclk>;
492 clock-names = "mclk", "apb_pclk";
493 vmmc-supply = <&vmmc>;
494 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
495 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
499 compatible = "arm,pl050", "arm,primecell";
500 reg = <0x10006000 0x1000>;
501 interrupt-parent = <&intc_tc11mp>;
502 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&kmiclk>, <&pclk>;
504 clock-names = "KMIREFCLK", "apb_pclk";
508 compatible = "arm,pl050", "arm,primecell";
509 reg = <0x10007000 0x1000>;
510 interrupt-parent = <&intc_tc11mp>;
511 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&kmiclk>, <&pclk>;
513 clock-names = "KMIREFCLK", "apb_pclk";
516 pb11mp_serial0: serial@10009000 {
517 compatible = "arm,pl011", "arm,primecell";
518 reg = <0x10009000 0x1000>;
519 interrupt-parent = <&intc_tc11mp>;
520 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&uartclk>, <&pclk>;
522 clock-names = "uartclk", "apb_pclk";
525 pb11mp_serial1: serial@1000a000 {
526 compatible = "arm,pl011", "arm,primecell";
527 reg = <0x1000a000 0x1000>;
528 interrupt-parent = <&intc_tc11mp>;
529 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&uartclk>, <&pclk>;
531 clock-names = "uartclk", "apb_pclk";
534 pb11mp_serial2: serial@1000b000 {
535 compatible = "arm,pl011", "arm,primecell";
536 reg = <0x1000b000 0x1000>;
537 interrupt-parent = <&intc_pb11mp>;
538 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&uartclk>, <&pclk>;
540 clock-names = "uartclk", "apb_pclk";
543 pb11mp_serial3: serial@1000c000 {
544 compatible = "arm,pl011", "arm,primecell";
545 reg = <0x1000c000 0x1000>;
546 interrupt-parent = <&intc_pb11mp>;
547 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&uartclk>, <&pclk>;
549 clock-names = "uartclk", "apb_pclk";
553 compatible = "arm,pl022", "arm,primecell";
554 reg = <0x1000d000 0x1000>;
555 interrupt-parent = <&intc_pb11mp>;
556 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&sspclk>, <&pclk>;
558 clock-names = "sspclk", "apb_pclk";
562 compatible = "arm,sp805", "arm,primecell";
563 reg = <0x1000f000 0x1000>;
564 interrupt-parent = <&intc_pb11mp>;
565 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&wdogclk>, <&pclk>;
567 clock-names = "wdog_clk", "apb_pclk";
572 compatible = "arm,sp805", "arm,primecell";
573 reg = <0x10010000 0x1000>;
574 interrupt-parent = <&intc_pb11mp>;
575 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&wdogclk>, <&pclk>;
577 clock-names = "wdog_clk", "apb_pclk";
580 timer01: timer@10011000 {
581 compatible = "arm,sp804", "arm,primecell";
582 reg = <0x10011000 0x1000>;
583 interrupt-parent = <&intc_tc11mp>;
584 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
585 arm,sp804-has-irq = <1>;
586 clocks = <&sp810_syscon 0>,
589 clock-names = "timer0clk",
594 timer23: timer@10012000 {
595 compatible = "arm,sp804", "arm,primecell";
596 reg = <0x10012000 0x1000>;
597 interrupt-parent = <&intc_tc11mp>;
598 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
599 arm,sp804-has-irq = <1>;
600 clocks = <&sp810_syscon 2>,
603 clock-names = "timer0clk",
608 gpio0: gpio@10013000 {
609 compatible = "arm,pl061", "arm,primecell";
610 reg = <0x10013000 0x1000>;
612 interrupt-parent = <&intc_pb11mp>;
613 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
618 clock-names = "apb_pclk";
621 gpio1: gpio@10014000 {
622 compatible = "arm,pl061", "arm,primecell";
623 reg = <0x10014000 0x1000>;
625 interrupt-parent = <&intc_pb11mp>;
626 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
631 clock-names = "apb_pclk";
634 gpio2: gpio@10015000 {
635 compatible = "arm,pl061", "arm,primecell";
636 reg = <0x10015000 0x1000>;
638 interrupt-parent = <&intc_pb11mp>;
639 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
641 interrupt-controller;
642 #interrupt-cells = <2>;
644 clock-names = "apb_pclk";
648 #address-cells = <1>;
650 compatible = "arm,versatile-i2c";
651 reg = <0x10016000 0x1000>;
655 compatible = "arm,pl031", "arm,primecell";
656 reg = <0x10017000 0x1000>;
657 interrupt-parent = <&intc_tc11mp>;
658 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
660 clock-names = "apb_pclk";
663 timer45: timer@10018000 {
664 compatible = "arm,sp804", "arm,primecell";
665 reg = <0x10018000 0x1000>;
666 clocks = <&timclk>, <&timclk>, <&pclk>;
667 clock-names = "timer0clk", "timer1clk", "apb_pclk";
671 timer67: timer@10019000 {
672 compatible = "arm,sp804", "arm,primecell";
673 reg = <0x10019000 0x1000>;
674 clocks = <&timclk>, <&timclk>, <&pclk>;
675 clock-names = "timer0clk", "timer1clk", "apb_pclk";
681 compatible = "arm,pl111", "arm,primecell";
682 reg = <0x10020000 0x1000>;
683 interrupt-parent = <&intc_pb11mp>;
684 interrupt-names = "combined";
685 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&oscclk4>, <&pclk>;
687 clock-names = "clcdclk", "apb_pclk";
688 /* 1024x768 16bpp @65MHz works fine */
689 max-memory-bandwidth = <95000000>;
692 clcd_pads: endpoint {
693 remote-endpoint = <&vga_bridge_in>;
694 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
700 * This GIC on the Platform Baseboard is cascaded off the
703 intc_pb11mp: interrupt-controller@1e000000 {
704 compatible = "arm,arm11mp-gic";
705 #interrupt-cells = <3>;
706 #address-cells = <1>;
707 interrupt-controller;
708 reg = <0x1e001000 0x1000>,
710 interrupt-parent = <&intc_tc11mp>;
711 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
714 /* SMSC 9118 ethernet with PHY and EEPROM */
716 compatible = "smsc,lan9118", "smsc,lan9115";
717 reg = <0x4e000000 0x10000>;
718 interrupt-parent = <&intc_tc11mp>;
719 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
722 smsc,irq-active-high;
724 vdd33a-supply = <&veth>;
725 vddvario-supply = <&veth>;
729 compatible = "nxp,usb-isp1761";
730 reg = <0x4f000000 0x20000>;
731 interrupt-parent = <&intc_tc11mp>;
732 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
733 dr_mode = "peripheral";