2 * Copyright 2016 Linaro Ltd
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
29 compatible = "arm,realview-eb";
42 device_type = "memory";
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
47 /* The voltage to the MMC card is hardwired at 3.3V */
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
56 xtal24mhz: xtal24mhz@24M {
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
64 compatible = "fixed-factor-clock";
67 clocks = <&xtal24mhz>;
72 compatible = "fixed-factor-clock";
75 clocks = <&xtal24mhz>;
80 compatible = "fixed-factor-clock";
83 clocks = <&xtal24mhz>;
88 compatible = "fixed-factor-clock";
91 clocks = <&xtal24mhz>;
94 uartclk: uartclk@24M {
96 compatible = "fixed-factor-clock";
99 clocks = <&xtal24mhz>;
102 wdogclk: wdogclk@24M {
104 compatible = "fixed-factor-clock";
107 clocks = <&xtal24mhz>;
110 /* FIXME: this actually hangs off the PLL clocks */
113 compatible = "fixed-clock";
114 clock-frequency = <0>;
118 /* 2 * 32MiB NOR Flash memory */
119 compatible = "arm,versatile-flash", "cfi-flash";
120 reg = <0x40000000 0x04000000>;
123 compatible = "arm,arm-firmware-suite";
128 /* 2 * 32MiB NOR Flash memory */
129 compatible = "arm,versatile-flash", "cfi-flash";
130 reg = <0x44000000 0x04000000>;
133 compatible = "arm,arm-firmware-suite";
137 /* SMSC LAN91C111 ethernet with PHY and EEPROM */
138 ethernet: ethernet@4e000000 {
139 compatible = "smsc,lan91c111";
140 reg = <0x4e000000 0x10000>;
142 * This means the adapter can be accessed with 8, 16 or
143 * 32 bit reads/writes.
149 compatible = "nxp,usb-isp1761";
150 reg = <0x4f000000 0x20000>;
151 dr_mode = "peripheral";
155 compatible = "ti,ths8134a", "ti,ths8134";
156 #address-cells = <1>;
160 #address-cells = <1>;
166 vga_bridge_in: endpoint {
167 remote-endpoint = <&clcd_pads>;
174 vga_bridge_out: endpoint {
175 remote-endpoint = <&vga_con_in>;
182 compatible = "vga-connector";
185 vga_con_in: endpoint {
186 remote-endpoint = <&vga_bridge_out>;
191 /* These peripherals are inside the FPGA */
193 #address-cells = <1>;
195 compatible = "simple-bus";
198 syscon: syscon@10000000 {
199 compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
200 reg = <0x10000000 0x1000>;
201 ranges = <0x0 0x10000000 0x1000>;
202 #address-cells = <1>;
206 compatible = "register-bit-led";
210 label = "versatile:0";
211 linux,default-trigger = "heartbeat";
212 default-state = "on";
215 compatible = "register-bit-led";
219 label = "versatile:1";
220 linux,default-trigger = "mmc0";
221 default-state = "off";
224 compatible = "register-bit-led";
228 label = "versatile:2";
229 linux,default-trigger = "cpu0";
230 default-state = "off";
233 compatible = "register-bit-led";
237 label = "versatile:3";
238 default-state = "off";
241 compatible = "register-bit-led";
245 label = "versatile:4";
246 default-state = "off";
249 compatible = "register-bit-led";
253 label = "versatile:5";
254 default-state = "off";
257 compatible = "register-bit-led";
261 label = "versatile:6";
262 default-state = "off";
265 compatible = "register-bit-led";
269 label = "versatile:7";
270 default-state = "off";
272 oscclk0: clock-controller@c {
273 compatible = "arm,syscon-icst307";
276 lock-offset = <0x20>;
278 clocks = <&xtal24mhz>;
280 oscclk1: clock-controller@10 {
281 compatible = "arm,syscon-icst307";
284 lock-offset = <0x20>;
286 clocks = <&xtal24mhz>;
288 oscclk2: clock-controller@14 {
289 compatible = "arm,syscon-icst307";
292 lock-offset = <0x20>;
294 clocks = <&xtal24mhz>;
296 oscclk3: clock-controller@18 {
297 compatible = "arm,syscon-icst307";
300 lock-offset = <0x20>;
302 clocks = <&xtal24mhz>;
304 oscclk4: clock-controller@1c {
305 compatible = "arm,syscon-icst307";
308 lock-offset = <0x20>;
310 clocks = <&xtal24mhz>;
315 #address-cells = <1>;
317 compatible = "arm,versatile-i2c";
318 reg = <0x10002000 0x1000>;
321 compatible = "dallas,ds1338";
326 aaci: aaci@10004000 {
327 compatible = "arm,pl041", "arm,primecell";
328 reg = <0x10004000 0x1000>;
330 clock-names = "apb_pclk";
333 mmc: mmcsd@10005000 {
334 compatible = "arm,pl18x", "arm,primecell";
335 reg = <0x10005000 0x1000>;
337 /* Due to frequent FIFO overruns, use just 500 kHz */
338 max-frequency = <500000>;
342 clocks = <&mclk>, <&pclk>;
343 clock-names = "mclk", "apb_pclk";
344 vmmc-supply = <&vmmc>;
345 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
346 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
350 compatible = "arm,pl050", "arm,primecell";
351 reg = <0x10006000 0x1000>;
352 clocks = <&kmiclk>, <&pclk>;
353 clock-names = "KMIREFCLK", "apb_pclk";
357 compatible = "arm,pl050", "arm,primecell";
358 reg = <0x10007000 0x1000>;
359 clocks = <&kmiclk>, <&pclk>;
360 clock-names = "KMIREFCLK", "apb_pclk";
363 charlcd: fpga_charlcd: charlcd@10008000 {
364 compatible = "arm,versatile-lcd";
365 reg = <0x10008000 0x1000>;
367 clock-names = "apb_pclk";
370 serial0: serial@10009000 {
371 compatible = "arm,pl011", "arm,primecell";
372 reg = <0x10009000 0x1000>;
373 clocks = <&uartclk>, <&pclk>;
374 clock-names = "uartclk", "apb_pclk";
377 serial1: serial@1000a000 {
378 compatible = "arm,pl011", "arm,primecell";
379 reg = <0x1000a000 0x1000>;
380 clocks = <&uartclk>, <&pclk>;
381 clock-names = "uartclk", "apb_pclk";
384 serial2: serial@1000b000 {
385 compatible = "arm,pl011", "arm,primecell";
386 reg = <0x1000b000 0x1000>;
387 clocks = <&uartclk>, <&pclk>;
388 clock-names = "uartclk", "apb_pclk";
391 serial3: serial@1000c000 {
392 compatible = "arm,pl011", "arm,primecell";
393 reg = <0x1000c000 0x1000>;
394 clocks = <&uartclk>, <&pclk>;
395 clock-names = "uartclk", "apb_pclk";
399 compatible = "arm,pl022", "arm,primecell";
400 reg = <0x1000d000 0x1000>;
401 clocks = <&sspclk>, <&pclk>;
402 clock-names = "sspclk", "apb_pclk";
405 wdog: watchdog@10010000 {
406 compatible = "arm,sp805", "arm,primecell";
407 reg = <0x10010000 0x1000>;
408 clocks = <&wdogclk>, <&pclk>;
409 clock-names = "wdog_clk", "apb_pclk";
413 timer01: timer@10011000 {
414 compatible = "arm,sp804", "arm,primecell";
415 reg = <0x10011000 0x1000>;
416 clocks = <&timclk>, <&timclk>, <&pclk>;
417 clock-names = "timer1", "timer2", "apb_pclk";
420 timer23: timer@10012000 {
421 compatible = "arm,sp804", "arm,primecell";
422 reg = <0x10012000 0x1000>;
423 clocks = <&timclk>, <&timclk>, <&pclk>;
424 clock-names = "timer1", "timer2", "apb_pclk";
427 gpio0: gpio@10013000 {
428 compatible = "arm,pl061", "arm,primecell";
429 reg = <0x10013000 0x1000>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
435 clock-names = "apb_pclk";
438 gpio1: gpio@10014000 {
439 compatible = "arm,pl061", "arm,primecell";
440 reg = <0x10014000 0x1000>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
446 clock-names = "apb_pclk";
449 gpio2: gpio@10015000 {
450 compatible = "arm,pl061", "arm,primecell";
451 reg = <0x10015000 0x1000>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
457 clock-names = "apb_pclk";
461 compatible = "arm,pl031", "arm,primecell";
462 reg = <0x10017000 0x1000>;
464 clock-names = "apb_pclk";
467 clcd: clcd@10020000 {
468 compatible = "arm,pl111", "arm,primecell";
469 reg = <0x10020000 0x1000>;
470 interrupt-names = "combined";
471 clocks = <&oscclk0>, <&pclk>;
472 clock-names = "clcdclk", "apb_pclk";
473 /* 1024x768 16bpp @65MHz works fine */
474 max-memory-bandwidth = <95000000>;
477 clcd_pads: endpoint {
478 remote-endpoint = <&vga_bridge_in>;
479 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;