2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/am4.h>
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
24 device_type = "memory";
38 ethernet0 = &cpsw_port1;
39 ethernet1 = &cpsw_port2;
47 compatible = "arm,cortex-a9";
48 enable-method = "ti,am4372";
52 clocks = <&dpll_mpu_ck>;
55 operating-points-v2 = <&cpu0_opp_table>;
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cpu-idle-states = <&mpu_gate>;
63 compatible = "arm,idle-state";
64 entry-latency-us = <40>;
65 exit-latency-us = <100>;
66 min-residency-us = <300>;
72 cpu0_opp_table: opp-table {
73 compatible = "operating-points-v2-ti-cpu";
77 opp-hz = /bits/ 64 <300000000>;
78 opp-microvolt = <950000 931000 969000>;
79 opp-supported-hw = <0xFF 0x01>;
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0xFF 0x04>;
90 opp-hz = /bits/ 64 <720000000>;
91 opp-microvolt = <1200000 1176000 1224000>;
92 opp-supported-hw = <0xFF 0x08>;
96 opp-hz = /bits/ 64 <800000000>;
97 opp-microvolt = <1260000 1234800 1285200>;
98 opp-supported-hw = <0xFF 0x10>;
101 oppnitro-1000000000 {
102 opp-hz = /bits/ 64 <1000000000>;
103 opp-microvolt = <1325000 1298500 1351500>;
104 opp-supported-hw = <0xFF 0x20>;
109 compatible = "ti,omap-infra";
112 gic: interrupt-controller@48241000 {
113 compatible = "arm,cortex-a9-gic";
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 reg = <0x48241000 0x1000>,
118 interrupt-parent = <&gic>;
121 wakeupgen: interrupt-controller@48281000 {
122 compatible = "ti,omap4-wugen-mpu";
123 interrupt-controller;
124 #interrupt-cells = <3>;
125 reg = <0x48281000 0x1000>;
126 interrupt-parent = <&gic>;
130 compatible = "arm,cortex-a9-scu";
131 reg = <0x48240000 0x100>;
134 global_timer: timer@48240200 {
135 compatible = "arm,cortex-a9-global-timer";
136 reg = <0x48240200 0x100>;
137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
138 interrupt-parent = <&gic>;
139 clocks = <&mpu_periphclk>;
142 local_timer: timer@48240600 {
143 compatible = "arm,cortex-a9-twd-timer";
144 reg = <0x48240600 0x100>;
145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
146 interrupt-parent = <&gic>;
147 clocks = <&mpu_periphclk>;
150 cache-controller@48242000 {
151 compatible = "arm,pl310-cache";
152 reg = <0x48242000 0x1000>;
158 compatible = "simple-pm-bus";
159 power-domains = <&prm_per>;
160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
162 #address-cells = <1>;
168 compatible = "ti,am4372-l3-noc";
169 reg = <0x44000000 0x400000>,
170 <0x44800000 0x400000>;
171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
175 l4_wkup: interconnect@44c00000 {
177 l4_per: interconnect@48000000 {
179 l4_fast: interconnect@4a000000 {
182 target-module@4c000000 {
183 compatible = "ti,sysc-omap4-simple", "ti,sysc";
184 reg = <0x4c000000 0x4>;
186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
189 #address-cells = <1>;
191 ranges = <0x0 0x4c000000 0x1000000>;
194 compatible = "ti,emif-am4372";
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 sram = <&pm_sram_code
202 target-module@49000000 {
203 compatible = "ti,sysc-omap4", "ti,sysc";
204 reg = <0x49000000 0x4>;
206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
208 #address-cells = <1>;
210 ranges = <0x0 0x49000000 0x10000>;
213 compatible = "ti,edma3-tpcc";
215 reg-names = "edma3_cc";
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "edma3_ccint", "edma3_mperr",
224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
227 ti,edma-memcpy-channels = <58 59>;
231 target-module@49800000 {
232 compatible = "ti,sysc-omap4", "ti,sysc";
233 reg = <0x49800000 0x4>,
235 reg-names = "rev", "sysc";
236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
237 ti,sysc-midle = <SYSC_IDLE_FORCE>;
238 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
242 #address-cells = <1>;
244 ranges = <0x0 0x49800000 0x100000>;
247 compatible = "ti,edma3-tptc";
249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-names = "edma3_tcerrint";
254 target-module@49900000 {
255 compatible = "ti,sysc-omap4", "ti,sysc";
256 reg = <0x49900000 0x4>,
258 reg-names = "rev", "sysc";
259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
260 ti,sysc-midle = <SYSC_IDLE_FORCE>;
261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
265 #address-cells = <1>;
267 ranges = <0x0 0x49900000 0x100000>;
270 compatible = "ti,edma3-tptc";
272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "edma3_tcerrint";
277 target-module@49a00000 {
278 compatible = "ti,sysc-omap4", "ti,sysc";
279 reg = <0x49a00000 0x4>,
281 reg-names = "rev", "sysc";
282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
283 ti,sysc-midle = <SYSC_IDLE_FORCE>;
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
288 #address-cells = <1>;
290 ranges = <0x0 0x49a00000 0x100000>;
293 compatible = "ti,edma3-tptc";
295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "edma3_tcerrint";
300 target-module@47810000 {
301 compatible = "ti,sysc-omap2", "ti,sysc";
302 reg = <0x478102fc 0x4>,
305 reg-names = "rev", "sysc", "syss";
306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
307 SYSC_OMAP2_ENAWAKEUP |
308 SYSC_OMAP2_SOFTRESET |
309 SYSC_OMAP2_AUTOIDLE)>;
310 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
316 #address-cells = <1>;
318 ranges = <0x0 0x47810000 0x1000>;
321 compatible = "ti,am437-sdhci";
322 ti,needs-special-reset;
323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
329 sham_target: target-module@53100000 {
330 compatible = "ti,sysc-omap3-sham", "ti,sysc";
331 reg = <0x53100100 0x4>,
334 reg-names = "rev", "sysc", "syss";
335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
336 SYSC_OMAP2_AUTOIDLE)>;
337 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
341 /* Domains (P, C): per_pwrdm, l3_clkdm */
342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
344 #address-cells = <1>;
346 ranges = <0x0 0x53100000 0x1000>;
349 compatible = "ti,omap5-sham";
353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
357 aes_target: target-module@53501000 {
358 compatible = "ti,sysc-omap2", "ti,sysc";
359 reg = <0x53501080 0x4>,
362 reg-names = "rev", "sysc", "syss";
363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
364 SYSC_OMAP2_AUTOIDLE)>;
365 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
368 <SYSC_IDLE_SMART_WKUP>;
370 /* Domains (P, C): per_pwrdm, l3_clkdm */
371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
373 #address-cells = <1>;
375 ranges = <0x0 0x53501000 0x1000>;
378 compatible = "ti,omap4-aes";
380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
383 dma-names = "tx", "rx";
387 des_target: target-module@53701000 {
388 compatible = "ti,sysc-omap2", "ti,sysc";
389 reg = <0x53701030 0x4>,
392 reg-names = "rev", "sysc", "syss";
393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
394 SYSC_OMAP2_AUTOIDLE)>;
395 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398 <SYSC_IDLE_SMART_WKUP>;
400 /* Domains (P, C): per_pwrdm, l3_clkdm */
401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
403 #address-cells = <1>;
405 ranges = <0 0x53701000 0x1000>;
408 compatible = "ti,omap4-des";
410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
413 dma-names = "tx", "rx";
417 pruss_tm: target-module@54400000 {
418 compatible = "ti,sysc-pruss", "ti,sysc";
419 reg = <0x54426000 0x4>,
421 reg-names = "rev", "sysc";
422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
423 SYSC_PRUSS_SUB_MWAIT)>;
424 ti,sysc-midle = <SYSC_IDLE_FORCE>,
427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
432 resets = <&prm_per 1>;
433 reset-names = "rstctrl";
434 #address-cells = <1>;
436 ranges = <0x0 0x54400000 0x80000>;
439 compatible = "ti,am4376-pruss1";
441 #address-cells = <1>;
445 pruss1_mem: memories@0 {
449 reg-names = "dram0", "dram1",
453 pruss1_cfg: cfg@26000 {
454 compatible = "ti,pruss-cfg", "syscon";
455 reg = <0x26000 0x2000>;
456 #address-cells = <1>;
458 ranges = <0x0 0x26000 0x2000>;
461 #address-cells = <1>;
464 pruss1_iepclk_mux: iepclk-mux@30 {
467 clocks = <&sysclk_div>, /* icss_iep_gclk */
468 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
473 pruss1_mii_rt: mii-rt@32000 {
474 compatible = "ti,pruss-mii", "syscon";
475 reg = <0x32000 0x58>;
478 pruss1_intc: interrupt-controller@20000 {
479 compatible = "ti,pruss-intc";
480 reg = <0x20000 0x2000>;
481 interrupt-controller;
482 #interrupt-cells = <3>;
483 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
490 interrupt-names = "host_intr0", "host_intr1",
491 "host_intr2", "host_intr3",
493 "host_intr6", "host_intr7";
494 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
498 compatible = "ti,am4376-pru";
499 reg = <0x34000 0x3000>,
502 reg-names = "iram", "control", "debug";
503 firmware-name = "am437x-pru1_0-fw";
507 compatible = "ti,am4376-pru";
508 reg = <0x38000 0x3000>,
511 reg-names = "iram", "control", "debug";
512 firmware-name = "am437x-pru1_1-fw";
515 pruss1_mdio: mdio@32400 {
516 compatible = "ti,davinci_mdio";
517 reg = <0x32400 0x90>;
518 clocks = <&dpll_core_m4_ck>;
520 bus_freq = <1000000>;
521 #address-cells = <1>;
526 pruss0: pruss@40000 {
527 compatible = "ti,am4376-pruss0";
528 reg = <0x40000 0x40000>;
529 #address-cells = <1>;
533 pruss0_mem: memories@40000 {
534 reg = <0x40000 0x1000>,
536 reg-names = "dram0", "dram1";
539 pruss0_cfg: cfg@66000 {
540 compatible = "ti,pruss-cfg", "syscon";
541 reg = <0x66000 0x2000>;
542 #address-cells = <1>;
544 ranges = <0x0 0x66000 0x2000>;
547 #address-cells = <1>;
550 pruss0_iepclk_mux: iepclk-mux@30 {
553 clocks = <&sysclk_div>, /* icss_iep_gclk */
554 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
559 pruss0_mii_rt: mii-rt@72000 {
560 compatible = "ti,pruss-mii", "syscon";
561 reg = <0x72000 0x58>;
565 pruss0_intc: interrupt-controller@60000 {
566 compatible = "ti,pruss-intc";
567 reg = <0x60000 0x2000>;
568 interrupt-controller;
569 #interrupt-cells = <3>;
570 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "host_intr0", "host_intr1",
578 "host_intr2", "host_intr3",
580 "host_intr6", "host_intr7";
581 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
585 compatible = "ti,am4376-pru";
586 reg = <0x74000 0x1000>,
589 reg-names = "iram", "control", "debug";
590 firmware-name = "am437x-pru0_0-fw";
594 compatible = "ti,am4376-pru";
595 reg = <0x78000 0x1000>,
598 reg-names = "iram", "control", "debug";
599 firmware-name = "am437x-pru0_1-fw";
604 target-module@50000000 {
605 compatible = "ti,sysc-omap2", "ti,sysc";
606 reg = <0x50000000 4>,
609 reg-names = "rev", "sysc", "syss";
610 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
614 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
616 #address-cells = <1>;
618 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
619 <0x00000000 0x00000000 0x40000000>; /* data */
621 gpmc: gpmc@50000000 {
622 compatible = "ti,am3352-gpmc";
625 clocks = <&l3s_gclk>;
627 reg = <0x50000000 0x2000>;
628 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
630 gpmc,num-waitpins = <2>;
631 #address-cells = <2>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
641 target-module@47900000 {
642 compatible = "ti,sysc-omap4", "ti,sysc";
643 reg = <0x47900000 0x4>,
645 reg-names = "rev", "sysc";
646 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
649 <SYSC_IDLE_SMART_WKUP>;
650 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
652 #address-cells = <1>;
654 ranges = <0x0 0x47900000 0x1000>,
655 <0x30000000 0x30000000 0x4000000>;
658 compatible = "ti,am4372-qspi";
660 <0x30000000 0x4000000>;
661 reg-names = "qspi_base", "qspi_mmap";
662 clocks = <&dpll_per_m2_div4_ck>;
664 #address-cells = <1>;
666 interrupts = <0 138 0x4>;
671 target-module@40300000 {
672 compatible = "ti,sysc-omap4-simple", "ti,sysc";
673 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
676 #address-cells = <1>;
678 ranges = <0 0x40300000 0x40000>;
681 compatible = "mmio-sram";
682 reg = <0 0x40000>; /* 256k */
683 ranges = <0 0 0x40000>;
684 #address-cells = <1>;
687 pm_sram_code: pm-code-sram@0 {
688 compatible = "ti,sram";
693 pm_sram_data: pm-data-sram@1000 {
694 compatible = "ti,sram";
695 reg = <0x1000 0x1000>;
701 target-module@56000000 {
702 compatible = "ti,sysc-omap4", "ti,sysc";
703 reg = <0x5600fe00 0x4>,
705 reg-names = "rev", "sysc";
706 ti,sysc-midle = <SYSC_IDLE_FORCE>,
709 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
712 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
714 power-domains = <&prm_gfx>;
715 resets = <&prm_gfx 0>;
716 reset-names = "rstctrl";
717 #address-cells = <1>;
719 ranges = <0 0x56000000 0x1000000>;
724 #include "am437x-l4.dtsi"
725 #include "am43xx-clocks.dtsi"
729 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
731 #power-domain-cells = <0>;
735 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
737 #power-domain-cells = <0>;
742 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
744 #power-domain-cells = <0>;
747 prm_tamper: prm@600 {
748 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
750 #power-domain-cells = <0>;
753 prm_cefuse: prm@700 {
754 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
756 #power-domain-cells = <0>;
760 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
763 #power-domain-cells = <0>;
767 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
768 reg = <0x2000 0x100>;
770 #power-domain-cells = <0>;
773 prm_device: prm@4000 {
774 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
775 reg = <0x4000 0x100>;
780 /* Preferred always-on timer for clocksource */
784 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
785 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
786 clock-names = "fck", "ick";
788 assigned-clocks = <&timer1_fck>;
789 assigned-clock-parents = <&sys_clkin_ck>;
793 /* Preferred timer for clockevent */
797 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
798 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
799 clock-names = "fck", "ick";
801 assigned-clocks = <&timer2_fck>;
802 assigned-clock-parents = <&sys_clkin_ck>;