1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33XX SoC
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
36 ethernet0 = &cpsw_port1;
37 ethernet1 = &cpsw_port2;
49 compatible = "arm,cortex-a8";
50 enable-method = "ti,am3352";
54 operating-points-v2 = <&cpu0_opp_table>;
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu-idle-states = <&mpu_gate>;
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
147 target-module@4b000000 {
148 compatible = "ti,sysc-omap4-simple", "ti,sysc";
149 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
152 #address-cells = <1>;
154 ranges = <0x0 0x4b000000 0x1000000>;
156 target-module@140000 {
157 compatible = "ti,sysc-omap4-simple", "ti,sysc";
158 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
160 #address-cells = <1>;
162 ranges = <0x0 0x140000 0xec0000>;
165 compatible = "arm,cortex-a8-pmu";
172 * The soc node represents the soc top level view. It is used for IPs
173 * that are not memory mapped in the MPU view or for the MPU itself.
176 compatible = "ti,omap-infra";
180 * XXX: Use a flat representation of the AM33XX interconnect.
181 * The real AM33XX interconnect network is quite complex. Since
182 * it will not bring real advantage to represent that in DT
183 * for the moment, just use a fake OCP bus entry to represent
184 * the whole bus hierarchy.
187 compatible = "simple-pm-bus";
188 power-domains = <&prm_per>;
189 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
191 #address-cells = <1>;
195 l4_wkup: interconnect@44c00000 {
197 l4_per: interconnect@48000000 {
199 l4_fw: interconnect@47c00000 {
201 l4_fast: interconnect@4a000000 {
203 l4_mpuss: interconnect@4b140000 {
206 intc: interrupt-controller@48200000 {
207 compatible = "ti,am33xx-intc";
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 reg = <0x48200000 0x1000>;
213 target-module@49000000 {
214 compatible = "ti,sysc-omap4", "ti,sysc";
215 reg = <0x49000000 0x4>;
217 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
219 #address-cells = <1>;
221 ranges = <0x0 0x49000000 0x10000>;
224 compatible = "ti,edma3-tpcc";
226 reg-names = "edma3_cc";
227 interrupts = <12 13 14>;
228 interrupt-names = "edma3_ccint", "edma3_mperr",
233 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
236 ti,edma-memcpy-channels = <20 21>;
240 target-module@49800000 {
241 compatible = "ti,sysc-omap4", "ti,sysc";
242 reg = <0x49800000 0x4>,
244 reg-names = "rev", "sysc";
245 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
246 ti,sysc-midle = <SYSC_IDLE_FORCE>;
247 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
249 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
251 #address-cells = <1>;
253 ranges = <0x0 0x49800000 0x100000>;
256 compatible = "ti,edma3-tptc";
259 interrupt-names = "edma3_tcerrint";
263 target-module@49900000 {
264 compatible = "ti,sysc-omap4", "ti,sysc";
265 reg = <0x49900000 0x4>,
267 reg-names = "rev", "sysc";
268 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
269 ti,sysc-midle = <SYSC_IDLE_FORCE>;
270 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
272 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
274 #address-cells = <1>;
276 ranges = <0x0 0x49900000 0x100000>;
279 compatible = "ti,edma3-tptc";
282 interrupt-names = "edma3_tcerrint";
286 target-module@49a00000 {
287 compatible = "ti,sysc-omap4", "ti,sysc";
288 reg = <0x49a00000 0x4>,
290 reg-names = "rev", "sysc";
291 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
292 ti,sysc-midle = <SYSC_IDLE_FORCE>;
293 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
295 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
297 #address-cells = <1>;
299 ranges = <0x0 0x49a00000 0x100000>;
302 compatible = "ti,edma3-tptc";
305 interrupt-names = "edma3_tcerrint";
309 target-module@47810000 {
310 compatible = "ti,sysc-omap2", "ti,sysc";
311 reg = <0x478102fc 0x4>,
314 reg-names = "rev", "sysc", "syss";
315 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
316 SYSC_OMAP2_ENAWAKEUP |
317 SYSC_OMAP2_SOFTRESET |
318 SYSC_OMAP2_AUTOIDLE)>;
319 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
323 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
325 #address-cells = <1>;
327 ranges = <0x0 0x47810000 0x1000>;
330 compatible = "ti,am335-sdhci";
331 ti,needs-special-reset;
338 usb: target-module@47400000 {
339 compatible = "ti,sysc-omap4", "ti,sysc";
340 reg = <0x47400000 0x4>,
342 reg-names = "rev", "sysc";
343 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
344 SYSC_OMAP4_SOFTRESET)>;
345 ti,sysc-midle = <SYSC_IDLE_FORCE>,
348 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
351 <SYSC_IDLE_SMART_WKUP>;
352 ti,sysc-delay-us = <2>;
353 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
355 #address-cells = <1>;
357 ranges = <0x0 0x47400000 0x8000>;
359 usb0_phy: usb-phy@1300 {
360 compatible = "ti,am335x-usb-phy";
361 reg = <0x1300 0x100>;
363 ti,ctrl_mod = <&usb_ctrl_mod>;
368 compatible = "ti,musb-am33xx";
369 reg = <0x1400 0x400>,
371 reg-names = "mc", "control";
374 interrupt-names = "mc";
376 mentor,multipoint = <1>;
377 mentor,num-eps = <16>;
378 mentor,ram-bits = <12>;
379 mentor,power = <500>;
382 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
383 &cppi41dma 2 0 &cppi41dma 3 0
384 &cppi41dma 4 0 &cppi41dma 5 0
385 &cppi41dma 6 0 &cppi41dma 7 0
386 &cppi41dma 8 0 &cppi41dma 9 0
387 &cppi41dma 10 0 &cppi41dma 11 0
388 &cppi41dma 12 0 &cppi41dma 13 0
389 &cppi41dma 14 0 &cppi41dma 0 1
390 &cppi41dma 1 1 &cppi41dma 2 1
391 &cppi41dma 3 1 &cppi41dma 4 1
392 &cppi41dma 5 1 &cppi41dma 6 1
393 &cppi41dma 7 1 &cppi41dma 8 1
394 &cppi41dma 9 1 &cppi41dma 10 1
395 &cppi41dma 11 1 &cppi41dma 12 1
396 &cppi41dma 13 1 &cppi41dma 14 1>;
398 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
399 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
401 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
402 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
406 usb1_phy: usb-phy@1b00 {
407 compatible = "ti,am335x-usb-phy";
408 reg = <0x1b00 0x100>;
410 ti,ctrl_mod = <&usb_ctrl_mod>;
415 compatible = "ti,musb-am33xx";
416 reg = <0x1c00 0x400>,
418 reg-names = "mc", "control";
420 interrupt-names = "mc";
422 mentor,multipoint = <1>;
423 mentor,num-eps = <16>;
424 mentor,ram-bits = <12>;
425 mentor,power = <500>;
428 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
429 &cppi41dma 17 0 &cppi41dma 18 0
430 &cppi41dma 19 0 &cppi41dma 20 0
431 &cppi41dma 21 0 &cppi41dma 22 0
432 &cppi41dma 23 0 &cppi41dma 24 0
433 &cppi41dma 25 0 &cppi41dma 26 0
434 &cppi41dma 27 0 &cppi41dma 28 0
435 &cppi41dma 29 0 &cppi41dma 15 1
436 &cppi41dma 16 1 &cppi41dma 17 1
437 &cppi41dma 18 1 &cppi41dma 19 1
438 &cppi41dma 20 1 &cppi41dma 21 1
439 &cppi41dma 22 1 &cppi41dma 23 1
440 &cppi41dma 24 1 &cppi41dma 25 1
441 &cppi41dma 26 1 &cppi41dma 27 1
442 &cppi41dma 28 1 &cppi41dma 29 1>;
444 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
445 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
447 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
448 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
452 cppi41dma: dma-controller@2000 {
453 compatible = "ti,am3359-cppi41";
454 reg = <0x0000 0x1000>,
458 reg-names = "glue", "controller", "scheduler", "queuemgr";
460 interrupt-names = "glue";
462 /* For backwards compatibility: */
463 #dma-channels = <30>;
465 #dma-requests = <256>;
466 dma-requests = <256>;
470 target-module@40300000 {
471 compatible = "ti,sysc-omap4-simple", "ti,sysc";
472 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
475 #address-cells = <1>;
477 ranges = <0 0x40300000 0x10000>;
480 compatible = "mmio-sram";
481 reg = <0 0x10000>; /* 64k */
482 ranges = <0 0 0x10000>;
483 #address-cells = <1>;
486 pm_sram_code: pm-code-sram@0 {
487 compatible = "ti,sram";
492 pm_sram_data: pm-data-sram@1000 {
493 compatible = "ti,sram";
494 reg = <0x1000 0x1000>;
500 target-module@4c000000 {
501 compatible = "ti,sysc-omap4-simple", "ti,sysc";
502 reg = <0x4c000000 0x4>;
504 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
507 #address-cells = <1>;
509 ranges = <0x0 0x4c000000 0x1000000>;
512 compatible = "ti,emif-am3352";
515 sram = <&pm_sram_code
520 target-module@50000000 {
521 compatible = "ti,sysc-omap2", "ti,sysc";
522 reg = <0x50000000 4>,
525 reg-names = "rev", "sysc", "syss";
526 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
530 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
532 #address-cells = <1>;
534 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
535 <0x00000000 0x00000000 0x40000000>; /* data */
537 gpmc: gpmc@50000000 {
538 compatible = "ti,am3352-gpmc";
539 reg = <0x50000000 0x2000>;
544 gpmc,num-waitpins = <2>;
545 #address-cells = <2>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
555 sham_target: target-module@53100000 {
556 compatible = "ti,sysc-omap3-sham", "ti,sysc";
557 reg = <0x53100100 0x4>,
560 reg-names = "rev", "sysc", "syss";
561 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
562 SYSC_OMAP2_AUTOIDLE)>;
563 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
567 /* Domains (P, C): per_pwrdm, l3_clkdm */
568 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
570 #address-cells = <1>;
572 ranges = <0x0 0x53100000 0x1000>;
575 compatible = "ti,omap4-sham";
583 aes_target: target-module@53500000 {
584 compatible = "ti,sysc-omap2", "ti,sysc";
585 reg = <0x53500080 0x4>,
588 reg-names = "rev", "sysc", "syss";
589 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
590 SYSC_OMAP2_AUTOIDLE)>;
591 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
594 <SYSC_IDLE_SMART_WKUP>;
596 /* Domains (P, C): per_pwrdm, l3_clkdm */
597 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
599 #address-cells = <1>;
601 ranges = <0x0 0x53500000 0x1000>;
604 compatible = "ti,omap4-aes";
609 dma-names = "tx", "rx";
613 target-module@56000000 {
614 compatible = "ti,sysc-omap4", "ti,sysc";
615 reg = <0x5600fe00 0x4>,
617 reg-names = "rev", "sysc";
618 ti,sysc-midle = <SYSC_IDLE_FORCE>,
621 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
624 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
626 power-domains = <&prm_gfx>;
627 resets = <&prm_gfx 0>;
628 reset-names = "rstctrl";
629 #address-cells = <1>;
631 ranges = <0 0x56000000 0x1000000>;
634 * Closed source PowerVR driver, no child device
635 * binding or driver in mainline
641 #include "am33xx-l4.dtsi"
642 #include "am33xx-clocks.dtsi"
646 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
649 #power-domain-cells = <0>;
653 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
656 #power-domain-cells = <0>;
660 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
662 #power-domain-cells = <0>;
665 prm_device: prm@f00 {
666 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
672 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
673 reg = <0x1000 0x100>;
674 #power-domain-cells = <0>;
678 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
679 reg = <0x1100 0x100>;
680 #power-domain-cells = <0>;
684 prm_cefuse: prm@1200 {
685 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
686 reg = <0x1200 0x100>;
687 #power-domain-cells = <0>;
691 /* Preferred always-on timer for clocksource */
693 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
694 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
695 clock-names = "fck", "ick";
699 assigned-clocks = <&timer1_fck>;
700 assigned-clock-parents = <&sys_clkin_ck>;
704 /* Preferred timer for clockevent */
706 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
707 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
708 clock-names = "fck", "ick";
712 assigned-clocks = <&timer2_fck>;
713 assigned-clock-parents = <&sys_clkin_ck>;