1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
9 cpu0-supply = <&dcdc2_reg>;
14 device_type = "memory";
15 reg = <0x80000000 0x10000000>; /* 256 MB */
23 pinctrl-names = "default";
24 pinctrl-0 = <&user_leds_s0>;
26 compatible = "gpio-leds";
29 label = "beaglebone:green:heartbeat";
30 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
31 linux,default-trigger = "heartbeat";
32 default-state = "off";
36 label = "beaglebone:green:mmc0";
37 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
38 linux,default-trigger = "mmc0";
39 default-state = "off";
43 label = "beaglebone:green:usr2";
44 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
45 linux,default-trigger = "cpu0";
46 default-state = "off";
50 label = "beaglebone:green:usr3";
51 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
52 linux,default-trigger = "mmc1";
53 default-state = "off";
57 vmmcsd_fixed: fixedregulator0 {
58 compatible = "regulator-fixed";
59 regulator-name = "vmmcsd_fixed";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&clkout2_pin>;
69 user_leds_s0: user_leds_s0 {
70 pinctrl-single,pins = <
71 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
72 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */
73 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */
74 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */
78 i2c0_pins: pinmux_i2c0_pins {
79 pinctrl-single,pins = <
80 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */
81 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */
85 i2c2_pins: pinmux_i2c2_pins {
86 pinctrl-single,pins = <
87 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */
88 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */
92 uart0_pins: pinmux_uart0_pins {
93 pinctrl-single,pins = <
94 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
95 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
99 clkout2_pin: pinmux_clkout2_pin {
100 pinctrl-single,pins = <
101 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
105 cpsw_default: cpsw_default {
106 pinctrl-single,pins = <
108 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
109 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
110 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
111 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
112 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
113 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
114 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
115 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
116 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
117 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
118 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
119 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
120 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
124 cpsw_sleep: cpsw_sleep {
125 pinctrl-single,pins = <
126 /* Slave 1 reset value */
127 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
128 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
129 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
130 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
131 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
132 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
133 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
134 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
135 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
136 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
137 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
138 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
139 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
143 davinci_mdio_default: davinci_mdio_default {
144 pinctrl-single,pins = <
146 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
147 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
151 davinci_mdio_sleep: davinci_mdio_sleep {
152 pinctrl-single,pins = <
153 /* MDIO reset value */
154 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
155 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
159 mmc1_pins: pinmux_mmc1_pins {
160 pinctrl-single,pins = <
161 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */
162 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
163 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
164 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
165 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
166 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
167 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
171 emmc_pins: pinmux_emmc_pins {
172 pinctrl-single,pins = <
173 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
174 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
175 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
176 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
177 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
178 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
179 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
180 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
181 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
182 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
188 pinctrl-names = "default";
189 pinctrl-0 = <&uart0_pins>;
212 dr_mode = "peripheral";
213 interrupts-extended = <&intc 18 &tps 0>;
214 interrupt-names = "mc", "vbus";
227 pinctrl-names = "default";
228 pinctrl-0 = <&i2c0_pins>;
231 clock-frequency = <400000>;
237 baseboard_eeprom: baseboard_eeprom@50 {
238 compatible = "atmel,24c256";
241 #address-cells = <1>;
243 baseboard_data: baseboard_data@0 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&i2c2_pins>;
254 clock-frequency = <100000>;
256 cape_eeprom0: cape_eeprom0@54 {
257 compatible = "atmel,24c256";
259 #address-cells = <1>;
261 cape0_data: cape_data@0 {
266 cape_eeprom1: cape_eeprom1@55 {
267 compatible = "atmel,24c256";
269 #address-cells = <1>;
271 cape1_data: cape_data@0 {
276 cape_eeprom2: cape_eeprom2@56 {
277 compatible = "atmel,24c256";
279 #address-cells = <1>;
281 cape2_data: cape_data@0 {
286 cape_eeprom3: cape_eeprom3@57 {
287 compatible = "atmel,24c256";
289 #address-cells = <1>;
291 cape3_data: cape_data@0 {
298 /include/ "tps65217.dtsi"
302 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
303 * mode") at poweroff. Most BeagleBone versions do not support RTC-only
304 * mode and risk hardware damage if this mode is entered.
306 * For details, see linux-omap mailing list May 2015 thread
307 * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
308 * In particular, messages:
309 * http://www.spinics.net/lists/linux-omap/msg118585.html
310 * http://www.spinics.net/lists/linux-omap/msg118615.html
312 * You can override this later with
313 * &tps { /delete-property/ ti,pmic-shutdown-controller; }
314 * if you want to use RTC-only mode and made sure you are not affected
315 * by the hardware problems. (Tip: double-check by performing a current
316 * measurement after shutdown: it should be less than 1 mA.)
319 interrupts = <7>; /* NMI */
320 interrupt-parent = <&intc>;
322 ti,pmic-shutdown-controller;
333 dcdc1_reg: regulator@0 {
334 regulator-name = "vdds_dpr";
338 dcdc2_reg: regulator@1 {
339 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
340 regulator-name = "vdd_mpu";
341 regulator-min-microvolt = <925000>;
342 regulator-max-microvolt = <1351500>;
347 dcdc3_reg: regulator@2 {
348 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
349 regulator-name = "vdd_core";
350 regulator-min-microvolt = <925000>;
351 regulator-max-microvolt = <1150000>;
356 ldo1_reg: regulator@3 {
357 regulator-name = "vio,vrtc,vdds";
361 ldo2_reg: regulator@4 {
362 regulator-name = "vdd_3v3aux";
366 ldo3_reg: regulator@5 {
367 regulator-name = "vdd_1v8";
371 ldo4_reg: regulator@6 {
372 regulator-name = "vdd_3v3a";
379 phy-handle = <ðphy0>;
385 pinctrl-names = "default", "sleep";
386 pinctrl-0 = <&cpsw_default>;
387 pinctrl-1 = <&cpsw_sleep>;
392 pinctrl-names = "default", "sleep";
393 pinctrl-0 = <&davinci_mdio_default>;
394 pinctrl-1 = <&davinci_mdio_sleep>;
397 ethphy0: ethernet-phy@0 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&mmc1_pins>;
407 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
419 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
420 clock-names = "ext-clk", "int-clk";