1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/boot/compressed/head.S
5 * Copyright (C) 1996-2002 Russell King
6 * Copyright (C) 2004 Hyok S. Choi (MPU support)
8 #include <linux/linkage.h>
9 #include <asm/assembler.h>
12 #include "efi-header.S"
14 AR_CLASS( .arch armv7-a )
15 M_CLASS( .arch armv7-m )
20 * Note that these macros must not contain any code which is not
21 * 100% relocatable. Any attempt to do so will result in a crash.
22 * Please select one of the following when turning on debugging.
26 #if defined(CONFIG_DEBUG_ICEDCC)
28 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
29 .macro loadsp, rb, tmp1, tmp2
32 mcr p14, 0, \ch, c0, c5, 0
34 #elif defined(CONFIG_CPU_XSCALE)
35 .macro loadsp, rb, tmp1, tmp2
38 mcr p14, 0, \ch, c8, c0, 0
41 .macro loadsp, rb, tmp1, tmp2
44 mcr p14, 0, \ch, c1, c0, 0
50 #include CONFIG_DEBUG_LL_INCLUDE
56 #if defined(CONFIG_ARCH_SA1100)
57 .macro loadsp, rb, tmp1, tmp2
58 mov \rb, #0x80000000 @ physical base address
59 #ifdef CONFIG_DEBUG_LL_SER3
60 add \rb, \rb, #0x00050000 @ Ser3
62 add \rb, \rb, #0x00010000 @ Ser1
66 .macro loadsp, rb, tmp1, tmp2
67 addruart \rb, \tmp1, \tmp2
84 .macro debug_reloc_start
87 kphex r6, 8 /* processor id */
89 kphex r7, 8 /* architecture id */
90 #ifdef CONFIG_CPU_CP15
92 mrc p15, 0, r0, c1, c0
93 kphex r0, 8 /* control reg */
96 kphex r5, 8 /* decompressed kernel start */
98 kphex r9, 8 /* decompressed kernel end */
100 kphex r4, 8 /* kernel execution address */
105 .macro debug_reloc_end
107 kphex r5, 8 /* end of kernel */
110 bl memdump /* dump 256 bytes at start of kernel */
115 * Debug kernel copy by printing the memory addresses involved
117 .macro dbgkc, begin, end, cbegin, cend
124 kphex \begin, 8 /* Start of compressed kernel */
128 kphex \end, 8 /* End of compressed kernel */
133 kphex \cbegin, 8 /* Start of kernel copy */
137 kphex \cend, 8 /* End of kernel copy */
143 .section ".start", "ax"
145 * sort out different calling conventions
149 * Always enter in ARM state for CPUs that support the ARM ISA.
150 * As of today (2014) that's exactly the members of the A and R
155 .type start,#function
157 * These 7 nops along with the 1 nop immediately below for
158 * !THUMB2 form 8 nops that make the compressed kernel bootable
159 * on legacy ARM systems that were assuming the kernel in a.out
160 * binary format. The boot loaders on these systems would
161 * jump 32 bytes into the image to skip the a.out header.
162 * with these 8 nops filling exactly 32 bytes, things still
163 * work as expected on these legacy systems. Thumb2 mode keeps
164 * 7 of the nops as it turns out that some boot loaders
165 * were patching the initial instructions of the kernel, i.e
166 * had started to exploit this "patch area".
172 #ifndef CONFIG_THUMB2_KERNEL
175 AR_CLASS( sub pc, pc, #3 ) @ A/R: switch to Thumb2 mode
176 M_CLASS( nop.w ) @ M: already in Thumb2 mode
181 .word _magic_sig @ Magic numbers to help the loader
182 .word _magic_start @ absolute load/run zImage address
183 .word _magic_end @ zImage end address
184 .word 0x04030201 @ endianness flag
185 .word 0x45454545 @ another magic number to indicate
186 .word _magic_table @ additional data table
190 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
191 AR_CLASS( mrs r9, cpsr )
192 #ifdef CONFIG_ARM_VIRT_EXT
193 bl __hyp_stub_install @ get into SVC mode, reversibly
195 mov r7, r1 @ save architecture ID
196 mov r8, r2 @ save atags pointer
198 #ifndef CONFIG_CPU_V7M
200 * Booting from Angel - need to enter SVC mode and disable
201 * FIQs/IRQs (numeric definitions from angel arm.h source).
202 * We only do this if we were in user mode on entry.
204 mrs r2, cpsr @ get current mode
205 tst r2, #3 @ not user?
207 mov r0, #0x17 @ angel_SWIreason_EnterSVC
208 ARM( swi 0x123456 ) @ angel_SWI_ARM
209 THUMB( svc 0xab ) @ angel_SWI_THUMB
211 safe_svcmode_maskall r0
212 msr spsr_cxsf, r9 @ Save the CPU boot mode in
216 * Note that some cache flushing and other stuff may
217 * be needed here - is there an Angel SWI call for this?
221 * some architecture specific code can be inserted
222 * by the linker here, but it should preserve r7, r8, and r9.
227 #ifdef CONFIG_AUTO_ZRELADDR
229 * Find the start of physical memory. As we are executing
230 * without the MMU on, we are in the physical address space.
231 * We just need to get rid of any offset by aligning the
234 * This alignment is a balance between the requirements of
235 * different platforms - we have chosen 128MB to allow
236 * platforms which align the start of their physical memory
237 * to 128MB to use this feature, while allowing the zImage
238 * to be placed within the first 128MB of memory on other
239 * platforms. Increasing the alignment means we place
240 * stricter alignment requirements on the start of physical
241 * memory, but relaxing it means that we break people who
242 * are already placing their zImage in (eg) the top 64MB
246 and r4, r4, #0xf8000000
247 /* Determine final kernel image address. */
248 add r4, r4, #TEXT_OFFSET
254 * Set up a page table only if it won't overwrite ourself.
255 * That means r4 < pc || r4 - 16k page directory > &_end.
256 * Given that r4 > &_end is most unfrequent, we add a rough
257 * additional 1MB of room for a possible appended DTB.
264 orrcc r4, r4, #1 @ remember we skipped cache_on
268 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
272 * We might be running at a different address. We need
273 * to fix up various pointers.
275 sub r0, r0, r1 @ calculate the delta offset
276 add r6, r6, r0 @ _edata
277 add r10, r10, r0 @ inflated kernel size location
280 * The kernel build system appends the size of the
281 * decompressed kernel at the end of the compressed data
282 * in little-endian form.
286 orr r9, r9, lr, lsl #8
289 orr r9, r9, lr, lsl #16
290 orr r9, r9, r10, lsl #24
292 #ifndef CONFIG_ZBOOT_ROM
293 /* malloc space is above the relocated stack (64k max) */
295 add r10, sp, #0x10000
298 * With ZBOOT_ROM the bss/stack is non relocatable,
299 * but someone could still run this code from RAM,
300 * in which case our reference is _edata.
305 mov r5, #0 @ init dtb size to 0
306 #ifdef CONFIG_ARM_APPENDED_DTB
311 * r4 = final kernel address (possibly with LSB set)
312 * r5 = appended dtb size (still unknown)
314 * r7 = architecture ID
315 * r8 = atags/device tree pointer
316 * r9 = size of decompressed image
317 * r10 = end of this image, including bss/stack/malloc space if non XIP
322 * if there are device trees (dtb) appended to zImage, advance r10 so that the
323 * dtb data will get relocated along with the kernel if necessary.
328 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
333 bne dtb_check_done @ not found
335 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
337 * OK... Let's do some funky business here.
338 * If we do have a DTB appended to zImage, and we do have
339 * an ATAG list around, we want the later to be translated
340 * and folded into the former here. No GOT fixup has occurred
341 * yet, but none of the code we're about to call uses any
345 /* Get the initial DTB size */
348 /* convert to little endian */
349 eor r1, r5, r5, ror #16
350 bic r1, r1, #0x00ff0000
352 eor r5, r5, r1, lsr #8
354 /* 50% DTB growth should be good enough */
355 add r5, r5, r5, lsr #1
356 /* preserve 64-bit alignment */
359 /* clamp to 32KB min and 1MB max */
364 /* temporarily relocate the stack past the DTB work space */
367 stmfd sp!, {r0-r3, ip, lr}
374 * If returned value is 1, there is no ATAG at the location
375 * pointed by r8. Try the typical 0x100 offset from start
376 * of RAM and hope for the best.
379 sub r0, r4, #TEXT_OFFSET
386 ldmfd sp!, {r0-r3, ip, lr}
390 mov r8, r6 @ use the appended device tree
393 * Make sure that the DTB doesn't end up in the final
394 * kernel's .bss area. To do so, we adjust the decompressed
395 * kernel size to compensate if that .bss size is larger
396 * than the relocated code.
398 ldr r5, =_kernel_bss_size
399 adr r1, wont_overwrite
404 /* Get the current DTB size */
407 /* convert r5 (dtb size) to little endian */
408 eor r1, r5, r5, ror #16
409 bic r1, r1, #0x00ff0000
411 eor r5, r5, r1, lsr #8
414 /* preserve 64-bit alignment */
418 /* relocate some pointers past the appended dtb */
426 * Check to see if we will overwrite ourselves.
427 * r4 = final kernel address (possibly with LSB set)
428 * r9 = size of decompressed image
429 * r10 = end of this image, including bss/stack/malloc space if non XIP
431 * r4 - 16k page directory >= r10 -> OK
432 * r4 + image length <= address of wont_overwrite -> OK
433 * Note: the possible LSB in r4 is harmless here.
439 adr r9, wont_overwrite
444 * Relocate ourselves past the end of the decompressed kernel.
446 * r10 = end of the decompressed kernel
447 * Because we always copy ahead, we need to do it from the end and go
448 * backward in case the source and destination overlap.
451 * Bump to the next 256-byte boundary with the size of
452 * the relocation code added. This avoids overwriting
453 * ourself when the offset is small.
455 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
458 /* Get start of code we want to copy and align it down. */
462 /* Relocate the hyp vector base if necessary */
463 #ifdef CONFIG_ARM_VIRT_EXT
465 and r0, r0, #MODE_MASK
470 * Compute the address of the hyp vectors after relocation.
471 * This requires some arithmetic since we cannot directly
472 * reference __hyp_stub_vectors in a PC-relative way.
473 * Call __hyp_set_vectors with the new address so that we
474 * can HVC again after the copy.
477 movw r1, #:lower16:__hyp_stub_vectors - 0b
478 movt r1, #:upper16:__hyp_stub_vectors - 0b
486 sub r9, r6, r5 @ size to copy
487 add r9, r9, #31 @ rounded up to a multiple
488 bic r9, r9, #31 @ ... of 32 bytes
496 * We are about to copy the kernel to a new memory area.
497 * The boundaries of the new memory area can be found in
498 * r10 and r9, whilst r5 and r6 contain the boundaries
499 * of the memory we are going to copy.
500 * Calling dbgkc will help with the printing of this
503 dbgkc r5, r6, r10, r9
506 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
508 stmdb r9!, {r0 - r3, r10 - r12, lr}
511 /* Preserve offset to relocated code. */
514 #ifndef CONFIG_ZBOOT_ROM
515 /* cache_clean_flush may use the stack, so relocate it */
527 * If delta is zero, we are running at the address we were linked at.
531 * r4 = kernel execution address (possibly with LSB set)
532 * r5 = appended dtb size (0 if not present)
533 * r7 = architecture ID
545 #ifndef CONFIG_ZBOOT_ROM
547 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
548 * we need to fix up pointers into the BSS region.
549 * Note that the stack pointer has already been fixed up.
555 * Relocate all entries in the GOT table.
556 * Bump bss entries to _edata + dtb size
558 1: ldr r1, [r11, #0] @ relocate entries in the GOT
559 add r1, r1, r0 @ This fixes up C references
560 cmp r1, r2 @ if entry >= bss_start &&
561 cmphs r3, r1 @ bss_end > entry
562 addhi r1, r1, r5 @ entry += dtb size
563 str r1, [r11], #4 @ next entry
567 /* bump our bss pointers too */
574 * Relocate entries in the GOT table. We only relocate
575 * the entries that are outside the (relocated) BSS region.
577 1: ldr r1, [r11, #0] @ relocate entries in the GOT
578 cmp r1, r2 @ entry < bss_start ||
579 cmphs r3, r1 @ _end < entry
580 addlo r1, r1, r0 @ table. This fixes up the
581 str r1, [r11], #4 @ C references.
586 not_relocated: mov r0, #0
587 1: str r0, [r2], #4 @ clear bss
595 * Did we skip the cache setup earlier?
596 * That is indicated by the LSB in r4.
604 * The C runtime environment should now be setup sufficiently.
605 * Set up some pointers, and start decompressing.
606 * r4 = kernel execution address
607 * r7 = architecture ID
611 mov r1, sp @ malloc space above stack
612 add r2, sp, #0x10000 @ 64k max
618 #ifdef CONFIG_ARM_VIRT_EXT
619 mrs r0, spsr @ Get saved CPU boot mode
620 and r0, r0, #MODE_MASK
621 cmp r0, #HYP_MODE @ if not booted in HYP mode...
622 bne __enter_kernel @ boot kernel directly
624 adr r12, .L__hyp_reentry_vectors_offset
629 __HVC(0) @ otherwise bounce to hyp mode
631 b . @ should never be reached
634 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
642 .word __bss_start @ r2
645 .word input_data_end - 4 @ r10 (inflated size location)
646 .word _got_start @ r11
648 .word .L_user_stack_end @ sp
649 .word _end - restart + 16384 + 1024*1024
652 #ifdef CONFIG_ARCH_RPC
654 params: ldr r0, =0x10000100 @ params_phys for RPC
661 * Turn on the cache. We need to setup some page tables so that we
662 * can have both the I and D caches on.
664 * We place the page tables 16k down from the kernel execution address,
665 * and we hope that nothing else is using it. If we're using it, we
669 * r4 = kernel execution address
670 * r7 = architecture number
673 * r0, r1, r2, r3, r9, r10, r12 corrupted
674 * This routine must preserve:
678 cache_on: mov r3, #8 @ cache_on function
682 * Initialize the highest priority protection region, PR7
683 * to cover all 32bit address and cacheable and bufferable.
685 __armv4_mpu_cache_on:
686 mov r0, #0x3f @ 4G, the whole
687 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
688 mcr p15, 0, r0, c6, c7, 1
691 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
692 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
693 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
696 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
697 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
700 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
701 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
702 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
703 mrc p15, 0, r0, c1, c0, 0 @ read control reg
704 @ ...I .... ..D. WC.M
705 orr r0, r0, #0x002d @ .... .... ..1. 11.1
706 orr r0, r0, #0x1000 @ ...1 .... .... ....
708 mcr p15, 0, r0, c1, c0, 0 @ write control reg
711 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
712 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
715 __armv3_mpu_cache_on:
716 mov r0, #0x3f @ 4G, the whole
717 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
720 mcr p15, 0, r0, c2, c0, 0 @ cache on
721 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
724 mcr p15, 0, r0, c5, c0, 0 @ access permission
727 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
729 * ?? ARMv3 MMU does not allow reading the control register,
730 * does this really work on ARMv3 MPU?
732 mrc p15, 0, r0, c1, c0, 0 @ read control reg
733 @ .... .... .... WC.M
734 orr r0, r0, #0x000d @ .... .... .... 11.1
735 /* ?? this overwrites the value constructed above? */
737 mcr p15, 0, r0, c1, c0, 0 @ write control reg
739 /* ?? invalidate for the second time? */
740 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
743 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
749 __setup_mmu: sub r3, r4, #16384 @ Page directory size
750 bic r3, r3, #0xff @ Align the pointer
753 * Initialise the page tables, turning on the cacheable and bufferable
754 * bits for the RAM area only.
758 mov r9, r9, lsl #18 @ start of RAM
759 add r10, r9, #0x10000000 @ a reasonable RAM size
760 mov r1, #0x12 @ XN|U + section mapping
761 orr r1, r1, #3 << 10 @ AP=11
763 1: cmp r1, r9 @ if virt > start of RAM
764 cmphs r10, r1 @ && end of RAM > virt
765 bic r1, r1, #0x1c @ clear XN|U + C + B
766 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
767 orrhs r1, r1, r6 @ set RAM section settings
768 str r1, [r0], #4 @ 1:1 mapping
773 * If ever we are running from Flash, then we surely want the cache
774 * to be enabled also for our execution instance... We map 2MB of it
775 * so there is no map overlap problem for up to 1 MB compressed kernel.
776 * If the execution is in RAM then we would only be duplicating the above.
778 orr r1, r6, #0x04 @ ensure B is set for this
782 orr r1, r1, r2, lsl #20
783 add r0, r3, r2, lsl #2
790 @ Enable unaligned access on v6, to allow better code generation
791 @ for the decompressor C code:
792 __armv6_mmu_cache_on:
793 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
794 bic r0, r0, #2 @ A (no unaligned access fault)
795 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
796 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
797 b __armv4_mmu_cache_on
799 __arm926ejs_mmu_cache_on:
800 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
801 mov r0, #4 @ put dcache in WT mode
802 mcr p15, 7, r0, c15, c0, 0
805 __armv4_mmu_cache_on:
808 mov r6, #CB_BITS | 0x12 @ U
811 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
812 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
813 mrc p15, 0, r0, c1, c0, 0 @ read control reg
814 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
816 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
817 bl __common_mmu_cache_on
819 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
823 __armv7_mmu_cache_on:
826 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
828 movne r6, #CB_BITS | 0x02 @ !XN
831 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
833 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
835 mrc p15, 0, r0, c1, c0, 0 @ read control reg
836 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
837 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
838 orr r0, r0, #0x003c @ write buffer
839 bic r0, r0, #2 @ A (no unaligned access fault)
840 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
841 @ (needed for ARM1176)
843 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
844 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
845 orrne r0, r0, #1 @ MMU enabled
846 movne r1, #0xfffffffd @ domain 0 = client
847 bic r6, r6, #1 << 31 @ 32-bit translation system
848 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
849 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
850 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
851 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
853 mcr p15, 0, r0, c7, c5, 4 @ ISB
854 mcr p15, 0, r0, c1, c0, 0 @ load control register
855 mrc p15, 0, r0, c1, c0, 0 @ and read it back
857 mcr p15, 0, r0, c7, c5, 4 @ ISB
862 mov r6, #CB_BITS | 0x12 @ U
865 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
866 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
867 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
868 mrc p15, 0, r0, c1, c0, 0 @ read control reg
869 orr r0, r0, #0x1000 @ I-cache enable
870 bl __common_mmu_cache_on
872 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
875 __common_mmu_cache_on:
876 #ifndef CONFIG_THUMB2_KERNEL
878 orr r0, r0, #0x000d @ Write buffer, mmu
881 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
882 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
884 .align 5 @ cache line aligned
885 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
886 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
887 sub pc, lr, r0, lsr #32 @ properly flush pipeline
890 #define PROC_ENTRY_SIZE (4*5)
893 * Here follow the relocatable cache support functions for the
894 * various processors. This is a generic hook for locating an
895 * entry and jumping to an instruction at the specified offset
896 * from the start of the block. Please note this is all position
906 call_cache_fn: adr r12, proc_types
907 #ifdef CONFIG_CPU_CP15
908 mrc p15, 0, r9, c0, c0 @ get processor ID
909 #elif defined(CONFIG_CPU_V7M)
911 * On v7-M the processor id is located in the V7M_SCB_CPUID
912 * register, but as cache handling is IMPLEMENTATION DEFINED on
913 * v7-M (if existant at all) we just return early here.
914 * If V7M_SCB_CPUID were used the cpu ID functions (i.e.
915 * __armv7_mmu_cache_{on,off,flush}) would be selected which
916 * use cp15 registers that are not implemented on v7-M.
920 ldr r9, =CONFIG_PROCESSOR_ID
922 1: ldr r1, [r12, #0] @ get value
923 ldr r2, [r12, #4] @ get mask
924 eor r1, r1, r9 @ (real ^ match)
926 ARM( addeq pc, r12, r3 ) @ call cache function
927 THUMB( addeq r12, r3 )
928 THUMB( moveq pc, r12 ) @ call cache function
929 add r12, r12, #PROC_ENTRY_SIZE
933 * Table for cache operations. This is basically:
936 * - 'cache on' method instruction
937 * - 'cache off' method instruction
938 * - 'cache flush' method instruction
940 * We match an entry using: ((real_id ^ match) & mask) == 0
942 * Writethrough caches generally only need 'on' and 'off'
943 * methods. Writeback caches _must_ have the flush method
947 .type proc_types,#object
949 .word 0x41000000 @ old ARM ID
958 .word 0x41007000 @ ARM7/710
967 .word 0x41807200 @ ARM720T (writethrough)
969 W(b) __armv4_mmu_cache_on
970 W(b) __armv4_mmu_cache_off
974 .word 0x41007400 @ ARM74x
976 W(b) __armv3_mpu_cache_on
977 W(b) __armv3_mpu_cache_off
978 W(b) __armv3_mpu_cache_flush
980 .word 0x41009400 @ ARM94x
982 W(b) __armv4_mpu_cache_on
983 W(b) __armv4_mpu_cache_off
984 W(b) __armv4_mpu_cache_flush
986 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
988 W(b) __arm926ejs_mmu_cache_on
989 W(b) __armv4_mmu_cache_off
990 W(b) __armv5tej_mmu_cache_flush
992 .word 0x00007000 @ ARM7 IDs
1001 @ Everything from here on will be the new ID system.
1003 .word 0x4401a100 @ sa110 / sa1100
1005 W(b) __armv4_mmu_cache_on
1006 W(b) __armv4_mmu_cache_off
1007 W(b) __armv4_mmu_cache_flush
1009 .word 0x6901b110 @ sa1110
1011 W(b) __armv4_mmu_cache_on
1012 W(b) __armv4_mmu_cache_off
1013 W(b) __armv4_mmu_cache_flush
1016 .word 0xffffff00 @ PXA9xx
1017 W(b) __armv4_mmu_cache_on
1018 W(b) __armv4_mmu_cache_off
1019 W(b) __armv4_mmu_cache_flush
1021 .word 0x56158000 @ PXA168
1023 W(b) __armv4_mmu_cache_on
1024 W(b) __armv4_mmu_cache_off
1025 W(b) __armv5tej_mmu_cache_flush
1027 .word 0x56050000 @ Feroceon
1029 W(b) __armv4_mmu_cache_on
1030 W(b) __armv4_mmu_cache_off
1031 W(b) __armv5tej_mmu_cache_flush
1033 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
1034 /* this conflicts with the standard ARMv5TE entry */
1035 .long 0x41009260 @ Old Feroceon
1037 b __armv4_mmu_cache_on
1038 b __armv4_mmu_cache_off
1039 b __armv5tej_mmu_cache_flush
1042 .word 0x66015261 @ FA526
1044 W(b) __fa526_cache_on
1045 W(b) __armv4_mmu_cache_off
1046 W(b) __fa526_cache_flush
1048 @ These match on the architecture ID
1050 .word 0x00020000 @ ARMv4T
1052 W(b) __armv4_mmu_cache_on
1053 W(b) __armv4_mmu_cache_off
1054 W(b) __armv4_mmu_cache_flush
1056 .word 0x00050000 @ ARMv5TE
1058 W(b) __armv4_mmu_cache_on
1059 W(b) __armv4_mmu_cache_off
1060 W(b) __armv4_mmu_cache_flush
1062 .word 0x00060000 @ ARMv5TEJ
1064 W(b) __armv4_mmu_cache_on
1065 W(b) __armv4_mmu_cache_off
1066 W(b) __armv5tej_mmu_cache_flush
1068 .word 0x0007b000 @ ARMv6
1070 W(b) __armv6_mmu_cache_on
1071 W(b) __armv4_mmu_cache_off
1072 W(b) __armv6_mmu_cache_flush
1074 .word 0x000f0000 @ new CPU Id
1076 W(b) __armv7_mmu_cache_on
1077 W(b) __armv7_mmu_cache_off
1078 W(b) __armv7_mmu_cache_flush
1080 .word 0 @ unrecognised type
1089 .size proc_types, . - proc_types
1092 * If you get a "non-constant expression in ".if" statement"
1093 * error from the assembler on this line, check that you have
1094 * not accidentally written a "b" instruction where you should
1095 * have written W(b).
1097 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1098 .error "The size of one or more proc_types entries is wrong."
1102 * Turn off the Cache and MMU. ARMv3 does not support
1103 * reading the control register, but ARMv4 does.
1106 * r0, r1, r2, r3, r9, r12 corrupted
1107 * This routine must preserve:
1111 cache_off: mov r3, #12 @ cache_off function
1114 __armv4_mpu_cache_off:
1115 mrc p15, 0, r0, c1, c0
1117 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1119 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1120 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1121 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1124 __armv3_mpu_cache_off:
1125 mrc p15, 0, r0, c1, c0
1127 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1129 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1132 __armv4_mmu_cache_off:
1134 mrc p15, 0, r0, c1, c0
1136 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1138 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1139 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1143 __armv7_mmu_cache_off:
1144 mrc p15, 0, r0, c1, c0
1150 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1152 bl __armv7_mmu_cache_flush
1155 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1158 mcr p15, 0, r0, c7, c10, 4 @ DSB
1159 mcr p15, 0, r0, c7, c5, 4 @ ISB
1163 * Clean and flush the cache to maintain consistency.
1166 * r1, r2, r3, r9, r10, r11, r12 corrupted
1167 * This routine must preserve:
1175 __armv4_mpu_cache_flush:
1180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1181 mov r1, #7 << 5 @ 8 segments
1182 1: orr r3, r1, #63 << 26 @ 64 entries
1183 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1184 subs r3, r3, #1 << 26
1185 bcs 2b @ entries 63 to 0
1186 subs r1, r1, #1 << 5
1187 bcs 1b @ segments 7 to 0
1190 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1191 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1194 __fa526_cache_flush:
1198 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1199 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1200 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1203 __armv6_mmu_cache_flush:
1206 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1207 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1208 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1209 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1212 __armv7_mmu_cache_flush:
1215 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1216 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1219 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1222 mcr p15, 0, r10, c7, c10, 5 @ DMB
1223 stmfd sp!, {r0-r7, r9-r11}
1224 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1225 ands r3, r0, #0x7000000 @ extract loc from clidr
1226 mov r3, r3, lsr #23 @ left align loc bit field
1227 beq finished @ if loc is 0, then no need to clean
1228 mov r10, #0 @ start clean at cache level 0
1230 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1231 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1232 and r1, r1, #7 @ mask of the bits for current cache only
1233 cmp r1, #2 @ see what cache we have at this level
1234 blt skip @ skip if no cache, or just i-cache
1235 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1236 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1237 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1238 and r2, r1, #7 @ extract the length of the cache lines
1239 add r2, r2, #4 @ add 4 (line length offset)
1241 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1242 clz r5, r4 @ find bit position of way size increment
1244 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1246 mov r9, r4 @ create working copy of max way size
1248 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1249 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1250 THUMB( lsl r6, r9, r5 )
1251 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1252 THUMB( lsl r6, r7, r2 )
1253 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1254 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1255 subs r9, r9, #1 @ decrement the way
1257 subs r7, r7, #1 @ decrement the index
1260 add r10, r10, #2 @ increment cache number
1264 ldmfd sp!, {r0-r7, r9-r11}
1265 mov r10, #0 @ switch back to cache level 0
1266 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1268 mcr p15, 0, r10, c7, c10, 4 @ DSB
1269 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1270 mcr p15, 0, r10, c7, c10, 4 @ DSB
1271 mcr p15, 0, r10, c7, c5, 4 @ ISB
1274 __armv5tej_mmu_cache_flush:
1277 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1279 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1283 __armv4_mmu_cache_flush:
1286 mov r2, #64*1024 @ default: 32K dcache size (*2)
1287 mov r11, #32 @ default: 32 byte line size
1288 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1289 teq r3, r9 @ cache ID register present?
1294 mov r2, r2, lsl r1 @ base dcache size *2
1295 tst r3, #1 << 14 @ test M bit
1296 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1300 mov r11, r11, lsl r3 @ cache line size in bytes
1303 bic r1, r1, #63 @ align to longest cache line
1306 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1307 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1308 THUMB( add r1, r1, r11 )
1312 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1313 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1314 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1317 __armv3_mmu_cache_flush:
1318 __armv3_mpu_cache_flush:
1322 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1326 * Various debugging routines for printing hex characters and
1327 * memory, which again must be relocatable.
1331 .type phexbuf,#object
1333 .size phexbuf, . - phexbuf
1335 @ phex corrupts {r0, r1, r2, r3}
1336 phex: adr r3, phexbuf
1350 @ puts corrupts {r0, r1, r2, r3}
1351 puts: loadsp r3, r2, r1
1352 1: ldrb r2, [r0], #1
1365 @ putc corrupts {r0, r1, r2, r3}
1372 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1373 memdump: mov r12, r0
1376 2: mov r0, r11, lsl #2
1384 ldr r0, [r12, r11, lsl #2]
1404 #ifdef CONFIG_ARM_VIRT_EXT
1406 __hyp_reentry_vectors:
1412 W(b) __enter_kernel @ hyp
1415 #endif /* CONFIG_ARM_VIRT_EXT */
1418 mov r0, #0 @ must be 0
1419 mov r1, r7 @ restore architecture number
1420 mov r2, r8 @ restore atags pointer
1421 ARM( mov pc, r4 ) @ call kernel
1422 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1423 THUMB( bx r4 ) @ entry point is always ARM for A/R classes
1427 #ifdef CONFIG_EFI_STUB
1429 _start: .long start - .
1431 ENTRY(efi_stub_entry)
1432 @ allocate space on stack for passing current zImage address
1433 @ and for the EFI stub to return of new entry point of
1434 @ zImage, as EFI stub may copy the kernel. Pointer address
1435 @ is passed in r2. r0 and r1 are passed through from the
1436 @ EFI firmware to efi_entry
1441 mov r2, sp @ pass zImage address in r2
1444 @ Check for error return from EFI stub. r0 has FDT address
1449 @ Preserve return value of efi_entry() in r4
1452 @ our cache maintenance code relies on CP15 barrier instructions
1453 @ but since we arrived here with the MMU and caches configured
1454 @ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
1455 @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
1456 @ the enable path will be executed on v7+ only.
1457 mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
1458 tst r1, #(1 << 5) @ CP15BEN bit set?
1460 orr r1, r1, #(1 << 5) @ CP15 barrier instructions
1461 mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
1462 ARM( .inst 0xf57ff06f @ v7+ isb )
1465 0: bl cache_clean_flush
1468 @ Set parameters for booting zImage according to boot protocol
1469 @ put FDT address in r2, it was returned by efi_entry()
1470 @ r1 is the machine type, and r0 needs to be 0
1475 @ Branch to (possibly) relocated zImage that is in [sp]
1477 ldr ip, =start_offset
1479 mov pc, lr @ no mode switch
1482 @ Return EFI_LOAD_ERROR to EFI firmware on error.
1485 ENDPROC(efi_stub_entry)
1489 .section ".stack", "aw", %nobits
1490 .L_user_stack: .space 4096