1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_DEBUG_VIRTUAL if MMU
11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_FORTIFY_SOURCE
14 select ARCH_HAS_KEEPINITRD
16 select ARCH_HAS_MEMBARRIER_SYNC_CORE
17 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
18 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
24 select ARCH_HAS_SYNC_DMA_FOR_CPU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_MIGHT_HAVE_PC_PARPORT
32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
34 select ARCH_SUPPORTS_ATOMIC_RMW
35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
36 select ARCH_USE_BUILTIN_BSWAP
37 select ARCH_USE_CMPXCHG_LOCKREF
38 select ARCH_USE_MEMTEST
39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
40 select ARCH_WANT_GENERAL_HUGETLB
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select ARCH_WANT_LD_ORPHAN_WARN
43 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
44 select BUILDTIME_TABLE_SORT if MMU
45 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
46 select CLONE_BACKWARDS
47 select CPU_PM if SUSPEND || CPU_IDLE
48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
49 select DMA_DECLARE_COHERENT
50 select DMA_GLOBAL_POOL if !MMU
52 select DMA_NONCOHERENT_MMAP if MMU
54 select EDAC_ATOMIC_SCRUB
55 select GENERIC_ALLOCATOR
56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
59 select GENERIC_IRQ_IPI if SMP
60 select GENERIC_CPU_AUTOPROBE
61 select GENERIC_EARLY_IOREMAP
62 select GENERIC_IDLE_POLL_SETUP
63 select GENERIC_IRQ_MULTI_HANDLER
64 select GENERIC_IRQ_PROBE
65 select GENERIC_IRQ_SHOW
66 select GENERIC_IRQ_SHOW_LEVEL
67 select GENERIC_LIB_DEVMEM_IS_ALLOWED
68 select GENERIC_PCI_IOMAP
69 select GENERIC_SCHED_CLOCK
70 select GENERIC_SMP_IDLE_THREAD
71 select HARDIRQS_SW_RESEND
72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
78 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
79 select HAVE_ARCH_MMAP_RND_BITS if MMU
80 select HAVE_ARCH_PFN_VALID
81 select HAVE_ARCH_SECCOMP
82 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
83 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
84 select HAVE_ARCH_TRACEHOOK
85 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
86 select HAVE_ARM_SMCCC if CPU_V7
87 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
88 select HAVE_CONTEXT_TRACKING_USER
89 select HAVE_C_RECORDMCOUNT
90 select HAVE_BUILDTIME_MCOUNT_SORT
91 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
92 select HAVE_DMA_CONTIGUOUS if MMU
93 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
94 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
95 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
96 select HAVE_EXIT_THREAD
97 select HAVE_FAST_GUP if ARM_LPAE
98 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
99 select HAVE_FUNCTION_GRAPH_TRACER
100 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
101 select HAVE_GCC_PLUGINS
102 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
103 select HAVE_IRQ_TIME_ACCOUNTING
104 select HAVE_KERNEL_GZIP
105 select HAVE_KERNEL_LZ4
106 select HAVE_KERNEL_LZMA
107 select HAVE_KERNEL_LZO
108 select HAVE_KERNEL_XZ
109 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
110 select HAVE_KRETPROBES if HAVE_KPROBES
111 select HAVE_MOD_ARCH_SPECIFIC
113 select HAVE_OPTPROBES if !THUMB2_KERNEL
114 select HAVE_PCI if MMU
115 select HAVE_PERF_EVENTS
116 select HAVE_PERF_REGS
117 select HAVE_PERF_USER_STACK_DUMP
118 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
119 select HAVE_REGS_AND_STACK_ACCESS_API
121 select HAVE_STACKPROTECTOR
122 select HAVE_SYSCALL_TRACEPOINTS
124 select HAVE_VIRT_CPU_ACCOUNTING_GEN
125 select IRQ_FORCED_THREADING
126 select LOCK_MM_AND_FIND_VMA
127 select MODULES_USE_ELF_REL
128 select NEED_DMA_MAP_STATE
129 select OF_EARLY_FLATTREE if OF
131 select OLD_SIGSUSPEND3
132 select PCI_DOMAINS_GENERIC if PCI
133 select PCI_SYSCALL if PCI
134 select PERF_USE_VMALLOC
136 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
137 select SYS_SUPPORTS_APM_EMULATION
138 select THREAD_INFO_IN_TASK
139 select TIMER_OF if OF
140 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
141 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
142 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
143 # Above selects are sorted alphabetically; please add new ones
144 # according to that. Thanks.
146 The ARM series is a line of low-power-consumption RISC chip designs
147 licensed by ARM Ltd and targeted at embedded applications and
148 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
149 manufactured, but legacy ARM-based PC hardware remains popular in
150 Europe. There is an ARM Linux project with a web page at
151 <http://www.arm.linux.org.uk/>.
153 config ARM_HAS_GROUP_RELOCS
155 depends on !LD_IS_LLD || LLD_VERSION >= 140000
156 depends on !COMPILE_TEST
158 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
159 relocations, which have been around for a long time, but were not
160 supported in LLD until version 14. The combined range is -/+ 256 MiB,
161 which is usually sufficient, but not for allyesconfig, so we disable
162 this feature when doing compile testing.
164 config ARM_DMA_USE_IOMMU
166 select NEED_SG_DMA_LENGTH
170 config ARM_DMA_IOMMU_ALIGNMENT
171 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
175 DMA mapping framework by default aligns all buffers to the smallest
176 PAGE_SIZE order which is greater than or equal to the requested buffer
177 size. This works well for buffers up to a few hundreds kilobytes, but
178 for larger buffers it just a waste of address space. Drivers which has
179 relatively small addressing window (like 64Mib) might run out of
180 virtual space with just a few allocations.
182 With this parameter you can specify the maximum PAGE_SIZE order for
183 DMA IOMMU buffers. Larger buffers will be aligned only to this
184 specified order. The order is expressed as a power of two multiplied
189 config SYS_SUPPORTS_APM_EMULATION
194 select GENERIC_ALLOCATOR
205 config STACKTRACE_SUPPORT
209 config LOCKDEP_SUPPORT
213 config ARCH_HAS_ILOG2_U32
216 config ARCH_HAS_ILOG2_U64
219 config ARCH_HAS_BANDGAP
222 config FIX_EARLYCON_MEM
225 config GENERIC_HWEIGHT
229 config GENERIC_CALIBRATE_DELAY
233 config ARCH_MAY_HAVE_PC_FDC
236 config ARCH_SUPPORTS_UPROBES
239 config GENERIC_ISA_DMA
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 2 MiB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_FOOTBRIDGE
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x30000000 if ARCH_S3C24XX
285 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
286 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
289 Please provide the physical address corresponding to the
290 location of main memory in your system.
296 config PGTABLE_LEVELS
298 default 3 if ARM_LPAE
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
310 config ARM_SINGLE_ARMV7M
316 config ARCH_MMAP_RND_BITS_MIN
319 config ARCH_MMAP_RND_BITS_MAX
320 default 14 if PAGE_OFFSET=0x40000000
321 default 15 if PAGE_OFFSET=0x80000000
324 config ARCH_MULTIPLATFORM
325 bool "Require kernel to be portable to multiple machines" if EXPERT
326 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
329 In general, all Arm machines can be supported in a single
330 kernel image, covering either Armv4/v5 or Armv6/v7.
332 However, some configuration options require hardcoding machine
333 specific physical addresses or enable errata workarounds that may
334 break other machines.
336 Selecting N here allows using those options, including
337 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
339 menu "Platform selection"
342 comment "CPU Core family selection"
345 bool "ARMv4 based platforms (FA526, StrongARM)"
346 depends on !ARCH_MULTI_V6_V7
347 select ARCH_MULTI_V4_V5
348 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
350 config ARCH_MULTI_V4T
351 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
352 depends on !ARCH_MULTI_V6_V7
353 select ARCH_MULTI_V4_V5
354 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
355 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
356 CPU_ARM925T || CPU_ARM940T)
359 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
360 depends on !ARCH_MULTI_V6_V7
361 select ARCH_MULTI_V4_V5
362 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
363 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
364 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
366 config ARCH_MULTI_V4_V5
370 bool "ARMv6 based platforms (ARM11)"
371 select ARCH_MULTI_V6_V7
375 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
377 select ARCH_MULTI_V6_V7
381 config ARCH_MULTI_V6_V7
383 select MIGHT_HAVE_CACHE_L2X0
385 config ARCH_MULTI_CPU_AUTO
386 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
392 bool "Dummy Virtual Machine"
393 depends on ARCH_MULTI_V7
396 select ARM_GIC_V2M if PCI
398 select ARM_GIC_V3_ITS if PCI
400 select HAVE_ARM_ARCH_TIMER
403 bool "Airoha SoC Support"
404 depends on ARCH_MULTI_V7
409 select HAVE_ARM_ARCH_TIMER
411 Support for Airoha EN7523 SoCs
414 # This is sorted alphabetically by mach-* pathname. However, plat-*
415 # Kconfigs may be included either alphabetically (according to the
416 # plat- suffix) or along side the corresponding mach-* source.
418 source "arch/arm/mach-actions/Kconfig"
420 source "arch/arm/mach-alpine/Kconfig"
422 source "arch/arm/mach-artpec/Kconfig"
424 source "arch/arm/mach-asm9260/Kconfig"
426 source "arch/arm/mach-aspeed/Kconfig"
428 source "arch/arm/mach-at91/Kconfig"
430 source "arch/arm/mach-axxia/Kconfig"
432 source "arch/arm/mach-bcm/Kconfig"
434 source "arch/arm/mach-berlin/Kconfig"
436 source "arch/arm/mach-clps711x/Kconfig"
438 source "arch/arm/mach-cns3xxx/Kconfig"
440 source "arch/arm/mach-davinci/Kconfig"
442 source "arch/arm/mach-digicolor/Kconfig"
444 source "arch/arm/mach-dove/Kconfig"
446 source "arch/arm/mach-ep93xx/Kconfig"
448 source "arch/arm/mach-exynos/Kconfig"
450 source "arch/arm/mach-footbridge/Kconfig"
452 source "arch/arm/mach-gemini/Kconfig"
454 source "arch/arm/mach-highbank/Kconfig"
456 source "arch/arm/mach-hisi/Kconfig"
458 source "arch/arm/mach-hpe/Kconfig"
460 source "arch/arm/mach-imx/Kconfig"
462 source "arch/arm/mach-iop32x/Kconfig"
464 source "arch/arm/mach-ixp4xx/Kconfig"
466 source "arch/arm/mach-keystone/Kconfig"
468 source "arch/arm/mach-lpc32xx/Kconfig"
470 source "arch/arm/mach-mediatek/Kconfig"
472 source "arch/arm/mach-meson/Kconfig"
474 source "arch/arm/mach-milbeaut/Kconfig"
476 source "arch/arm/mach-mmp/Kconfig"
478 source "arch/arm/mach-moxart/Kconfig"
480 source "arch/arm/mach-mstar/Kconfig"
482 source "arch/arm/mach-mv78xx0/Kconfig"
484 source "arch/arm/mach-mvebu/Kconfig"
486 source "arch/arm/mach-mxs/Kconfig"
488 source "arch/arm/mach-nomadik/Kconfig"
490 source "arch/arm/mach-npcm/Kconfig"
492 source "arch/arm/mach-nspire/Kconfig"
494 source "arch/arm/mach-omap1/Kconfig"
496 source "arch/arm/mach-omap2/Kconfig"
498 source "arch/arm/mach-orion5x/Kconfig"
500 source "arch/arm/mach-oxnas/Kconfig"
502 source "arch/arm/mach-pxa/Kconfig"
504 source "arch/arm/mach-qcom/Kconfig"
506 source "arch/arm/mach-rda/Kconfig"
508 source "arch/arm/mach-realtek/Kconfig"
510 source "arch/arm/mach-rpc/Kconfig"
512 source "arch/arm/mach-rockchip/Kconfig"
514 source "arch/arm/mach-s3c/Kconfig"
516 source "arch/arm/mach-s5pv210/Kconfig"
518 source "arch/arm/mach-sa1100/Kconfig"
520 source "arch/arm/mach-shmobile/Kconfig"
522 source "arch/arm/mach-socfpga/Kconfig"
524 source "arch/arm/mach-spear/Kconfig"
526 source "arch/arm/mach-sti/Kconfig"
528 source "arch/arm/mach-stm32/Kconfig"
530 source "arch/arm/mach-sunplus/Kconfig"
532 source "arch/arm/mach-sunxi/Kconfig"
534 source "arch/arm/mach-tegra/Kconfig"
536 source "arch/arm/mach-uniphier/Kconfig"
538 source "arch/arm/mach-ux500/Kconfig"
540 source "arch/arm/mach-versatile/Kconfig"
542 source "arch/arm/mach-vt8500/Kconfig"
544 source "arch/arm/mach-zynq/Kconfig"
546 # ARMv7-M architecture
548 bool "NXP LPC18xx/LPC43xx"
549 depends on ARM_SINGLE_ARMV7M
550 select ARCH_HAS_RESET_CONTROLLER
552 select CLKSRC_LPC32XX
555 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
556 high performance microcontrollers.
559 bool "ARM MPS2 platform"
560 depends on ARM_SINGLE_ARMV7M
564 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
565 with a range of available cores like Cortex-M3/M4/M7.
567 Please, note that depends which Application Note is used memory map
568 for the platform may vary, so adjustment of RAM base might be needed.
570 # Definitions to make life easier
577 select GENERIC_IRQ_CHIP
580 config PLAT_ORION_LEGACY
584 config PLAT_VERSATILE
587 source "arch/arm/mm/Kconfig"
590 bool "Enable iWMMXt support"
591 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
592 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
594 Enable support for iWMMXt context switching at run time if
595 running on a CPU that supports it.
598 source "arch/arm/Kconfig-nommu"
601 config PJ4B_ERRATA_4742
602 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
603 depends on CPU_PJ4B && MACH_ARMADA_370
606 When coming out of either a Wait for Interrupt (WFI) or a Wait for
607 Event (WFE) IDLE states, a specific timing sensitivity exists between
608 the retiring WFI/WFE instructions and the newly issued subsequent
609 instructions. This sensitivity can result in a CPU hang scenario.
611 The software must insert either a Data Synchronization Barrier (DSB)
612 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
615 config ARM_ERRATA_326103
616 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
619 Executing a SWP instruction to read-only memory does not set bit 11
620 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
621 treat the access as a read, preventing a COW from occurring and
622 causing the faulting task to livelock.
624 config ARM_ERRATA_411920
625 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
626 depends on CPU_V6 || CPU_V6K
628 Invalidation of the Instruction Cache operation can
629 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
630 It does not affect the MPCore. This option enables the ARM Ltd.
631 recommended workaround.
633 config ARM_ERRATA_430973
634 bool "ARM errata: Stale prediction on replaced interworking branch"
637 This option enables the workaround for the 430973 Cortex-A8
638 r1p* erratum. If a code sequence containing an ARM/Thumb
639 interworking branch is replaced with another code sequence at the
640 same virtual address, whether due to self-modifying code or virtual
641 to physical address re-mapping, Cortex-A8 does not recover from the
642 stale interworking branch prediction. This results in Cortex-A8
643 executing the new code sequence in the incorrect ARM or Thumb state.
644 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
645 and also flushes the branch target cache at every context switch.
646 Note that setting specific bits in the ACTLR register may not be
647 available in non-secure mode.
649 config ARM_ERRATA_458693
650 bool "ARM errata: Processor deadlock when a false hazard is created"
652 depends on !ARCH_MULTIPLATFORM
654 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
655 erratum. For very specific sequences of memory operations, it is
656 possible for a hazard condition intended for a cache line to instead
657 be incorrectly associated with a different cache line. This false
658 hazard might then cause a processor deadlock. The workaround enables
659 the L1 caching of the NEON accesses and disables the PLD instruction
660 in the ACTLR register. Note that setting specific bits in the ACTLR
661 register may not be available in non-secure mode.
663 config ARM_ERRATA_460075
664 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
666 depends on !ARCH_MULTIPLATFORM
668 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
669 erratum. Any asynchronous access to the L2 cache may encounter a
670 situation in which recent store transactions to the L2 cache are lost
671 and overwritten with stale memory contents from external memory. The
672 workaround disables the write-allocate mode for the L2 cache via the
673 ACTLR register. Note that setting specific bits in the ACTLR register
674 may not be available in non-secure mode.
676 config ARM_ERRATA_742230
677 bool "ARM errata: DMB operation may be faulty"
678 depends on CPU_V7 && SMP
679 depends on !ARCH_MULTIPLATFORM
681 This option enables the workaround for the 742230 Cortex-A9
682 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
683 between two write operations may not ensure the correct visibility
684 ordering of the two writes. This workaround sets a specific bit in
685 the diagnostic register of the Cortex-A9 which causes the DMB
686 instruction to behave as a DSB, ensuring the correct behaviour of
689 config ARM_ERRATA_742231
690 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
691 depends on CPU_V7 && SMP
692 depends on !ARCH_MULTIPLATFORM
694 This option enables the workaround for the 742231 Cortex-A9
695 (r2p0..r2p2) erratum. Under certain conditions, specific to the
696 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
697 accessing some data located in the same cache line, may get corrupted
698 data due to bad handling of the address hazard when the line gets
699 replaced from one of the CPUs at the same time as another CPU is
700 accessing it. This workaround sets specific bits in the diagnostic
701 register of the Cortex-A9 which reduces the linefill issuing
702 capabilities of the processor.
704 config ARM_ERRATA_643719
705 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
706 depends on CPU_V7 && SMP
709 This option enables the workaround for the 643719 Cortex-A9 (prior to
710 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
711 register returns zero when it should return one. The workaround
712 corrects this value, ensuring cache maintenance operations which use
713 it behave as intended and avoiding data corruption.
715 config ARM_ERRATA_720789
716 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
719 This option enables the workaround for the 720789 Cortex-A9 (prior to
720 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
721 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
722 As a consequence of this erratum, some TLB entries which should be
723 invalidated are not, resulting in an incoherency in the system page
724 tables. The workaround changes the TLB flushing routines to invalidate
725 entries regardless of the ASID.
727 config ARM_ERRATA_743622
728 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
730 depends on !ARCH_MULTIPLATFORM
732 This option enables the workaround for the 743622 Cortex-A9
733 (r2p*) erratum. Under very rare conditions, a faulty
734 optimisation in the Cortex-A9 Store Buffer may lead to data
735 corruption. This workaround sets a specific bit in the diagnostic
736 register of the Cortex-A9 which disables the Store Buffer
737 optimisation, preventing the defect from occurring. This has no
738 visible impact on the overall performance or power consumption of the
741 config ARM_ERRATA_751472
742 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
744 depends on !ARCH_MULTIPLATFORM
746 This option enables the workaround for the 751472 Cortex-A9 (prior
747 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
748 completion of a following broadcasted operation if the second
749 operation is received by a CPU before the ICIALLUIS has completed,
750 potentially leading to corrupted entries in the cache or TLB.
752 config ARM_ERRATA_754322
753 bool "ARM errata: possible faulty MMU translations following an ASID switch"
756 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
757 r3p*) erratum. A speculative memory access may cause a page table walk
758 which starts prior to an ASID switch but completes afterwards. This
759 can populate the micro-TLB with a stale entry which may be hit with
760 the new ASID. This workaround places two dsb instructions in the mm
761 switching code so that no page table walks can cross the ASID switch.
763 config ARM_ERRATA_754327
764 bool "ARM errata: no automatic Store Buffer drain"
765 depends on CPU_V7 && SMP
767 This option enables the workaround for the 754327 Cortex-A9 (prior to
768 r2p0) erratum. The Store Buffer does not have any automatic draining
769 mechanism and therefore a livelock may occur if an external agent
770 continuously polls a memory location waiting to observe an update.
771 This workaround defines cpu_relax() as smp_mb(), preventing correctly
772 written polling loops from denying visibility of updates to memory.
774 config ARM_ERRATA_364296
775 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
778 This options enables the workaround for the 364296 ARM1136
779 r0p2 erratum (possible cache data corruption with
780 hit-under-miss enabled). It sets the undocumented bit 31 in
781 the auxiliary control register and the FI bit in the control
782 register, thus disabling hit-under-miss without putting the
783 processor into full low interrupt latency mode. ARM11MPCore
786 config ARM_ERRATA_764369
787 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
788 depends on CPU_V7 && SMP
790 This option enables the workaround for erratum 764369
791 affecting Cortex-A9 MPCore with two or more processors (all
792 current revisions). Under certain timing circumstances, a data
793 cache line maintenance operation by MVA targeting an Inner
794 Shareable memory region may fail to proceed up to either the
795 Point of Coherency or to the Point of Unification of the
796 system. This workaround adds a DSB instruction before the
797 relevant cache maintenance functions and sets a specific bit
798 in the diagnostic control register of the SCU.
800 config ARM_ERRATA_764319
801 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
804 This option enables the workaround for the 764319 Cortex A-9 erratum.
805 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
806 unexpected Undefined Instruction exception when the DBGSWENABLE
807 external pin is set to 0, even when the CP14 accesses are performed
808 from a privileged mode. This work around catches the exception in a
809 way the kernel does not stop execution.
811 config ARM_ERRATA_775420
812 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
815 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
816 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
817 operation aborts with MMU exception, it might cause the processor
818 to deadlock. This workaround puts DSB before executing ISB if
819 an abort may occur on cache maintenance.
821 config ARM_ERRATA_798181
822 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
823 depends on CPU_V7 && SMP
825 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
826 adequately shooting down all use of the old entries. This
827 option enables the Linux kernel workaround for this erratum
828 which sends an IPI to the CPUs that are running the same ASID
829 as the one being invalidated.
831 config ARM_ERRATA_773022
832 bool "ARM errata: incorrect instructions may be executed from loop buffer"
835 This option enables the workaround for the 773022 Cortex-A15
836 (up to r0p4) erratum. In certain rare sequences of code, the
837 loop buffer may deliver incorrect instructions. This
838 workaround disables the loop buffer to avoid the erratum.
840 config ARM_ERRATA_818325_852422
841 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
844 This option enables the workaround for:
845 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
846 instruction might deadlock. Fixed in r0p1.
847 - Cortex-A12 852422: Execution of a sequence of instructions might
848 lead to either a data corruption or a CPU deadlock. Not fixed in
849 any Cortex-A12 cores yet.
850 This workaround for all both errata involves setting bit[12] of the
851 Feature Register. This bit disables an optimisation applied to a
852 sequence of 2 instructions that use opposing condition codes.
854 config ARM_ERRATA_821420
855 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
858 This option enables the workaround for the 821420 Cortex-A12
859 (all revs) erratum. In very rare timing conditions, a sequence
860 of VMOV to Core registers instructions, for which the second
861 one is in the shadow of a branch or abort, can lead to a
862 deadlock when the VMOV instructions are issued out-of-order.
864 config ARM_ERRATA_825619
865 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
868 This option enables the workaround for the 825619 Cortex-A12
869 (all revs) erratum. Within rare timing constraints, executing a
870 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
871 and Device/Strongly-Ordered loads and stores might cause deadlock
873 config ARM_ERRATA_857271
874 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
877 This option enables the workaround for the 857271 Cortex-A12
878 (all revs) erratum. Under very rare timing conditions, the CPU might
879 hang. The workaround is expected to have a < 1% performance impact.
881 config ARM_ERRATA_852421
882 bool "ARM errata: A17: DMB ST might fail to create order between stores"
885 This option enables the workaround for the 852421 Cortex-A17
886 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
887 execution of a DMB ST instruction might fail to properly order
888 stores from GroupA and stores from GroupB.
890 config ARM_ERRATA_852423
891 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
894 This option enables the workaround for:
895 - Cortex-A17 852423: Execution of a sequence of instructions might
896 lead to either a data corruption or a CPU deadlock. Not fixed in
897 any Cortex-A17 cores yet.
898 This is identical to Cortex-A12 erratum 852422. It is a separate
899 config option from the A12 erratum due to the way errata are checked
902 config ARM_ERRATA_857272
903 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
906 This option enables the workaround for the 857272 Cortex-A17 erratum.
907 This erratum is not known to be fixed in any A17 revision.
908 This is identical to Cortex-A12 erratum 857271. It is a separate
909 config option from the A12 erratum due to the way errata are checked
914 source "arch/arm/common/Kconfig"
921 Find out whether you have ISA slots on your motherboard. ISA is the
922 name of a bus system, i.e. the way the CPU talks to the other stuff
923 inside your box. Other bus systems are PCI, EISA, MicroChannel
924 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
925 newer boards don't support it. If you have ISA, say Y, otherwise N.
927 # Select ISA DMA interface
931 config PCI_NANOENGINE
932 bool "BSE nanoEngine PCI support"
933 depends on SA1100_NANOENGINE
935 Enable PCI on the BSE nanoEngine board.
937 config ARM_ERRATA_814220
938 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
941 The v7 ARM states that all cache and branch predictor maintenance
942 operations that do not specify an address execute, relative to
943 each other, in program order.
944 However, because of this erratum, an L2 set/way cache maintenance
945 operation can overtake an L1 set/way cache maintenance operation.
946 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
951 menu "Kernel Features"
956 This option should be selected by machines which have an SMP-
959 The only effect of this option is to make the SMP-related
960 options available to the user for configuration.
963 bool "Symmetric Multi-Processing"
964 depends on CPU_V6K || CPU_V7
966 depends on MMU || ARM_MPU
969 This enables support for systems with more than one CPU. If you have
970 a system with only one CPU, say N. If you have a system with more
973 If you say N here, the kernel will run on uni- and multiprocessor
974 machines, but will use only one CPU of a multiprocessor machine. If
975 you say Y here, the kernel will run on many, but not all,
976 uniprocessor machines. On a uniprocessor machine, the kernel
977 will run faster if you say N here.
979 See also <file:Documentation/x86/i386/IO-APIC.rst>,
980 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
981 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
983 If you don't know what to do here, say N.
986 bool "Allow booting SMP kernel on uniprocessor systems"
987 depends on SMP && MMU
990 SMP kernels contain instructions which fail on non-SMP processors.
991 Enabling this option allows the kernel to modify itself to make
992 these instructions safe. Disabling it allows about 1K of space
995 If you don't know what to do here, say Y.
998 config CURRENT_POINTER_IN_TPIDRURO
1000 depends on CPU_32v6K && !CPU_V6
1004 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1005 select HAVE_SOFTIRQ_ON_OWN_STACK
1007 config ARM_CPU_TOPOLOGY
1008 bool "Support cpu topology definition"
1009 depends on SMP && CPU_V7
1012 Support ARM cpu topology definition. The MPIDR register defines
1013 affinity between processors which is then used to describe the cpu
1014 topology of an ARM System.
1017 bool "Multi-core scheduler support"
1018 depends on ARM_CPU_TOPOLOGY
1020 Multi-core scheduler support improves the CPU scheduler's decision
1021 making when dealing with multi-core CPU chips at a cost of slightly
1022 increased overhead in some places. If unsure say N here.
1025 bool "SMT scheduler support"
1026 depends on ARM_CPU_TOPOLOGY
1028 Improves the CPU scheduler's decision making when dealing with
1029 MultiThreading at a cost of slightly increased overhead in some
1030 places. If unsure say N here.
1035 This option enables support for the ARM snoop control unit
1037 config HAVE_ARM_ARCH_TIMER
1038 bool "Architected timer support"
1040 select ARM_ARCH_TIMER
1042 This option enables support for the ARM architected timer
1047 This options enables support for the ARM timer and watchdog unit
1050 bool "Multi-Cluster Power Management"
1051 depends on CPU_V7 && SMP
1053 This option provides the common power management infrastructure
1054 for (multi-)cluster based systems, such as big.LITTLE based
1057 config MCPM_QUAD_CLUSTER
1061 To avoid wasting resources unnecessarily, MCPM only supports up
1062 to 2 clusters by default.
1063 Platforms with 3 or 4 clusters that use MCPM must select this
1064 option to allow the additional clusters to be managed.
1067 bool "big.LITTLE support (Experimental)"
1068 depends on CPU_V7 && SMP
1071 This option enables support selections for the big.LITTLE
1072 system architecture.
1075 bool "big.LITTLE switcher support"
1076 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1079 The big.LITTLE "switcher" provides the core functionality to
1080 transparently handle transition between a cluster of A15's
1081 and a cluster of A7's in a big.LITTLE system.
1083 config BL_SWITCHER_DUMMY_IF
1084 tristate "Simple big.LITTLE switcher user interface"
1085 depends on BL_SWITCHER && DEBUG_KERNEL
1087 This is a simple and dummy char dev interface to control
1088 the big.LITTLE switcher core code. It is meant for
1089 debugging purposes only.
1092 prompt "Memory split"
1096 Select the desired split between kernel and user memory.
1098 If you are not absolutely sure what you are doing, leave this
1102 bool "3G/1G user/kernel split"
1103 config VMSPLIT_3G_OPT
1104 depends on !ARM_LPAE
1105 bool "3G/1G user/kernel split (for full 1G low memory)"
1107 bool "2G/2G user/kernel split"
1109 bool "1G/3G user/kernel split"
1114 default PHYS_OFFSET if !MMU
1115 default 0x40000000 if VMSPLIT_1G
1116 default 0x80000000 if VMSPLIT_2G
1117 default 0xB0000000 if VMSPLIT_3G_OPT
1120 config KASAN_SHADOW_OFFSET
1123 default 0x1f000000 if PAGE_OFFSET=0x40000000
1124 default 0x5f000000 if PAGE_OFFSET=0x80000000
1125 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1126 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1130 int "Maximum number of CPUs (2-32)"
1131 range 2 16 if DEBUG_KMAP_LOCAL
1132 range 2 32 if !DEBUG_KMAP_LOCAL
1136 The maximum number of CPUs that the kernel can support.
1137 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1138 debugging is enabled, which uses half of the per-CPU fixmap
1139 slots as guard regions.
1142 bool "Support for hot-pluggable CPUs"
1144 select GENERIC_IRQ_MIGRATION
1146 Say Y here to experiment with turning CPUs off and on. CPUs
1147 can be controlled through /sys/devices/system/cpu.
1150 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1151 depends on HAVE_ARM_SMCCC
1154 Say Y here if you want Linux to communicate with system firmware
1155 implementing the PSCI specification for CPU-centric power
1156 management operations described in ARM document number ARM DEN
1157 0022A ("Power State Coordination Interface System Software on
1160 # The GPIO number here must be sorted by descending number. In case of
1161 # a multiplatform kernel, we just want the highest value required by the
1162 # selected platforms.
1165 default 2048 if ARCH_INTEL_SOCFPGA
1166 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1167 ARCH_ZYNQ || ARCH_ASPEED
1168 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1169 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1170 default 416 if ARCH_SUNXI
1171 default 392 if ARCH_U8500
1172 default 352 if ARCH_VT8500
1173 default 288 if ARCH_ROCKCHIP
1174 default 264 if MACH_H4700
1177 Maximum number of GPIOs in the system.
1179 If unsure, leave the default value.
1183 default 128 if SOC_AT91RM9200
1187 depends on HZ_FIXED = 0
1188 prompt "Timer frequency"
1212 default HZ_FIXED if HZ_FIXED != 0
1213 default 100 if HZ_100
1214 default 200 if HZ_200
1215 default 250 if HZ_250
1216 default 300 if HZ_300
1217 default 500 if HZ_500
1221 def_bool HIGH_RES_TIMERS
1223 config THUMB2_KERNEL
1224 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1225 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1226 default y if CPU_THUMBONLY
1229 By enabling this option, the kernel will be compiled in
1234 config ARM_PATCH_IDIV
1235 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1239 The ARM compiler inserts calls to __aeabi_idiv() and
1240 __aeabi_uidiv() when it needs to perform division on signed
1241 and unsigned integers. Some v7 CPUs have support for the sdiv
1242 and udiv instructions that can be used to implement those
1245 Enabling this option allows the kernel to modify itself to
1246 replace the first two instructions of these library functions
1247 with the sdiv or udiv plus "bx lr" instructions when the CPU
1248 it is running on supports them. Typically this will be faster
1249 and less power intensive than running the original library
1250 code to do integer division.
1253 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1254 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1255 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1257 This option allows for the kernel to be compiled using the latest
1258 ARM ABI (aka EABI). This is only useful if you are using a user
1259 space environment that is also compiled with EABI.
1261 Since there are major incompatibilities between the legacy ABI and
1262 EABI, especially with regard to structure member alignment, this
1263 option also changes the kernel syscall calling convention to
1264 disambiguate both ABIs and allow for backward compatibility support
1265 (selected with CONFIG_OABI_COMPAT).
1267 To use this you need GCC version 4.0.0 or later.
1270 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1271 depends on AEABI && !THUMB2_KERNEL
1273 This option preserves the old syscall interface along with the
1274 new (ARM EABI) one. It also provides a compatibility layer to
1275 intercept syscalls that have structure arguments which layout
1276 in memory differs between the legacy ABI and the new ARM EABI
1277 (only for non "thumb" binaries). This option adds a tiny
1278 overhead to all syscalls and produces a slightly larger kernel.
1280 The seccomp filter system will not be available when this is
1281 selected, since there is no way yet to sensibly distinguish
1282 between calling conventions during filtering.
1284 If you know you'll be using only pure EABI user space then you
1285 can say N here. If this option is not selected and you attempt
1286 to execute a legacy ABI binary then the result will be
1287 UNPREDICTABLE (in fact it can be predicted that it won't work
1288 at all). If in doubt say N.
1290 config ARCH_SELECT_MEMORY_MODEL
1293 config ARCH_FLATMEM_ENABLE
1294 def_bool !(ARCH_RPC || ARCH_SA1100)
1296 config ARCH_SPARSEMEM_ENABLE
1297 def_bool !ARCH_FOOTBRIDGE
1298 select SPARSEMEM_STATIC if SPARSEMEM
1301 bool "High Memory Support"
1304 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1306 The address space of ARM processors is only 4 Gigabytes large
1307 and it has to accommodate user address space, kernel address
1308 space as well as some memory mapped IO. That means that, if you
1309 have a large amount of physical memory and/or IO, not all of the
1310 memory can be "permanently mapped" by the kernel. The physical
1311 memory that is not permanently mapped is called "high memory".
1313 Depending on the selected kernel/user memory split, minimum
1314 vmalloc space and actual amount of RAM, you may not need this
1315 option which should result in a slightly faster kernel.
1320 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1324 The VM uses one page of physical memory for each page table.
1325 For systems with a lot of processes, this can use a lot of
1326 precious low memory, eventually leading to low memory being
1327 consumed by page tables. Setting this option will allow
1328 user-space 2nd level page tables to reside in high memory.
1330 config CPU_SW_DOMAIN_PAN
1331 bool "Enable use of CPU domains to implement privileged no-access"
1332 depends on MMU && !ARM_LPAE
1335 Increase kernel security by ensuring that normal kernel accesses
1336 are unable to access userspace addresses. This can help prevent
1337 use-after-free bugs becoming an exploitable privilege escalation
1338 by ensuring that magic values (such as LIST_POISON) will always
1339 fault when dereferenced.
1341 CPUs with low-vector mappings use a best-efforts implementation.
1342 Their lower 1MB needs to remain accessible for the vectors, but
1343 the remainder of userspace will become appropriately inaccessible.
1345 config HW_PERF_EVENTS
1349 config ARM_MODULE_PLTS
1350 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1352 select KASAN_VMALLOC if KASAN
1355 Allocate PLTs when loading modules so that jumps and calls whose
1356 targets are too far away for their relative offsets to be encoded
1357 in the instructions themselves can be bounced via veneers in the
1358 module's PLT. This allows modules to be allocated in the generic
1359 vmalloc area after the dedicated module memory area has been
1360 exhausted. The modules will use slightly more memory, but after
1361 rounding up to page size, the actual memory footprint is usually
1364 Disabling this is usually safe for small single-platform
1365 configurations. If unsure, say y.
1367 config ARCH_FORCE_MAX_ORDER
1368 int "Maximum zone order"
1369 default "12" if SOC_AM33XX
1370 default "9" if SA1111
1373 The kernel memory allocator divides physically contiguous memory
1374 blocks into "zones", where each zone is a power of two number of
1375 pages. This option selects the largest power of two that the kernel
1376 keeps in the memory allocator. If you need to allocate very large
1377 blocks of physically contiguous memory, then you may need to
1378 increase this value.
1380 This config option is actually maximum order plus one. For example,
1381 a value of 11 means that the largest free memory block is 2^10 pages.
1383 config ALIGNMENT_TRAP
1384 def_bool CPU_CP15_MMU
1385 select HAVE_PROC_CPU if PROC_FS
1387 ARM processors cannot fetch/store information which is not
1388 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1389 address divisible by 4. On 32-bit ARM processors, these non-aligned
1390 fetch/store instructions will be emulated in software if you say
1391 here, which has a severe performance impact. This is necessary for
1392 correct operation of some network protocols. With an IP-only
1393 configuration it is safe to say N, otherwise say Y.
1395 config UACCESS_WITH_MEMCPY
1396 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1398 default y if CPU_FEROCEON
1400 Implement faster copy_to_user and clear_user methods for CPU
1401 cores where a 8-word STM instruction give significantly higher
1402 memory write throughput than a sequence of individual 32bit stores.
1404 A possible side effect is a slight increase in scheduling latency
1405 between threads sharing the same address space if they invoke
1406 such copy operations with large buffers.
1408 However, if the CPU data cache is using a write-allocate mode,
1409 this option is unlikely to provide any performance gain.
1412 bool "Enable paravirtualization code"
1414 This changes the kernel so it can modify itself when it is run
1415 under a hypervisor, potentially improving performance significantly
1416 over full virtualization.
1418 config PARAVIRT_TIME_ACCOUNTING
1419 bool "Paravirtual steal time accounting"
1422 Select this option to enable fine granularity task steal time
1423 accounting. Time spent executing other tasks in parallel with
1424 the current vCPU is discounted from the vCPU power. To account for
1425 that, there can be a small performance impact.
1427 If in doubt, say N here.
1434 bool "Xen guest support on ARM"
1435 depends on ARM && AEABI && OF
1436 depends on CPU_V7 && !CPU_V6
1437 depends on !GENERIC_ATOMIC64
1439 select ARCH_DMA_ADDR_T_64BIT
1445 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1447 config CC_HAVE_STACKPROTECTOR_TLS
1448 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1450 config STACKPROTECTOR_PER_TASK
1451 bool "Use a unique stack canary value for each task"
1452 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1453 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1454 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1457 Due to the fact that GCC uses an ordinary symbol reference from
1458 which to load the value of the stack canary, this value can only
1459 change at reboot time on SMP systems, and all tasks running in the
1460 kernel's address space are forced to use the same canary value for
1461 the entire duration that the system is up.
1463 Enable this option to switch to a different method that uses a
1464 different canary value for each task.
1471 bool "Flattened Device Tree support"
1475 Include support for flattened device tree machine descriptions.
1478 bool "Support for the traditional ATAGS boot data passing"
1481 This is the traditional way of passing data to the kernel at boot
1482 time. If you are solely relying on the flattened device tree (or
1483 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1484 to remove ATAGS support from your kernel binary.
1486 config UNUSED_BOARD_FILES
1487 bool "Board support for machines without known users"
1490 Most ATAGS based board files are completely unused and are
1491 scheduled for removal in early 2023, and left out of kernels
1492 by default now. If you are using a board file that is marked
1493 as unused, turn on this option to build support into the kernel.
1495 To keep support for your individual board from being removed,
1496 send a reply to the email discussion at
1497 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
1499 config DEPRECATED_PARAM_STRUCT
1500 bool "Provide old way to pass kernel parameters"
1503 This was deprecated in 2001 and announced to live on for 5 years.
1504 Some old boot loaders still use this way.
1506 # Compressed boot loader in ROM. Yes, we really want to ask about
1507 # TEXT and BSS so we preserve their values in the config files.
1508 config ZBOOT_ROM_TEXT
1509 hex "Compressed ROM boot loader base address"
1512 The physical address at which the ROM-able zImage is to be
1513 placed in the target. Platforms which normally make use of
1514 ROM-able zImage formats normally set this to a suitable
1515 value in their defconfig file.
1517 If ZBOOT_ROM is not enabled, this has no effect.
1519 config ZBOOT_ROM_BSS
1520 hex "Compressed ROM boot loader BSS address"
1523 The base address of an area of read/write memory in the target
1524 for the ROM-able zImage which must be available while the
1525 decompressor is running. It must be large enough to hold the
1526 entire decompressed kernel plus an additional 128 KiB.
1527 Platforms which normally make use of ROM-able zImage formats
1528 normally set this to a suitable value in their defconfig file.
1530 If ZBOOT_ROM is not enabled, this has no effect.
1533 bool "Compressed boot loader in ROM/flash"
1534 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1535 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1537 Say Y here if you intend to execute your compressed kernel image
1538 (zImage) directly from ROM or flash. If unsure, say N.
1540 config ARM_APPENDED_DTB
1541 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1544 With this option, the boot code will look for a device tree binary
1545 (DTB) appended to zImage
1546 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1548 This is meant as a backward compatibility convenience for those
1549 systems with a bootloader that can't be upgraded to accommodate
1550 the documented boot protocol using a device tree.
1552 Beware that there is very little in terms of protection against
1553 this option being confused by leftover garbage in memory that might
1554 look like a DTB header after a reboot if no actual DTB is appended
1555 to zImage. Do not leave this option active in a production kernel
1556 if you don't intend to always append a DTB. Proper passing of the
1557 location into r2 of a bootloader provided DTB is always preferable
1560 config ARM_ATAG_DTB_COMPAT
1561 bool "Supplement the appended DTB with traditional ATAG information"
1562 depends on ARM_APPENDED_DTB
1564 Some old bootloaders can't be updated to a DTB capable one, yet
1565 they provide ATAGs with memory configuration, the ramdisk address,
1566 the kernel cmdline string, etc. Such information is dynamically
1567 provided by the bootloader and can't always be stored in a static
1568 DTB. To allow a device tree enabled kernel to be used with such
1569 bootloaders, this option allows zImage to extract the information
1570 from the ATAG list and store it at run time into the appended DTB.
1573 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1574 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1576 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1577 bool "Use bootloader kernel arguments if available"
1579 Uses the command-line options passed by the boot loader instead of
1580 the device tree bootargs property. If the boot loader doesn't provide
1581 any, the device tree bootargs property will be used.
1583 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1584 bool "Extend with bootloader kernel arguments"
1586 The command-line arguments provided by the boot loader will be
1587 appended to the the device tree bootargs property.
1592 string "Default kernel command string"
1595 On some architectures (e.g. CATS), there is currently no way
1596 for the boot loader to pass arguments to the kernel. For these
1597 architectures, you should supply some command-line options at build
1598 time by entering them here. As a minimum, you should specify the
1599 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1602 prompt "Kernel command line type" if CMDLINE != ""
1603 default CMDLINE_FROM_BOOTLOADER
1605 config CMDLINE_FROM_BOOTLOADER
1606 bool "Use bootloader kernel arguments if available"
1608 Uses the command-line options passed by the boot loader. If
1609 the boot loader doesn't provide any, the default kernel command
1610 string provided in CMDLINE will be used.
1612 config CMDLINE_EXTEND
1613 bool "Extend bootloader kernel arguments"
1615 The command-line arguments provided by the boot loader will be
1616 appended to the default kernel command string.
1618 config CMDLINE_FORCE
1619 bool "Always use the default kernel command string"
1621 Always use the default kernel command string, even if the boot
1622 loader passes other arguments to the kernel.
1623 This is useful if you cannot or don't want to change the
1624 command-line options your boot loader passes to the kernel.
1628 bool "Kernel Execute-In-Place from ROM"
1629 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1630 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1632 Execute-In-Place allows the kernel to run from non-volatile storage
1633 directly addressable by the CPU, such as NOR flash. This saves RAM
1634 space since the text section of the kernel is not loaded from flash
1635 to RAM. Read-write sections, such as the data section and stack,
1636 are still copied to RAM. The XIP kernel is not compressed since
1637 it has to run directly from flash, so it will take more space to
1638 store it. The flash address used to link the kernel object files,
1639 and for storing it, is configuration dependent. Therefore, if you
1640 say Y here, you must know the proper physical address where to
1641 store the kernel image depending on your own flash memory usage.
1643 Also note that the make target becomes "make xipImage" rather than
1644 "make zImage" or "make Image". The final kernel binary to put in
1645 ROM memory will be arch/arm/boot/xipImage.
1649 config XIP_PHYS_ADDR
1650 hex "XIP Kernel Physical Location"
1651 depends on XIP_KERNEL
1652 default "0x00080000"
1654 This is the physical address in your flash memory the kernel will
1655 be linked for and stored to. This address is dependent on your
1658 config XIP_DEFLATED_DATA
1659 bool "Store kernel .data section compressed in ROM"
1660 depends on XIP_KERNEL
1663 Before the kernel is actually executed, its .data section has to be
1664 copied to RAM from ROM. This option allows for storing that data
1665 in compressed form and decompressed to RAM rather than merely being
1666 copied, saving some precious ROM space. A possible drawback is a
1667 slightly longer boot delay.
1670 bool "Kexec system call (EXPERIMENTAL)"
1671 depends on (!SMP || PM_SLEEP_SMP)
1675 kexec is a system call that implements the ability to shutdown your
1676 current kernel, and to start another kernel. It is like a reboot
1677 but it is independent of the system firmware. And like a reboot
1678 you can start any kernel with it, not just Linux.
1680 It is an ongoing process to be certain the hardware in a machine
1681 is properly shutdown, so do not be surprised if this code does not
1682 initially work for you.
1685 bool "Export atags in procfs"
1686 depends on ATAGS && KEXEC
1689 Should the atags used to boot the kernel be exported in an "atags"
1690 file in procfs. Useful with kexec.
1693 bool "Build kdump crash kernel (EXPERIMENTAL)"
1695 Generate crash dump after being started by kexec. This should
1696 be normally only set in special crash dump kernels which are
1697 loaded in the main kernel with kexec-tools into a specially
1698 reserved region and then later executed after a crash by
1699 kdump/kexec. The crash dump kernel must be compiled to a
1700 memory address not used by the main kernel
1702 For more details see Documentation/admin-guide/kdump/kdump.rst
1704 config AUTO_ZRELADDR
1705 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1706 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1708 ZRELADDR is the physical address where the decompressed kernel
1709 image will be placed. If AUTO_ZRELADDR is selected, the address
1710 will be determined at run-time, either by masking the current IP
1711 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1712 This assumes the zImage being placed in the first 128MB from
1719 bool "UEFI runtime support"
1720 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1722 select EFI_PARAMS_FROM_FDT
1724 select EFI_GENERIC_STUB
1725 select EFI_RUNTIME_WRAPPERS
1727 This option provides support for runtime services provided
1728 by UEFI firmware (such as non-volatile variables, realtime
1729 clock, and platform reset). A UEFI stub is also provided to
1730 allow the kernel to be booted as an EFI application. This
1731 is only useful for kernels that may run on systems that have
1735 bool "Enable support for SMBIOS (DMI) tables"
1739 This enables SMBIOS/DMI feature for systems.
1741 This option is only useful on systems that have UEFI firmware.
1742 However, even with this option, the resultant kernel should
1743 continue to boot on existing non-UEFI platforms.
1745 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1746 i.e., the the practice of identifying the platform via DMI to
1747 decide whether certain workarounds for buggy hardware and/or
1748 firmware need to be enabled. This would require the DMI subsystem
1749 to be enabled much earlier than we do on ARM, which is non-trivial.
1753 menu "CPU Power Management"
1755 source "drivers/cpufreq/Kconfig"
1757 source "drivers/cpuidle/Kconfig"
1761 menu "Floating point emulation"
1763 comment "At least one emulation must be selected"
1766 bool "NWFPE math emulation"
1767 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1769 Say Y to include the NWFPE floating point emulator in the kernel.
1770 This is necessary to run most binaries. Linux does not currently
1771 support floating point hardware so you need to say Y here even if
1772 your machine has an FPA or floating point co-processor podule.
1774 You may say N here if you are going to load the Acorn FPEmulator
1775 early in the bootup.
1778 bool "Support extended precision"
1779 depends on FPE_NWFPE
1781 Say Y to include 80-bit support in the kernel floating-point
1782 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1783 Note that gcc does not generate 80-bit operations by default,
1784 so in most cases this option only enlarges the size of the
1785 floating point emulator without any good reason.
1787 You almost surely want to say N here.
1790 bool "FastFPE math emulation (EXPERIMENTAL)"
1791 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1793 Say Y here to include the FAST floating point emulator in the kernel.
1794 This is an experimental much faster emulator which now also has full
1795 precision for the mantissa. It does not support any exceptions.
1796 It is very simple, and approximately 3-6 times faster than NWFPE.
1798 It should be sufficient for most programs. It may be not suitable
1799 for scientific calculations, but you have to check this for yourself.
1800 If you do not feel you need a faster FP emulation you should better
1804 bool "VFP-format floating point maths"
1805 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1807 Say Y to include VFP support code in the kernel. This is needed
1808 if your hardware includes a VFP unit.
1810 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1811 release notes and additional status information.
1813 Say N if your target does not have VFP hardware.
1821 bool "Advanced SIMD (NEON) Extension support"
1822 depends on VFPv3 && CPU_V7
1824 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1827 config KERNEL_MODE_NEON
1828 bool "Support for NEON in kernel mode"
1829 depends on NEON && AEABI
1831 Say Y to include support for NEON in kernel mode.
1835 menu "Power management options"
1837 source "kernel/power/Kconfig"
1839 config ARCH_SUSPEND_POSSIBLE
1840 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1841 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1844 config ARM_CPU_SUSPEND
1845 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1846 depends on ARCH_SUSPEND_POSSIBLE
1848 config ARCH_HIBERNATION_POSSIBLE
1851 default y if ARCH_SUSPEND_POSSIBLE
1855 source "arch/arm/Kconfig.assembler"