1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
28 select ARCH_HAS_GCOV_PROFILE_ALL
29 select ARCH_KEEP_MEMBLOCK
30 select ARCH_MIGHT_HAVE_PC_PARPORT
31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
34 select ARCH_SUPPORTS_ATOMIC_RMW
35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
36 select ARCH_USE_BUILTIN_BSWAP
37 select ARCH_USE_CMPXCHG_LOCKREF
38 select ARCH_USE_MEMTEST
39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
40 select ARCH_WANT_IPC_PARSE_VERSION
41 select ARCH_WANT_LD_ORPHAN_WARN
42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
43 select BUILDTIME_TABLE_SORT if MMU
44 select CLONE_BACKWARDS
45 select CPU_PM if SUSPEND || CPU_IDLE
46 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
47 select DMA_DECLARE_COHERENT
48 select DMA_GLOBAL_POOL if !MMU
50 select DMA_REMAP if MMU
52 select EDAC_ATOMIC_SCRUB
53 select GENERIC_ALLOCATOR
54 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
55 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
56 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
57 select GENERIC_IRQ_IPI if SMP
58 select GENERIC_CPU_AUTOPROBE
59 select GENERIC_EARLY_IOREMAP
60 select GENERIC_IDLE_POLL_SETUP
61 select GENERIC_IRQ_PROBE
62 select GENERIC_IRQ_SHOW
63 select GENERIC_IRQ_SHOW_LEVEL
64 select GENERIC_LIB_DEVMEM_IS_ALLOWED
65 select GENERIC_PCI_IOMAP
66 select GENERIC_SCHED_CLOCK
67 select GENERIC_SMP_IDLE_THREAD
68 select HANDLE_DOMAIN_IRQ
69 select HARDIRQS_SW_RESEND
70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
75 select HAVE_ARCH_MMAP_RND_BITS if MMU
76 select HAVE_ARCH_PFN_VALID
77 select HAVE_ARCH_SECCOMP
78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
80 select HAVE_ARCH_TRACEHOOK
81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
82 select HAVE_ARM_SMCCC if CPU_V7
83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
84 select HAVE_CONTEXT_TRACKING
85 select HAVE_C_RECORDMCOUNT
86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
87 select HAVE_DMA_CONTIGUOUS if MMU
88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
91 select HAVE_EXIT_THREAD
92 select HAVE_FAST_GUP if ARM_LPAE
93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
96 select HAVE_FUTEX_CMPXCHG if FUTEX
97 select HAVE_GCC_PLUGINS
98 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
99 select HAVE_IRQ_TIME_ACCOUNTING
100 select HAVE_KERNEL_GZIP
101 select HAVE_KERNEL_LZ4
102 select HAVE_KERNEL_LZMA
103 select HAVE_KERNEL_LZO
104 select HAVE_KERNEL_XZ
105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
106 select HAVE_KRETPROBES if HAVE_KPROBES
107 select HAVE_MOD_ARCH_SPECIFIC
109 select HAVE_OPTPROBES if !THUMB2_KERNEL
110 select HAVE_PERF_EVENTS
111 select HAVE_PERF_REGS
112 select HAVE_PERF_USER_STACK_DUMP
113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
114 select HAVE_REGS_AND_STACK_ACCESS_API
116 select HAVE_STACKPROTECTOR
117 select HAVE_SYSCALL_TRACEPOINTS
119 select HAVE_VIRT_CPU_ACCOUNTING_GEN
120 select IRQ_FORCED_THREADING
121 select MODULES_USE_ELF_REL
122 select NEED_DMA_MAP_STATE
123 select OF_EARLY_FLATTREE if OF
125 select OLD_SIGSUSPEND3
126 select PCI_SYSCALL if PCI
127 select PERF_USE_VMALLOC
129 select SYS_SUPPORTS_APM_EMULATION
130 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
131 # Above selects are sorted alphabetically; please add new ones
132 # according to that. Thanks.
134 The ARM series is a line of low-power-consumption RISC chip designs
135 licensed by ARM Ltd and targeted at embedded applications and
136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
137 manufactured, but legacy ARM-based PC hardware remains popular in
138 Europe. There is an ARM Linux project with a web page at
139 <http://www.arm.linux.org.uk/>.
141 config ARM_HAS_SG_CHAIN
144 config ARM_DMA_USE_IOMMU
146 select ARM_HAS_SG_CHAIN
147 select NEED_SG_DMA_LENGTH
151 config ARM_DMA_IOMMU_ALIGNMENT
152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
156 DMA mapping framework by default aligns all buffers to the smallest
157 PAGE_SIZE order which is greater than or equal to the requested buffer
158 size. This works well for buffers up to a few hundreds kilobytes, but
159 for larger buffers it just a waste of address space. Drivers which has
160 relatively small addressing window (like 64Mib) might run out of
161 virtual space with just a few allocations.
163 With this parameter you can specify the maximum PAGE_SIZE order for
164 DMA IOMMU buffers. Larger buffers will be aligned only to this
165 specified order. The order is expressed as a power of two multiplied
170 config SYS_SUPPORTS_APM_EMULATION
175 select GENERIC_ALLOCATOR
186 config STACKTRACE_SUPPORT
190 config LOCKDEP_SUPPORT
194 config ARCH_HAS_ILOG2_U32
197 config ARCH_HAS_ILOG2_U64
200 config ARCH_HAS_BANDGAP
203 config FIX_EARLYCON_MEM
206 config GENERIC_HWEIGHT
210 config GENERIC_CALIBRATE_DELAY
214 config ARCH_MAY_HAVE_PC_FDC
217 config ARCH_SUPPORTS_UPROBES
220 config ARCH_HAS_DMA_SET_COHERENT_MASK
223 config GENERIC_ISA_DMA
229 config NEED_RET_TO_USER
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 2 MiB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_IO_H
254 Select this when mach/io.h is required to provide special
255 definitions for this platform. The need for mach/io.h should
256 be avoided when possible.
258 config NEED_MACH_MEMORY_H
261 Select this when mach/memory.h is required to provide special
262 definitions for this platform. The need for mach/memory.h should
263 be avoided when possible.
266 hex "Physical address of main memory" if MMU
267 depends on !ARM_PATCH_PHYS_VIRT
268 default DRAM_BASE if !MMU
269 default 0x00000000 if ARCH_FOOTBRIDGE
270 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
271 default 0x20000000 if ARCH_S5PV210
272 default 0xc0000000 if ARCH_SA1100
274 Please provide the physical address corresponding to the
275 location of main memory in your system.
281 config PGTABLE_LEVELS
283 default 3 if ARM_LPAE
289 bool "MMU-based Paged Memory Management Support"
292 Select if you want MMU-based virtualised addressing space
293 support by paged memory management. If unsure, say 'Y'.
295 config ARCH_MMAP_RND_BITS_MIN
298 config ARCH_MMAP_RND_BITS_MAX
299 default 14 if PAGE_OFFSET=0x40000000
300 default 15 if PAGE_OFFSET=0x80000000
304 # The "ARM system type" choice list is ordered alphabetically by option
305 # text. Please add new entries in the option alphabetic order.
308 prompt "ARM system type"
309 default ARM_SINGLE_ARMV7M if !MMU
310 default ARCH_MULTIPLATFORM if MMU
312 config ARCH_MULTIPLATFORM
313 bool "Allow multiple platforms to be selected"
315 select ARCH_FLATMEM_ENABLE
316 select ARCH_SPARSEMEM_ENABLE
317 select ARCH_SELECT_MEMORY_MODEL
318 select ARM_HAS_SG_CHAIN
319 select ARM_PATCH_PHYS_VIRT
323 select GENERIC_IRQ_MULTI_HANDLER
325 select PCI_DOMAINS_GENERIC if PCI
329 config ARM_SINGLE_ARMV7M
330 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
343 select ARCH_SPARSEMEM_ENABLE
345 imply ARM_PATCH_PHYS_VIRT
347 select GENERIC_IRQ_MULTI_HANDLER
352 select HAVE_LEGACY_CLK
354 This enables support for the Cirrus EP93xx series of CPUs.
356 config ARCH_FOOTBRIDGE
360 select NEED_MACH_IO_H if !MMU
361 select NEED_MACH_MEMORY_H
363 Support for systems based on the DC21285 companion chip
364 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
372 select NEED_RET_TO_USER
376 Support for Intel's 80219 and IOP32X (XScale) family of
382 select ARCH_HAS_DMA_SET_COHERENT_MASK
383 select ARCH_SUPPORTS_BIG_ENDIAN
385 select DMABOUNCE if PCI
386 select GENERIC_IRQ_MULTI_HANDLER
392 # With the new PCI driver this is not needed
393 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
394 select USB_EHCI_BIG_ENDIAN_DESC
395 select USB_EHCI_BIG_ENDIAN_MMIO
397 Support for Intel's IXP4XX (XScale) family of processors.
402 select GENERIC_IRQ_MULTI_HANDLER
408 select PLAT_ORION_LEGACY
410 select PM_GENERIC_DOMAINS if PM
412 Support for the Marvell Dove SoC 88AP510
415 bool "PXA2xx/PXA3xx-based"
418 select ARM_CPU_SUSPEND if PM
424 select CPU_XSCALE if !CPU_XSC3
425 select GENERIC_IRQ_MULTI_HANDLER
432 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
438 select ARCH_MAY_HAVE_PC_FDC
439 select ARCH_SPARSEMEM_ENABLE
440 select ARM_HAS_SG_CHAIN
443 select HAVE_PATA_PLATFORM
445 select LEGACY_TIMER_TICK
446 select NEED_MACH_IO_H
447 select NEED_MACH_MEMORY_H
450 On the Acorn Risc-PC, Linux can support the internal IDE disk and
451 CD-ROM interface, serial and parallel port, and the floppy drive.
456 select ARCH_SPARSEMEM_ENABLE
459 select TIMER_OF if OF
463 select GENERIC_IRQ_MULTI_HANDLER
467 select NEED_MACH_MEMORY_H
470 Support for StrongARM 11x0 based boards.
473 bool "Samsung S3C24XX SoCs"
475 select CLKSRC_SAMSUNG_PWM
478 select GENERIC_IRQ_MULTI_HANDLER
479 select HAVE_S3C2410_I2C if I2C
480 select HAVE_S3C_RTC if RTC_CLASS
481 select NEED_MACH_IO_H
482 select S3C2410_WATCHDOG
487 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
488 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
489 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
490 Samsung SMDK2410 development board (and derivatives).
497 select GENERIC_IRQ_CHIP
498 select GENERIC_IRQ_MULTI_HANDLER
500 select HAVE_LEGACY_CLK
502 select NEED_MACH_IO_H if PCCARD
503 select NEED_MACH_MEMORY_H
506 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
510 menu "Multiple platform selection"
511 depends on ARCH_MULTIPLATFORM
513 comment "CPU Core family selection"
516 bool "ARMv4 based platforms (FA526)"
517 depends on !ARCH_MULTI_V6_V7
518 select ARCH_MULTI_V4_V5
521 config ARCH_MULTI_V4T
522 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
523 depends on !ARCH_MULTI_V6_V7
524 select ARCH_MULTI_V4_V5
525 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
526 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
527 CPU_ARM925T || CPU_ARM940T)
530 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
531 depends on !ARCH_MULTI_V6_V7
532 select ARCH_MULTI_V4_V5
533 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
534 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
535 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
537 config ARCH_MULTI_V4_V5
541 bool "ARMv6 based platforms (ARM11)"
542 select ARCH_MULTI_V6_V7
546 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
548 select ARCH_MULTI_V6_V7
552 config ARCH_MULTI_V6_V7
554 select MIGHT_HAVE_CACHE_L2X0
556 config ARCH_MULTI_CPU_AUTO
557 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
563 bool "Dummy Virtual Machine"
564 depends on ARCH_MULTI_V7
567 select ARM_GIC_V2M if PCI
569 select ARM_GIC_V3_ITS if PCI
571 select HAVE_ARM_ARCH_TIMER
572 select ARCH_SUPPORTS_BIG_ENDIAN
575 # This is sorted alphabetically by mach-* pathname. However, plat-*
576 # Kconfigs may be included either alphabetically (according to the
577 # plat- suffix) or along side the corresponding mach-* source.
579 source "arch/arm/mach-actions/Kconfig"
581 source "arch/arm/mach-alpine/Kconfig"
583 source "arch/arm/mach-artpec/Kconfig"
585 source "arch/arm/mach-asm9260/Kconfig"
587 source "arch/arm/mach-aspeed/Kconfig"
589 source "arch/arm/mach-at91/Kconfig"
591 source "arch/arm/mach-axxia/Kconfig"
593 source "arch/arm/mach-bcm/Kconfig"
595 source "arch/arm/mach-berlin/Kconfig"
597 source "arch/arm/mach-clps711x/Kconfig"
599 source "arch/arm/mach-cns3xxx/Kconfig"
601 source "arch/arm/mach-davinci/Kconfig"
603 source "arch/arm/mach-digicolor/Kconfig"
605 source "arch/arm/mach-dove/Kconfig"
607 source "arch/arm/mach-ep93xx/Kconfig"
609 source "arch/arm/mach-exynos/Kconfig"
611 source "arch/arm/mach-footbridge/Kconfig"
613 source "arch/arm/mach-gemini/Kconfig"
615 source "arch/arm/mach-highbank/Kconfig"
617 source "arch/arm/mach-hisi/Kconfig"
619 source "arch/arm/mach-imx/Kconfig"
621 source "arch/arm/mach-integrator/Kconfig"
623 source "arch/arm/mach-iop32x/Kconfig"
625 source "arch/arm/mach-ixp4xx/Kconfig"
627 source "arch/arm/mach-keystone/Kconfig"
629 source "arch/arm/mach-lpc32xx/Kconfig"
631 source "arch/arm/mach-mediatek/Kconfig"
633 source "arch/arm/mach-meson/Kconfig"
635 source "arch/arm/mach-milbeaut/Kconfig"
637 source "arch/arm/mach-mmp/Kconfig"
639 source "arch/arm/mach-moxart/Kconfig"
641 source "arch/arm/mach-mstar/Kconfig"
643 source "arch/arm/mach-mv78xx0/Kconfig"
645 source "arch/arm/mach-mvebu/Kconfig"
647 source "arch/arm/mach-mxs/Kconfig"
649 source "arch/arm/mach-nomadik/Kconfig"
651 source "arch/arm/mach-npcm/Kconfig"
653 source "arch/arm/mach-nspire/Kconfig"
655 source "arch/arm/plat-omap/Kconfig"
657 source "arch/arm/mach-omap1/Kconfig"
659 source "arch/arm/mach-omap2/Kconfig"
661 source "arch/arm/mach-orion5x/Kconfig"
663 source "arch/arm/mach-oxnas/Kconfig"
665 source "arch/arm/mach-pxa/Kconfig"
666 source "arch/arm/plat-pxa/Kconfig"
668 source "arch/arm/mach-qcom/Kconfig"
670 source "arch/arm/mach-rda/Kconfig"
672 source "arch/arm/mach-realtek/Kconfig"
674 source "arch/arm/mach-realview/Kconfig"
676 source "arch/arm/mach-rockchip/Kconfig"
678 source "arch/arm/mach-s3c/Kconfig"
680 source "arch/arm/mach-s5pv210/Kconfig"
682 source "arch/arm/mach-sa1100/Kconfig"
684 source "arch/arm/mach-shmobile/Kconfig"
686 source "arch/arm/mach-socfpga/Kconfig"
688 source "arch/arm/mach-spear/Kconfig"
690 source "arch/arm/mach-sti/Kconfig"
692 source "arch/arm/mach-stm32/Kconfig"
694 source "arch/arm/mach-sunxi/Kconfig"
696 source "arch/arm/mach-tegra/Kconfig"
698 source "arch/arm/mach-uniphier/Kconfig"
700 source "arch/arm/mach-ux500/Kconfig"
702 source "arch/arm/mach-versatile/Kconfig"
704 source "arch/arm/mach-vexpress/Kconfig"
706 source "arch/arm/mach-vt8500/Kconfig"
708 source "arch/arm/mach-zynq/Kconfig"
710 # ARMv7-M architecture
712 bool "NXP LPC18xx/LPC43xx"
713 depends on ARM_SINGLE_ARMV7M
714 select ARCH_HAS_RESET_CONTROLLER
716 select CLKSRC_LPC32XX
719 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
720 high performance microcontrollers.
723 bool "ARM MPS2 platform"
724 depends on ARM_SINGLE_ARMV7M
728 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
729 with a range of available cores like Cortex-M3/M4/M7.
731 Please, note that depends which Application Note is used memory map
732 for the platform may vary, so adjustment of RAM base might be needed.
734 # Definitions to make life easier
745 select GENERIC_IRQ_CHIP
748 config PLAT_ORION_LEGACY
755 config PLAT_VERSATILE
758 source "arch/arm/mm/Kconfig"
761 bool "Enable iWMMXt support"
762 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
763 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
765 Enable support for iWMMXt context switching at run time if
766 running on a CPU that supports it.
769 source "arch/arm/Kconfig-nommu"
772 config PJ4B_ERRATA_4742
773 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
774 depends on CPU_PJ4B && MACH_ARMADA_370
777 When coming out of either a Wait for Interrupt (WFI) or a Wait for
778 Event (WFE) IDLE states, a specific timing sensitivity exists between
779 the retiring WFI/WFE instructions and the newly issued subsequent
780 instructions. This sensitivity can result in a CPU hang scenario.
782 The software must insert either a Data Synchronization Barrier (DSB)
783 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
786 config ARM_ERRATA_326103
787 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
790 Executing a SWP instruction to read-only memory does not set bit 11
791 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
792 treat the access as a read, preventing a COW from occurring and
793 causing the faulting task to livelock.
795 config ARM_ERRATA_411920
796 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
797 depends on CPU_V6 || CPU_V6K
799 Invalidation of the Instruction Cache operation can
800 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
801 It does not affect the MPCore. This option enables the ARM Ltd.
802 recommended workaround.
804 config ARM_ERRATA_430973
805 bool "ARM errata: Stale prediction on replaced interworking branch"
808 This option enables the workaround for the 430973 Cortex-A8
809 r1p* erratum. If a code sequence containing an ARM/Thumb
810 interworking branch is replaced with another code sequence at the
811 same virtual address, whether due to self-modifying code or virtual
812 to physical address re-mapping, Cortex-A8 does not recover from the
813 stale interworking branch prediction. This results in Cortex-A8
814 executing the new code sequence in the incorrect ARM or Thumb state.
815 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
816 and also flushes the branch target cache at every context switch.
817 Note that setting specific bits in the ACTLR register may not be
818 available in non-secure mode.
820 config ARM_ERRATA_458693
821 bool "ARM errata: Processor deadlock when a false hazard is created"
823 depends on !ARCH_MULTIPLATFORM
825 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
826 erratum. For very specific sequences of memory operations, it is
827 possible for a hazard condition intended for a cache line to instead
828 be incorrectly associated with a different cache line. This false
829 hazard might then cause a processor deadlock. The workaround enables
830 the L1 caching of the NEON accesses and disables the PLD instruction
831 in the ACTLR register. Note that setting specific bits in the ACTLR
832 register may not be available in non-secure mode.
834 config ARM_ERRATA_460075
835 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
837 depends on !ARCH_MULTIPLATFORM
839 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
840 erratum. Any asynchronous access to the L2 cache may encounter a
841 situation in which recent store transactions to the L2 cache are lost
842 and overwritten with stale memory contents from external memory. The
843 workaround disables the write-allocate mode for the L2 cache via the
844 ACTLR register. Note that setting specific bits in the ACTLR register
845 may not be available in non-secure mode.
847 config ARM_ERRATA_742230
848 bool "ARM errata: DMB operation may be faulty"
849 depends on CPU_V7 && SMP
850 depends on !ARCH_MULTIPLATFORM
852 This option enables the workaround for the 742230 Cortex-A9
853 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
854 between two write operations may not ensure the correct visibility
855 ordering of the two writes. This workaround sets a specific bit in
856 the diagnostic register of the Cortex-A9 which causes the DMB
857 instruction to behave as a DSB, ensuring the correct behaviour of
860 config ARM_ERRATA_742231
861 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
862 depends on CPU_V7 && SMP
863 depends on !ARCH_MULTIPLATFORM
865 This option enables the workaround for the 742231 Cortex-A9
866 (r2p0..r2p2) erratum. Under certain conditions, specific to the
867 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
868 accessing some data located in the same cache line, may get corrupted
869 data due to bad handling of the address hazard when the line gets
870 replaced from one of the CPUs at the same time as another CPU is
871 accessing it. This workaround sets specific bits in the diagnostic
872 register of the Cortex-A9 which reduces the linefill issuing
873 capabilities of the processor.
875 config ARM_ERRATA_643719
876 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
877 depends on CPU_V7 && SMP
880 This option enables the workaround for the 643719 Cortex-A9 (prior to
881 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
882 register returns zero when it should return one. The workaround
883 corrects this value, ensuring cache maintenance operations which use
884 it behave as intended and avoiding data corruption.
886 config ARM_ERRATA_720789
887 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
890 This option enables the workaround for the 720789 Cortex-A9 (prior to
891 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
892 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
893 As a consequence of this erratum, some TLB entries which should be
894 invalidated are not, resulting in an incoherency in the system page
895 tables. The workaround changes the TLB flushing routines to invalidate
896 entries regardless of the ASID.
898 config ARM_ERRATA_743622
899 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
901 depends on !ARCH_MULTIPLATFORM
903 This option enables the workaround for the 743622 Cortex-A9
904 (r2p*) erratum. Under very rare conditions, a faulty
905 optimisation in the Cortex-A9 Store Buffer may lead to data
906 corruption. This workaround sets a specific bit in the diagnostic
907 register of the Cortex-A9 which disables the Store Buffer
908 optimisation, preventing the defect from occurring. This has no
909 visible impact on the overall performance or power consumption of the
912 config ARM_ERRATA_751472
913 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
915 depends on !ARCH_MULTIPLATFORM
917 This option enables the workaround for the 751472 Cortex-A9 (prior
918 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
919 completion of a following broadcasted operation if the second
920 operation is received by a CPU before the ICIALLUIS has completed,
921 potentially leading to corrupted entries in the cache or TLB.
923 config ARM_ERRATA_754322
924 bool "ARM errata: possible faulty MMU translations following an ASID switch"
927 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
928 r3p*) erratum. A speculative memory access may cause a page table walk
929 which starts prior to an ASID switch but completes afterwards. This
930 can populate the micro-TLB with a stale entry which may be hit with
931 the new ASID. This workaround places two dsb instructions in the mm
932 switching code so that no page table walks can cross the ASID switch.
934 config ARM_ERRATA_754327
935 bool "ARM errata: no automatic Store Buffer drain"
936 depends on CPU_V7 && SMP
938 This option enables the workaround for the 754327 Cortex-A9 (prior to
939 r2p0) erratum. The Store Buffer does not have any automatic draining
940 mechanism and therefore a livelock may occur if an external agent
941 continuously polls a memory location waiting to observe an update.
942 This workaround defines cpu_relax() as smp_mb(), preventing correctly
943 written polling loops from denying visibility of updates to memory.
945 config ARM_ERRATA_364296
946 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
949 This options enables the workaround for the 364296 ARM1136
950 r0p2 erratum (possible cache data corruption with
951 hit-under-miss enabled). It sets the undocumented bit 31 in
952 the auxiliary control register and the FI bit in the control
953 register, thus disabling hit-under-miss without putting the
954 processor into full low interrupt latency mode. ARM11MPCore
957 config ARM_ERRATA_764369
958 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
959 depends on CPU_V7 && SMP
961 This option enables the workaround for erratum 764369
962 affecting Cortex-A9 MPCore with two or more processors (all
963 current revisions). Under certain timing circumstances, a data
964 cache line maintenance operation by MVA targeting an Inner
965 Shareable memory region may fail to proceed up to either the
966 Point of Coherency or to the Point of Unification of the
967 system. This workaround adds a DSB instruction before the
968 relevant cache maintenance functions and sets a specific bit
969 in the diagnostic control register of the SCU.
971 config ARM_ERRATA_775420
972 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
975 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
976 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
977 operation aborts with MMU exception, it might cause the processor
978 to deadlock. This workaround puts DSB before executing ISB if
979 an abort may occur on cache maintenance.
981 config ARM_ERRATA_798181
982 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
983 depends on CPU_V7 && SMP
985 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
986 adequately shooting down all use of the old entries. This
987 option enables the Linux kernel workaround for this erratum
988 which sends an IPI to the CPUs that are running the same ASID
989 as the one being invalidated.
991 config ARM_ERRATA_773022
992 bool "ARM errata: incorrect instructions may be executed from loop buffer"
995 This option enables the workaround for the 773022 Cortex-A15
996 (up to r0p4) erratum. In certain rare sequences of code, the
997 loop buffer may deliver incorrect instructions. This
998 workaround disables the loop buffer to avoid the erratum.
1000 config ARM_ERRATA_818325_852422
1001 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1004 This option enables the workaround for:
1005 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1006 instruction might deadlock. Fixed in r0p1.
1007 - Cortex-A12 852422: Execution of a sequence of instructions might
1008 lead to either a data corruption or a CPU deadlock. Not fixed in
1009 any Cortex-A12 cores yet.
1010 This workaround for all both errata involves setting bit[12] of the
1011 Feature Register. This bit disables an optimisation applied to a
1012 sequence of 2 instructions that use opposing condition codes.
1014 config ARM_ERRATA_821420
1015 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1018 This option enables the workaround for the 821420 Cortex-A12
1019 (all revs) erratum. In very rare timing conditions, a sequence
1020 of VMOV to Core registers instructions, for which the second
1021 one is in the shadow of a branch or abort, can lead to a
1022 deadlock when the VMOV instructions are issued out-of-order.
1024 config ARM_ERRATA_825619
1025 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1028 This option enables the workaround for the 825619 Cortex-A12
1029 (all revs) erratum. Within rare timing constraints, executing a
1030 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1031 and Device/Strongly-Ordered loads and stores might cause deadlock
1033 config ARM_ERRATA_857271
1034 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1037 This option enables the workaround for the 857271 Cortex-A12
1038 (all revs) erratum. Under very rare timing conditions, the CPU might
1039 hang. The workaround is expected to have a < 1% performance impact.
1041 config ARM_ERRATA_852421
1042 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1045 This option enables the workaround for the 852421 Cortex-A17
1046 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1047 execution of a DMB ST instruction might fail to properly order
1048 stores from GroupA and stores from GroupB.
1050 config ARM_ERRATA_852423
1051 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1054 This option enables the workaround for:
1055 - Cortex-A17 852423: Execution of a sequence of instructions might
1056 lead to either a data corruption or a CPU deadlock. Not fixed in
1057 any Cortex-A17 cores yet.
1058 This is identical to Cortex-A12 erratum 852422. It is a separate
1059 config option from the A12 erratum due to the way errata are checked
1062 config ARM_ERRATA_857272
1063 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1066 This option enables the workaround for the 857272 Cortex-A17 erratum.
1067 This erratum is not known to be fixed in any A17 revision.
1068 This is identical to Cortex-A12 erratum 857271. It is a separate
1069 config option from the A12 erratum due to the way errata are checked
1074 source "arch/arm/common/Kconfig"
1081 Find out whether you have ISA slots on your motherboard. ISA is the
1082 name of a bus system, i.e. the way the CPU talks to the other stuff
1083 inside your box. Other bus systems are PCI, EISA, MicroChannel
1084 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1085 newer boards don't support it. If you have ISA, say Y, otherwise N.
1087 # Select ISA DMA controller support
1092 # Select ISA DMA interface
1096 config PCI_NANOENGINE
1097 bool "BSE nanoEngine PCI support"
1098 depends on SA1100_NANOENGINE
1100 Enable PCI on the BSE nanoEngine board.
1102 config ARM_ERRATA_814220
1103 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1106 The v7 ARM states that all cache and branch predictor maintenance
1107 operations that do not specify an address execute, relative to
1108 each other, in program order.
1109 However, because of this erratum, an L2 set/way cache maintenance
1110 operation can overtake an L1 set/way cache maintenance operation.
1111 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1116 menu "Kernel Features"
1121 This option should be selected by machines which have an SMP-
1124 The only effect of this option is to make the SMP-related
1125 options available to the user for configuration.
1128 bool "Symmetric Multi-Processing"
1129 depends on CPU_V6K || CPU_V7
1131 depends on MMU || ARM_MPU
1134 This enables support for systems with more than one CPU. If you have
1135 a system with only one CPU, say N. If you have a system with more
1136 than one CPU, say Y.
1138 If you say N here, the kernel will run on uni- and multiprocessor
1139 machines, but will use only one CPU of a multiprocessor machine. If
1140 you say Y here, the kernel will run on many, but not all,
1141 uniprocessor machines. On a uniprocessor machine, the kernel
1142 will run faster if you say N here.
1144 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1145 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1146 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1148 If you don't know what to do here, say N.
1151 bool "Allow booting SMP kernel on uniprocessor systems"
1152 depends on SMP && !XIP_KERNEL && MMU
1155 SMP kernels contain instructions which fail on non-SMP processors.
1156 Enabling this option allows the kernel to modify itself to make
1157 these instructions safe. Disabling it allows about 1K of space
1160 If you don't know what to do here, say Y.
1162 config ARM_CPU_TOPOLOGY
1163 bool "Support cpu topology definition"
1164 depends on SMP && CPU_V7
1167 Support ARM cpu topology definition. The MPIDR register defines
1168 affinity between processors which is then used to describe the cpu
1169 topology of an ARM System.
1172 bool "Multi-core scheduler support"
1173 depends on ARM_CPU_TOPOLOGY
1175 Multi-core scheduler support improves the CPU scheduler's decision
1176 making when dealing with multi-core CPU chips at a cost of slightly
1177 increased overhead in some places. If unsure say N here.
1180 bool "SMT scheduler support"
1181 depends on ARM_CPU_TOPOLOGY
1183 Improves the CPU scheduler's decision making when dealing with
1184 MultiThreading at a cost of slightly increased overhead in some
1185 places. If unsure say N here.
1190 This option enables support for the ARM snoop control unit
1192 config HAVE_ARM_ARCH_TIMER
1193 bool "Architected timer support"
1195 select ARM_ARCH_TIMER
1197 This option enables support for the ARM architected timer
1202 This options enables support for the ARM timer and watchdog unit
1205 bool "Multi-Cluster Power Management"
1206 depends on CPU_V7 && SMP
1208 This option provides the common power management infrastructure
1209 for (multi-)cluster based systems, such as big.LITTLE based
1212 config MCPM_QUAD_CLUSTER
1216 To avoid wasting resources unnecessarily, MCPM only supports up
1217 to 2 clusters by default.
1218 Platforms with 3 or 4 clusters that use MCPM must select this
1219 option to allow the additional clusters to be managed.
1222 bool "big.LITTLE support (Experimental)"
1223 depends on CPU_V7 && SMP
1226 This option enables support selections for the big.LITTLE
1227 system architecture.
1230 bool "big.LITTLE switcher support"
1231 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1234 The big.LITTLE "switcher" provides the core functionality to
1235 transparently handle transition between a cluster of A15's
1236 and a cluster of A7's in a big.LITTLE system.
1238 config BL_SWITCHER_DUMMY_IF
1239 tristate "Simple big.LITTLE switcher user interface"
1240 depends on BL_SWITCHER && DEBUG_KERNEL
1242 This is a simple and dummy char dev interface to control
1243 the big.LITTLE switcher core code. It is meant for
1244 debugging purposes only.
1247 prompt "Memory split"
1251 Select the desired split between kernel and user memory.
1253 If you are not absolutely sure what you are doing, leave this
1257 bool "3G/1G user/kernel split"
1258 config VMSPLIT_3G_OPT
1259 depends on !ARM_LPAE
1260 bool "3G/1G user/kernel split (for full 1G low memory)"
1262 bool "2G/2G user/kernel split"
1264 bool "1G/3G user/kernel split"
1269 default PHYS_OFFSET if !MMU
1270 default 0x40000000 if VMSPLIT_1G
1271 default 0x80000000 if VMSPLIT_2G
1272 default 0xB0000000 if VMSPLIT_3G_OPT
1275 config KASAN_SHADOW_OFFSET
1278 default 0x1f000000 if PAGE_OFFSET=0x40000000
1279 default 0x5f000000 if PAGE_OFFSET=0x80000000
1280 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1281 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1285 int "Maximum number of CPUs (2-32)"
1286 range 2 16 if DEBUG_KMAP_LOCAL
1287 range 2 32 if !DEBUG_KMAP_LOCAL
1291 The maximum number of CPUs that the kernel can support.
1292 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1293 debugging is enabled, which uses half of the per-CPU fixmap
1294 slots as guard regions.
1297 bool "Support for hot-pluggable CPUs"
1299 select GENERIC_IRQ_MIGRATION
1301 Say Y here to experiment with turning CPUs off and on. CPUs
1302 can be controlled through /sys/devices/system/cpu.
1305 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1306 depends on HAVE_ARM_SMCCC
1309 Say Y here if you want Linux to communicate with system firmware
1310 implementing the PSCI specification for CPU-centric power
1311 management operations described in ARM document number ARM DEN
1312 0022A ("Power State Coordination Interface System Software on
1315 # The GPIO number here must be sorted by descending number. In case of
1316 # a multiplatform kernel, we just want the highest value required by the
1317 # selected platforms.
1320 default 2048 if ARCH_INTEL_SOCFPGA
1321 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1322 ARCH_ZYNQ || ARCH_ASPEED
1323 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1324 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1325 default 416 if ARCH_SUNXI
1326 default 392 if ARCH_U8500
1327 default 352 if ARCH_VT8500
1328 default 288 if ARCH_ROCKCHIP
1329 default 264 if MACH_H4700
1332 Maximum number of GPIOs in the system.
1334 If unsure, leave the default value.
1338 default 128 if SOC_AT91RM9200
1342 depends on HZ_FIXED = 0
1343 prompt "Timer frequency"
1367 default HZ_FIXED if HZ_FIXED != 0
1368 default 100 if HZ_100
1369 default 200 if HZ_200
1370 default 250 if HZ_250
1371 default 300 if HZ_300
1372 default 500 if HZ_500
1376 def_bool HIGH_RES_TIMERS
1378 config THUMB2_KERNEL
1379 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1380 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1381 default y if CPU_THUMBONLY
1384 By enabling this option, the kernel will be compiled in
1389 config ARM_PATCH_IDIV
1390 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1391 depends on CPU_32v7 && !XIP_KERNEL
1394 The ARM compiler inserts calls to __aeabi_idiv() and
1395 __aeabi_uidiv() when it needs to perform division on signed
1396 and unsigned integers. Some v7 CPUs have support for the sdiv
1397 and udiv instructions that can be used to implement those
1400 Enabling this option allows the kernel to modify itself to
1401 replace the first two instructions of these library functions
1402 with the sdiv or udiv plus "bx lr" instructions when the CPU
1403 it is running on supports them. Typically this will be faster
1404 and less power intensive than running the original library
1405 code to do integer division.
1408 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1409 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1410 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1412 This option allows for the kernel to be compiled using the latest
1413 ARM ABI (aka EABI). This is only useful if you are using a user
1414 space environment that is also compiled with EABI.
1416 Since there are major incompatibilities between the legacy ABI and
1417 EABI, especially with regard to structure member alignment, this
1418 option also changes the kernel syscall calling convention to
1419 disambiguate both ABIs and allow for backward compatibility support
1420 (selected with CONFIG_OABI_COMPAT).
1422 To use this you need GCC version 4.0.0 or later.
1425 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1426 depends on AEABI && !THUMB2_KERNEL
1428 This option preserves the old syscall interface along with the
1429 new (ARM EABI) one. It also provides a compatibility layer to
1430 intercept syscalls that have structure arguments which layout
1431 in memory differs between the legacy ABI and the new ARM EABI
1432 (only for non "thumb" binaries). This option adds a tiny
1433 overhead to all syscalls and produces a slightly larger kernel.
1435 The seccomp filter system will not be available when this is
1436 selected, since there is no way yet to sensibly distinguish
1437 between calling conventions during filtering.
1439 If you know you'll be using only pure EABI user space then you
1440 can say N here. If this option is not selected and you attempt
1441 to execute a legacy ABI binary then the result will be
1442 UNPREDICTABLE (in fact it can be predicted that it won't work
1443 at all). If in doubt say N.
1445 config ARCH_SELECT_MEMORY_MODEL
1448 config ARCH_FLATMEM_ENABLE
1451 config ARCH_SPARSEMEM_ENABLE
1453 select SPARSEMEM_STATIC if SPARSEMEM
1456 bool "High Memory Support"
1459 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1461 The address space of ARM processors is only 4 Gigabytes large
1462 and it has to accommodate user address space, kernel address
1463 space as well as some memory mapped IO. That means that, if you
1464 have a large amount of physical memory and/or IO, not all of the
1465 memory can be "permanently mapped" by the kernel. The physical
1466 memory that is not permanently mapped is called "high memory".
1468 Depending on the selected kernel/user memory split, minimum
1469 vmalloc space and actual amount of RAM, you may not need this
1470 option which should result in a slightly faster kernel.
1475 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1479 The VM uses one page of physical memory for each page table.
1480 For systems with a lot of processes, this can use a lot of
1481 precious low memory, eventually leading to low memory being
1482 consumed by page tables. Setting this option will allow
1483 user-space 2nd level page tables to reside in high memory.
1485 config CPU_SW_DOMAIN_PAN
1486 bool "Enable use of CPU domains to implement privileged no-access"
1487 depends on MMU && !ARM_LPAE
1490 Increase kernel security by ensuring that normal kernel accesses
1491 are unable to access userspace addresses. This can help prevent
1492 use-after-free bugs becoming an exploitable privilege escalation
1493 by ensuring that magic values (such as LIST_POISON) will always
1494 fault when dereferenced.
1496 CPUs with low-vector mappings use a best-efforts implementation.
1497 Their lower 1MB needs to remain accessible for the vectors, but
1498 the remainder of userspace will become appropriately inaccessible.
1500 config HW_PERF_EVENTS
1504 config ARCH_WANT_GENERAL_HUGETLB
1507 config ARM_MODULE_PLTS
1508 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1512 Allocate PLTs when loading modules so that jumps and calls whose
1513 targets are too far away for their relative offsets to be encoded
1514 in the instructions themselves can be bounced via veneers in the
1515 module's PLT. This allows modules to be allocated in the generic
1516 vmalloc area after the dedicated module memory area has been
1517 exhausted. The modules will use slightly more memory, but after
1518 rounding up to page size, the actual memory footprint is usually
1521 Disabling this is usually safe for small single-platform
1522 configurations. If unsure, say y.
1524 config FORCE_MAX_ZONEORDER
1525 int "Maximum zone order"
1526 default "12" if SOC_AM33XX
1527 default "9" if SA1111
1530 The kernel memory allocator divides physically contiguous memory
1531 blocks into "zones", where each zone is a power of two number of
1532 pages. This option selects the largest power of two that the kernel
1533 keeps in the memory allocator. If you need to allocate very large
1534 blocks of physically contiguous memory, then you may need to
1535 increase this value.
1537 This config option is actually maximum order plus one. For example,
1538 a value of 11 means that the largest free memory block is 2^10 pages.
1540 config ALIGNMENT_TRAP
1541 def_bool CPU_CP15_MMU
1542 select HAVE_PROC_CPU if PROC_FS
1544 ARM processors cannot fetch/store information which is not
1545 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1546 address divisible by 4. On 32-bit ARM processors, these non-aligned
1547 fetch/store instructions will be emulated in software if you say
1548 here, which has a severe performance impact. This is necessary for
1549 correct operation of some network protocols. With an IP-only
1550 configuration it is safe to say N, otherwise say Y.
1552 config UACCESS_WITH_MEMCPY
1553 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1555 default y if CPU_FEROCEON
1557 Implement faster copy_to_user and clear_user methods for CPU
1558 cores where a 8-word STM instruction give significantly higher
1559 memory write throughput than a sequence of individual 32bit stores.
1561 A possible side effect is a slight increase in scheduling latency
1562 between threads sharing the same address space if they invoke
1563 such copy operations with large buffers.
1565 However, if the CPU data cache is using a write-allocate mode,
1566 this option is unlikely to provide any performance gain.
1569 bool "Enable paravirtualization code"
1571 This changes the kernel so it can modify itself when it is run
1572 under a hypervisor, potentially improving performance significantly
1573 over full virtualization.
1575 config PARAVIRT_TIME_ACCOUNTING
1576 bool "Paravirtual steal time accounting"
1579 Select this option to enable fine granularity task steal time
1580 accounting. Time spent executing other tasks in parallel with
1581 the current vCPU is discounted from the vCPU power. To account for
1582 that, there can be a small performance impact.
1584 If in doubt, say N here.
1591 bool "Xen guest support on ARM"
1592 depends on ARM && AEABI && OF
1593 depends on CPU_V7 && !CPU_V6
1594 depends on !GENERIC_ATOMIC64
1596 select ARCH_DMA_ADDR_T_64BIT
1602 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1604 config STACKPROTECTOR_PER_TASK
1605 bool "Use a unique stack canary value for each task"
1606 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1607 select GCC_PLUGIN_ARM_SSP_PER_TASK
1610 Due to the fact that GCC uses an ordinary symbol reference from
1611 which to load the value of the stack canary, this value can only
1612 change at reboot time on SMP systems, and all tasks running in the
1613 kernel's address space are forced to use the same canary value for
1614 the entire duration that the system is up.
1616 Enable this option to switch to a different method that uses a
1617 different canary value for each task.
1624 bool "Flattened Device Tree support"
1628 Include support for flattened device tree machine descriptions.
1631 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1634 This is the traditional way of passing data to the kernel at boot
1635 time. If you are solely relying on the flattened device tree (or
1636 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1637 to remove ATAGS support from your kernel binary. If unsure,
1640 config DEPRECATED_PARAM_STRUCT
1641 bool "Provide old way to pass kernel parameters"
1644 This was deprecated in 2001 and announced to live on for 5 years.
1645 Some old boot loaders still use this way.
1647 # Compressed boot loader in ROM. Yes, we really want to ask about
1648 # TEXT and BSS so we preserve their values in the config files.
1649 config ZBOOT_ROM_TEXT
1650 hex "Compressed ROM boot loader base address"
1653 The physical address at which the ROM-able zImage is to be
1654 placed in the target. Platforms which normally make use of
1655 ROM-able zImage formats normally set this to a suitable
1656 value in their defconfig file.
1658 If ZBOOT_ROM is not enabled, this has no effect.
1660 config ZBOOT_ROM_BSS
1661 hex "Compressed ROM boot loader BSS address"
1664 The base address of an area of read/write memory in the target
1665 for the ROM-able zImage which must be available while the
1666 decompressor is running. It must be large enough to hold the
1667 entire decompressed kernel plus an additional 128 KiB.
1668 Platforms which normally make use of ROM-able zImage formats
1669 normally set this to a suitable value in their defconfig file.
1671 If ZBOOT_ROM is not enabled, this has no effect.
1674 bool "Compressed boot loader in ROM/flash"
1675 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1676 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1678 Say Y here if you intend to execute your compressed kernel image
1679 (zImage) directly from ROM or flash. If unsure, say N.
1681 config ARM_APPENDED_DTB
1682 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1685 With this option, the boot code will look for a device tree binary
1686 (DTB) appended to zImage
1687 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1689 This is meant as a backward compatibility convenience for those
1690 systems with a bootloader that can't be upgraded to accommodate
1691 the documented boot protocol using a device tree.
1693 Beware that there is very little in terms of protection against
1694 this option being confused by leftover garbage in memory that might
1695 look like a DTB header after a reboot if no actual DTB is appended
1696 to zImage. Do not leave this option active in a production kernel
1697 if you don't intend to always append a DTB. Proper passing of the
1698 location into r2 of a bootloader provided DTB is always preferable
1701 config ARM_ATAG_DTB_COMPAT
1702 bool "Supplement the appended DTB with traditional ATAG information"
1703 depends on ARM_APPENDED_DTB
1705 Some old bootloaders can't be updated to a DTB capable one, yet
1706 they provide ATAGs with memory configuration, the ramdisk address,
1707 the kernel cmdline string, etc. Such information is dynamically
1708 provided by the bootloader and can't always be stored in a static
1709 DTB. To allow a device tree enabled kernel to be used with such
1710 bootloaders, this option allows zImage to extract the information
1711 from the ATAG list and store it at run time into the appended DTB.
1714 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1715 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1717 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1718 bool "Use bootloader kernel arguments if available"
1720 Uses the command-line options passed by the boot loader instead of
1721 the device tree bootargs property. If the boot loader doesn't provide
1722 any, the device tree bootargs property will be used.
1724 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1725 bool "Extend with bootloader kernel arguments"
1727 The command-line arguments provided by the boot loader will be
1728 appended to the the device tree bootargs property.
1733 string "Default kernel command string"
1736 On some architectures (e.g. CATS), there is currently no way
1737 for the boot loader to pass arguments to the kernel. For these
1738 architectures, you should supply some command-line options at build
1739 time by entering them here. As a minimum, you should specify the
1740 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1743 prompt "Kernel command line type" if CMDLINE != ""
1744 default CMDLINE_FROM_BOOTLOADER
1746 config CMDLINE_FROM_BOOTLOADER
1747 bool "Use bootloader kernel arguments if available"
1749 Uses the command-line options passed by the boot loader. If
1750 the boot loader doesn't provide any, the default kernel command
1751 string provided in CMDLINE will be used.
1753 config CMDLINE_EXTEND
1754 bool "Extend bootloader kernel arguments"
1756 The command-line arguments provided by the boot loader will be
1757 appended to the default kernel command string.
1759 config CMDLINE_FORCE
1760 bool "Always use the default kernel command string"
1762 Always use the default kernel command string, even if the boot
1763 loader passes other arguments to the kernel.
1764 This is useful if you cannot or don't want to change the
1765 command-line options your boot loader passes to the kernel.
1769 bool "Kernel Execute-In-Place from ROM"
1770 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1772 Execute-In-Place allows the kernel to run from non-volatile storage
1773 directly addressable by the CPU, such as NOR flash. This saves RAM
1774 space since the text section of the kernel is not loaded from flash
1775 to RAM. Read-write sections, such as the data section and stack,
1776 are still copied to RAM. The XIP kernel is not compressed since
1777 it has to run directly from flash, so it will take more space to
1778 store it. The flash address used to link the kernel object files,
1779 and for storing it, is configuration dependent. Therefore, if you
1780 say Y here, you must know the proper physical address where to
1781 store the kernel image depending on your own flash memory usage.
1783 Also note that the make target becomes "make xipImage" rather than
1784 "make zImage" or "make Image". The final kernel binary to put in
1785 ROM memory will be arch/arm/boot/xipImage.
1789 config XIP_PHYS_ADDR
1790 hex "XIP Kernel Physical Location"
1791 depends on XIP_KERNEL
1792 default "0x00080000"
1794 This is the physical address in your flash memory the kernel will
1795 be linked for and stored to. This address is dependent on your
1798 config XIP_DEFLATED_DATA
1799 bool "Store kernel .data section compressed in ROM"
1800 depends on XIP_KERNEL
1803 Before the kernel is actually executed, its .data section has to be
1804 copied to RAM from ROM. This option allows for storing that data
1805 in compressed form and decompressed to RAM rather than merely being
1806 copied, saving some precious ROM space. A possible drawback is a
1807 slightly longer boot delay.
1810 bool "Kexec system call (EXPERIMENTAL)"
1811 depends on (!SMP || PM_SLEEP_SMP)
1815 kexec is a system call that implements the ability to shutdown your
1816 current kernel, and to start another kernel. It is like a reboot
1817 but it is independent of the system firmware. And like a reboot
1818 you can start any kernel with it, not just Linux.
1820 It is an ongoing process to be certain the hardware in a machine
1821 is properly shutdown, so do not be surprised if this code does not
1822 initially work for you.
1825 bool "Export atags in procfs"
1826 depends on ATAGS && KEXEC
1829 Should the atags used to boot the kernel be exported in an "atags"
1830 file in procfs. Useful with kexec.
1833 bool "Build kdump crash kernel (EXPERIMENTAL)"
1835 Generate crash dump after being started by kexec. This should
1836 be normally only set in special crash dump kernels which are
1837 loaded in the main kernel with kexec-tools into a specially
1838 reserved region and then later executed after a crash by
1839 kdump/kexec. The crash dump kernel must be compiled to a
1840 memory address not used by the main kernel
1842 For more details see Documentation/admin-guide/kdump/kdump.rst
1844 config AUTO_ZRELADDR
1845 bool "Auto calculation of the decompressed kernel image address"
1847 ZRELADDR is the physical address where the decompressed kernel
1848 image will be placed. If AUTO_ZRELADDR is selected, the address
1849 will be determined at run-time, either by masking the current IP
1850 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1851 This assumes the zImage being placed in the first 128MB from
1858 bool "UEFI runtime support"
1859 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1861 select EFI_PARAMS_FROM_FDT
1863 select EFI_GENERIC_STUB
1864 select EFI_RUNTIME_WRAPPERS
1866 This option provides support for runtime services provided
1867 by UEFI firmware (such as non-volatile variables, realtime
1868 clock, and platform reset). A UEFI stub is also provided to
1869 allow the kernel to be booted as an EFI application. This
1870 is only useful for kernels that may run on systems that have
1874 bool "Enable support for SMBIOS (DMI) tables"
1878 This enables SMBIOS/DMI feature for systems.
1880 This option is only useful on systems that have UEFI firmware.
1881 However, even with this option, the resultant kernel should
1882 continue to boot on existing non-UEFI platforms.
1884 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1885 i.e., the the practice of identifying the platform via DMI to
1886 decide whether certain workarounds for buggy hardware and/or
1887 firmware need to be enabled. This would require the DMI subsystem
1888 to be enabled much earlier than we do on ARM, which is non-trivial.
1892 menu "CPU Power Management"
1894 source "drivers/cpufreq/Kconfig"
1896 source "drivers/cpuidle/Kconfig"
1900 menu "Floating point emulation"
1902 comment "At least one emulation must be selected"
1905 bool "NWFPE math emulation"
1906 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1908 Say Y to include the NWFPE floating point emulator in the kernel.
1909 This is necessary to run most binaries. Linux does not currently
1910 support floating point hardware so you need to say Y here even if
1911 your machine has an FPA or floating point co-processor podule.
1913 You may say N here if you are going to load the Acorn FPEmulator
1914 early in the bootup.
1917 bool "Support extended precision"
1918 depends on FPE_NWFPE
1920 Say Y to include 80-bit support in the kernel floating-point
1921 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1922 Note that gcc does not generate 80-bit operations by default,
1923 so in most cases this option only enlarges the size of the
1924 floating point emulator without any good reason.
1926 You almost surely want to say N here.
1929 bool "FastFPE math emulation (EXPERIMENTAL)"
1930 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1932 Say Y here to include the FAST floating point emulator in the kernel.
1933 This is an experimental much faster emulator which now also has full
1934 precision for the mantissa. It does not support any exceptions.
1935 It is very simple, and approximately 3-6 times faster than NWFPE.
1937 It should be sufficient for most programs. It may be not suitable
1938 for scientific calculations, but you have to check this for yourself.
1939 If you do not feel you need a faster FP emulation you should better
1943 bool "VFP-format floating point maths"
1944 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1946 Say Y to include VFP support code in the kernel. This is needed
1947 if your hardware includes a VFP unit.
1949 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1950 release notes and additional status information.
1952 Say N if your target does not have VFP hardware.
1960 bool "Advanced SIMD (NEON) Extension support"
1961 depends on VFPv3 && CPU_V7
1963 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1966 config KERNEL_MODE_NEON
1967 bool "Support for NEON in kernel mode"
1968 depends on NEON && AEABI
1970 Say Y to include support for NEON in kernel mode.
1974 menu "Power management options"
1976 source "kernel/power/Kconfig"
1978 config ARCH_SUSPEND_POSSIBLE
1979 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1980 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1983 config ARM_CPU_SUSPEND
1984 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1985 depends on ARCH_SUSPEND_POSSIBLE
1987 config ARCH_HIBERNATION_POSSIBLE
1990 default y if ARCH_SUSPEND_POSSIBLE
1995 source "arch/arm/crypto/Kconfig"
1998 source "arch/arm/Kconfig.assembler"