1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_FORTIFY_SOURCE
14 select ARCH_HAS_KEEPINITRD
16 select ARCH_HAS_MEMBARRIER_SYNC_CORE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_PHYS_TO_DMA
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAS_GCOV_PROFILE_ALL
29 select ARCH_KEEP_MEMBLOCK
30 select ARCH_MIGHT_HAVE_PC_PARPORT
31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
34 select ARCH_SUPPORTS_ATOMIC_RMW
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
38 select ARCH_WANT_IPC_PARSE_VERSION
39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
40 select BUILDTIME_EXTABLE_SORT if MMU
41 select CLONE_BACKWARDS
42 select CPU_PM if SUSPEND || CPU_IDLE
43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
44 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_CPU_AUTOPROBE
53 select GENERIC_EARLY_IOREMAP
54 select GENERIC_IDLE_POLL_SETUP
55 select GENERIC_IRQ_PROBE
56 select GENERIC_IRQ_SHOW
57 select GENERIC_IRQ_SHOW_LEVEL
58 select GENERIC_PCI_IOMAP
59 select GENERIC_SCHED_CLOCK
60 select GENERIC_SMP_IDLE_THREAD
61 select GENERIC_STRNCPY_FROM_USER
62 select GENERIC_STRNLEN_USER
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_MMAP_RND_BITS if MMU
70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
72 select HAVE_ARCH_TRACEHOOK
73 select HAVE_ARM_SMCCC if CPU_V7
74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
75 select HAVE_CONTEXT_TRACKING
76 select HAVE_COPY_THREAD_TLS
77 select HAVE_C_RECORDMCOUNT
78 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
79 select HAVE_DMA_CONTIGUOUS if MMU
80 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
81 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
82 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
83 select HAVE_EXIT_THREAD
84 select HAVE_FAST_GUP if ARM_LPAE
85 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
86 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
87 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
88 select HAVE_FUTEX_CMPXCHG if FUTEX
89 select HAVE_GCC_PLUGINS
90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
91 select HAVE_IDE if PCI || ISA || PCMCIA
92 select HAVE_IRQ_TIME_ACCOUNTING
93 select HAVE_KERNEL_GZIP
94 select HAVE_KERNEL_LZ4
95 select HAVE_KERNEL_LZMA
96 select HAVE_KERNEL_LZO
98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
99 select HAVE_KRETPROBES if HAVE_KPROBES
100 select HAVE_MOD_ARCH_SPECIFIC
102 select HAVE_OPROFILE if HAVE_PERF_EVENTS
103 select HAVE_OPTPROBES if !THUMB2_KERNEL
104 select HAVE_PERF_EVENTS
105 select HAVE_PERF_REGS
106 select HAVE_PERF_USER_STACK_DUMP
107 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
108 select HAVE_REGS_AND_STACK_ACCESS_API
110 select HAVE_STACKPROTECTOR
111 select HAVE_SYSCALL_TRACEPOINTS
113 select HAVE_VIRT_CPU_ACCOUNTING_GEN
114 select IRQ_FORCED_THREADING
115 select MODULES_USE_ELF_REL
116 select NEED_DMA_MAP_STATE
117 select OF_EARLY_FLATTREE if OF
119 select OLD_SIGSUSPEND3
120 select PCI_SYSCALL if PCI
121 select PERF_USE_VMALLOC
123 select SYS_SUPPORTS_APM_EMULATION
124 # Above selects are sorted alphabetically; please add new ones
125 # according to that. Thanks.
127 The ARM series is a line of low-power-consumption RISC chip designs
128 licensed by ARM Ltd and targeted at embedded applications and
129 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
130 manufactured, but legacy ARM-based PC hardware remains popular in
131 Europe. There is an ARM Linux project with a web page at
132 <http://www.arm.linux.org.uk/>.
134 config ARM_HAS_SG_CHAIN
137 config ARM_DMA_USE_IOMMU
139 select ARM_HAS_SG_CHAIN
140 select NEED_SG_DMA_LENGTH
144 config ARM_DMA_IOMMU_ALIGNMENT
145 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
149 DMA mapping framework by default aligns all buffers to the smallest
150 PAGE_SIZE order which is greater than or equal to the requested buffer
151 size. This works well for buffers up to a few hundreds kilobytes, but
152 for larger buffers it just a waste of address space. Drivers which has
153 relatively small addressing window (like 64Mib) might run out of
154 virtual space with just a few allocations.
156 With this parameter you can specify the maximum PAGE_SIZE order for
157 DMA IOMMU buffers. Larger buffers will be aligned only to this
158 specified order. The order is expressed as a power of two multiplied
163 config SYS_SUPPORTS_APM_EMULATION
168 select GENERIC_ALLOCATOR
179 config STACKTRACE_SUPPORT
183 config LOCKDEP_SUPPORT
187 config TRACE_IRQFLAGS_SUPPORT
191 config ARCH_HAS_ILOG2_U32
194 config ARCH_HAS_ILOG2_U64
197 config ARCH_HAS_BANDGAP
200 config FIX_EARLYCON_MEM
203 config GENERIC_HWEIGHT
207 config GENERIC_CALIBRATE_DELAY
211 config ARCH_MAY_HAVE_PC_FDC
217 config ARCH_SUPPORTS_UPROBES
220 config ARCH_HAS_DMA_SET_COHERENT_MASK
223 config GENERIC_ISA_DMA
229 config NEED_RET_TO_USER
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_IO_H
254 Select this when mach/io.h is required to provide special
255 definitions for this platform. The need for mach/io.h should
256 be avoided when possible.
258 config NEED_MACH_MEMORY_H
261 Select this when mach/memory.h is required to provide special
262 definitions for this platform. The need for mach/memory.h should
263 be avoided when possible.
266 hex "Physical address of main memory" if MMU
267 depends on !ARM_PATCH_PHYS_VIRT
268 default DRAM_BASE if !MMU
269 default 0x00000000 if ARCH_EBSA110 || \
273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
274 default 0x20000000 if ARCH_S5PV210
275 default 0xc0000000 if ARCH_SA1100
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 config PGTABLE_LEVELS
286 default 3 if ARM_LPAE
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
298 config ARCH_MMAP_RND_BITS_MIN
301 config ARCH_MMAP_RND_BITS_MAX
302 default 14 if PAGE_OFFSET=0x40000000
303 default 15 if PAGE_OFFSET=0x80000000
307 # The "ARM system type" choice list is ordered alphabetically by option
308 # text. Please add new entries in the option alphabetic order.
311 prompt "ARM system type"
312 default ARM_SINGLE_ARMV7M if !MMU
313 default ARCH_MULTIPLATFORM if MMU
315 config ARCH_MULTIPLATFORM
316 bool "Allow multiple platforms to be selected"
318 select ARM_HAS_SG_CHAIN
319 select ARM_PATCH_PHYS_VIRT
323 select GENERIC_CLOCKEVENTS
324 select GENERIC_IRQ_MULTI_HANDLER
326 select PCI_DOMAINS_GENERIC if PCI
330 config ARM_SINGLE_ARMV7M
331 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
338 select GENERIC_CLOCKEVENTS
345 select ARCH_USES_GETTIMEOFFSET
348 select NEED_MACH_IO_H
349 select NEED_MACH_MEMORY_H
352 This is an evaluation board for the StrongARM processor available
353 from Digital. It has limited hardware on-board, including an
354 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_SPARSEMEM_ENABLE
361 imply ARM_PATCH_PHYS_VIRT
367 select GENERIC_CLOCKEVENTS
370 This enables support for the Cirrus EP93xx series of CPUs.
372 config ARCH_FOOTBRIDGE
376 select GENERIC_CLOCKEVENTS
378 select NEED_MACH_IO_H if !MMU
379 select NEED_MACH_MEMORY_H
381 Support for systems based on the DC21285 companion chip
382 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
390 select NEED_RET_TO_USER
394 Support for Intel's 80219 and IOP32X (XScale) family of
400 select ARCH_HAS_DMA_SET_COHERENT_MASK
401 select ARCH_SUPPORTS_BIG_ENDIAN
403 select DMABOUNCE if PCI
404 select GENERIC_CLOCKEVENTS
405 select GENERIC_IRQ_MULTI_HANDLER
411 select NEED_MACH_IO_H
412 select USB_EHCI_BIG_ENDIAN_DESC
413 select USB_EHCI_BIG_ENDIAN_MMIO
415 Support for Intel's IXP4XX (XScale) family of processors.
420 select GENERIC_CLOCKEVENTS
421 select GENERIC_IRQ_MULTI_HANDLER
427 select PLAT_ORION_LEGACY
429 select PM_GENERIC_DOMAINS if PM
431 Support for the Marvell Dove SoC 88AP510
434 bool "PXA2xx/PXA3xx-based"
437 select ARM_CPU_SUSPEND if PM
444 select CPU_XSCALE if !CPU_XSC3
445 select GENERIC_CLOCKEVENTS
446 select GENERIC_IRQ_MULTI_HANDLER
454 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
460 select ARCH_MAY_HAVE_PC_FDC
461 select ARCH_SPARSEMEM_ENABLE
462 select ARM_HAS_SG_CHAIN
466 select HAVE_PATA_PLATFORM
468 select NEED_MACH_IO_H
469 select NEED_MACH_MEMORY_H
472 On the Acorn Risc-PC, Linux can support the internal IDE disk and
473 CD-ROM interface, serial and parallel port, and the floppy drive.
478 select ARCH_SPARSEMEM_ENABLE
482 select TIMER_OF if OF
486 select GENERIC_CLOCKEVENTS
487 select GENERIC_IRQ_MULTI_HANDLER
492 select NEED_MACH_MEMORY_H
495 Support for StrongARM 11x0 based boards.
498 bool "Samsung S3C24XX SoCs"
501 select CLKSRC_SAMSUNG_PWM
502 select GENERIC_CLOCKEVENTS
505 select GENERIC_IRQ_MULTI_HANDLER
506 select HAVE_S3C2410_I2C if I2C
507 select HAVE_S3C2410_WATCHDOG if WATCHDOG
508 select HAVE_S3C_RTC if RTC_CLASS
509 select NEED_MACH_IO_H
510 select S3C2410_WATCHDOG
515 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
516 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
517 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
518 Samsung SMDK2410 development board (and derivatives).
526 select GENERIC_CLOCKEVENTS
527 select GENERIC_IRQ_CHIP
528 select GENERIC_IRQ_MULTI_HANDLER
532 select NEED_MACH_IO_H if PCCARD
533 select NEED_MACH_MEMORY_H
536 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
540 menu "Multiple platform selection"
541 depends on ARCH_MULTIPLATFORM
543 comment "CPU Core family selection"
546 bool "ARMv4 based platforms (FA526)"
547 depends on !ARCH_MULTI_V6_V7
548 select ARCH_MULTI_V4_V5
551 config ARCH_MULTI_V4T
552 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
553 depends on !ARCH_MULTI_V6_V7
554 select ARCH_MULTI_V4_V5
555 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
556 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
557 CPU_ARM925T || CPU_ARM940T)
560 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
561 depends on !ARCH_MULTI_V6_V7
562 select ARCH_MULTI_V4_V5
563 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
564 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
565 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
567 config ARCH_MULTI_V4_V5
571 bool "ARMv6 based platforms (ARM11)"
572 select ARCH_MULTI_V6_V7
576 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
578 select ARCH_MULTI_V6_V7
582 config ARCH_MULTI_V6_V7
584 select MIGHT_HAVE_CACHE_L2X0
586 config ARCH_MULTI_CPU_AUTO
587 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
593 bool "Dummy Virtual Machine"
594 depends on ARCH_MULTI_V7
597 select ARM_GIC_V2M if PCI
599 select ARM_GIC_V3_ITS if PCI
601 select HAVE_ARM_ARCH_TIMER
602 select ARCH_SUPPORTS_BIG_ENDIAN
605 # This is sorted alphabetically by mach-* pathname. However, plat-*
606 # Kconfigs may be included either alphabetically (according to the
607 # plat- suffix) or along side the corresponding mach-* source.
609 source "arch/arm/mach-actions/Kconfig"
611 source "arch/arm/mach-alpine/Kconfig"
613 source "arch/arm/mach-artpec/Kconfig"
615 source "arch/arm/mach-asm9260/Kconfig"
617 source "arch/arm/mach-aspeed/Kconfig"
619 source "arch/arm/mach-at91/Kconfig"
621 source "arch/arm/mach-axxia/Kconfig"
623 source "arch/arm/mach-bcm/Kconfig"
625 source "arch/arm/mach-berlin/Kconfig"
627 source "arch/arm/mach-clps711x/Kconfig"
629 source "arch/arm/mach-cns3xxx/Kconfig"
631 source "arch/arm/mach-davinci/Kconfig"
633 source "arch/arm/mach-digicolor/Kconfig"
635 source "arch/arm/mach-dove/Kconfig"
637 source "arch/arm/mach-ep93xx/Kconfig"
639 source "arch/arm/mach-exynos/Kconfig"
640 source "arch/arm/plat-samsung/Kconfig"
642 source "arch/arm/mach-footbridge/Kconfig"
644 source "arch/arm/mach-gemini/Kconfig"
646 source "arch/arm/mach-highbank/Kconfig"
648 source "arch/arm/mach-hisi/Kconfig"
650 source "arch/arm/mach-imx/Kconfig"
652 source "arch/arm/mach-integrator/Kconfig"
654 source "arch/arm/mach-iop32x/Kconfig"
656 source "arch/arm/mach-ixp4xx/Kconfig"
658 source "arch/arm/mach-keystone/Kconfig"
660 source "arch/arm/mach-lpc32xx/Kconfig"
662 source "arch/arm/mach-mediatek/Kconfig"
664 source "arch/arm/mach-meson/Kconfig"
666 source "arch/arm/mach-milbeaut/Kconfig"
668 source "arch/arm/mach-mmp/Kconfig"
670 source "arch/arm/mach-moxart/Kconfig"
672 source "arch/arm/mach-mv78xx0/Kconfig"
674 source "arch/arm/mach-mvebu/Kconfig"
676 source "arch/arm/mach-mxs/Kconfig"
678 source "arch/arm/mach-nomadik/Kconfig"
680 source "arch/arm/mach-npcm/Kconfig"
682 source "arch/arm/mach-nspire/Kconfig"
684 source "arch/arm/plat-omap/Kconfig"
686 source "arch/arm/mach-omap1/Kconfig"
688 source "arch/arm/mach-omap2/Kconfig"
690 source "arch/arm/mach-orion5x/Kconfig"
692 source "arch/arm/mach-oxnas/Kconfig"
694 source "arch/arm/mach-picoxcell/Kconfig"
696 source "arch/arm/mach-prima2/Kconfig"
698 source "arch/arm/mach-pxa/Kconfig"
699 source "arch/arm/plat-pxa/Kconfig"
701 source "arch/arm/mach-qcom/Kconfig"
703 source "arch/arm/mach-rda/Kconfig"
705 source "arch/arm/mach-realview/Kconfig"
707 source "arch/arm/mach-rockchip/Kconfig"
709 source "arch/arm/mach-s3c24xx/Kconfig"
711 source "arch/arm/mach-s3c64xx/Kconfig"
713 source "arch/arm/mach-s5pv210/Kconfig"
715 source "arch/arm/mach-sa1100/Kconfig"
717 source "arch/arm/mach-shmobile/Kconfig"
719 source "arch/arm/mach-socfpga/Kconfig"
721 source "arch/arm/mach-spear/Kconfig"
723 source "arch/arm/mach-sti/Kconfig"
725 source "arch/arm/mach-stm32/Kconfig"
727 source "arch/arm/mach-sunxi/Kconfig"
729 source "arch/arm/mach-tango/Kconfig"
731 source "arch/arm/mach-tegra/Kconfig"
733 source "arch/arm/mach-u300/Kconfig"
735 source "arch/arm/mach-uniphier/Kconfig"
737 source "arch/arm/mach-ux500/Kconfig"
739 source "arch/arm/mach-versatile/Kconfig"
741 source "arch/arm/mach-vexpress/Kconfig"
742 source "arch/arm/plat-versatile/Kconfig"
744 source "arch/arm/mach-vt8500/Kconfig"
746 source "arch/arm/mach-zx/Kconfig"
748 source "arch/arm/mach-zynq/Kconfig"
750 # ARMv7-M architecture
752 bool "Energy Micro efm32"
753 depends on ARM_SINGLE_ARMV7M
756 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
760 bool "NXP LPC18xx/LPC43xx"
761 depends on ARM_SINGLE_ARMV7M
762 select ARCH_HAS_RESET_CONTROLLER
764 select CLKSRC_LPC32XX
767 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
768 high performance microcontrollers.
771 bool "ARM MPS2 platform"
772 depends on ARM_SINGLE_ARMV7M
776 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
777 with a range of available cores like Cortex-M3/M4/M7.
779 Please, note that depends which Application Note is used memory map
780 for the platform may vary, so adjustment of RAM base might be needed.
782 # Definitions to make life easier
788 select GENERIC_CLOCKEVENTS
794 select GENERIC_IRQ_CHIP
797 config PLAT_ORION_LEGACY
804 config PLAT_VERSATILE
807 source "arch/arm/mm/Kconfig"
810 bool "Enable iWMMXt support"
811 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
812 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
814 Enable support for iWMMXt context switching at run time if
815 running on a CPU that supports it.
818 source "arch/arm/Kconfig-nommu"
821 config PJ4B_ERRATA_4742
822 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
823 depends on CPU_PJ4B && MACH_ARMADA_370
826 When coming out of either a Wait for Interrupt (WFI) or a Wait for
827 Event (WFE) IDLE states, a specific timing sensitivity exists between
828 the retiring WFI/WFE instructions and the newly issued subsequent
829 instructions. This sensitivity can result in a CPU hang scenario.
831 The software must insert either a Data Synchronization Barrier (DSB)
832 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
835 config ARM_ERRATA_326103
836 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
839 Executing a SWP instruction to read-only memory does not set bit 11
840 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
841 treat the access as a read, preventing a COW from occurring and
842 causing the faulting task to livelock.
844 config ARM_ERRATA_411920
845 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
846 depends on CPU_V6 || CPU_V6K
848 Invalidation of the Instruction Cache operation can
849 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
850 It does not affect the MPCore. This option enables the ARM Ltd.
851 recommended workaround.
853 config ARM_ERRATA_430973
854 bool "ARM errata: Stale prediction on replaced interworking branch"
857 This option enables the workaround for the 430973 Cortex-A8
858 r1p* erratum. If a code sequence containing an ARM/Thumb
859 interworking branch is replaced with another code sequence at the
860 same virtual address, whether due to self-modifying code or virtual
861 to physical address re-mapping, Cortex-A8 does not recover from the
862 stale interworking branch prediction. This results in Cortex-A8
863 executing the new code sequence in the incorrect ARM or Thumb state.
864 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
865 and also flushes the branch target cache at every context switch.
866 Note that setting specific bits in the ACTLR register may not be
867 available in non-secure mode.
869 config ARM_ERRATA_458693
870 bool "ARM errata: Processor deadlock when a false hazard is created"
872 depends on !ARCH_MULTIPLATFORM
874 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
875 erratum. For very specific sequences of memory operations, it is
876 possible for a hazard condition intended for a cache line to instead
877 be incorrectly associated with a different cache line. This false
878 hazard might then cause a processor deadlock. The workaround enables
879 the L1 caching of the NEON accesses and disables the PLD instruction
880 in the ACTLR register. Note that setting specific bits in the ACTLR
881 register may not be available in non-secure mode.
883 config ARM_ERRATA_460075
884 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
886 depends on !ARCH_MULTIPLATFORM
888 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
889 erratum. Any asynchronous access to the L2 cache may encounter a
890 situation in which recent store transactions to the L2 cache are lost
891 and overwritten with stale memory contents from external memory. The
892 workaround disables the write-allocate mode for the L2 cache via the
893 ACTLR register. Note that setting specific bits in the ACTLR register
894 may not be available in non-secure mode.
896 config ARM_ERRATA_742230
897 bool "ARM errata: DMB operation may be faulty"
898 depends on CPU_V7 && SMP
899 depends on !ARCH_MULTIPLATFORM
901 This option enables the workaround for the 742230 Cortex-A9
902 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
903 between two write operations may not ensure the correct visibility
904 ordering of the two writes. This workaround sets a specific bit in
905 the diagnostic register of the Cortex-A9 which causes the DMB
906 instruction to behave as a DSB, ensuring the correct behaviour of
909 config ARM_ERRATA_742231
910 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
911 depends on CPU_V7 && SMP
912 depends on !ARCH_MULTIPLATFORM
914 This option enables the workaround for the 742231 Cortex-A9
915 (r2p0..r2p2) erratum. Under certain conditions, specific to the
916 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
917 accessing some data located in the same cache line, may get corrupted
918 data due to bad handling of the address hazard when the line gets
919 replaced from one of the CPUs at the same time as another CPU is
920 accessing it. This workaround sets specific bits in the diagnostic
921 register of the Cortex-A9 which reduces the linefill issuing
922 capabilities of the processor.
924 config ARM_ERRATA_643719
925 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
926 depends on CPU_V7 && SMP
929 This option enables the workaround for the 643719 Cortex-A9 (prior to
930 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
931 register returns zero when it should return one. The workaround
932 corrects this value, ensuring cache maintenance operations which use
933 it behave as intended and avoiding data corruption.
935 config ARM_ERRATA_720789
936 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
939 This option enables the workaround for the 720789 Cortex-A9 (prior to
940 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
941 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
942 As a consequence of this erratum, some TLB entries which should be
943 invalidated are not, resulting in an incoherency in the system page
944 tables. The workaround changes the TLB flushing routines to invalidate
945 entries regardless of the ASID.
947 config ARM_ERRATA_743622
948 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
950 depends on !ARCH_MULTIPLATFORM
952 This option enables the workaround for the 743622 Cortex-A9
953 (r2p*) erratum. Under very rare conditions, a faulty
954 optimisation in the Cortex-A9 Store Buffer may lead to data
955 corruption. This workaround sets a specific bit in the diagnostic
956 register of the Cortex-A9 which disables the Store Buffer
957 optimisation, preventing the defect from occurring. This has no
958 visible impact on the overall performance or power consumption of the
961 config ARM_ERRATA_751472
962 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
964 depends on !ARCH_MULTIPLATFORM
966 This option enables the workaround for the 751472 Cortex-A9 (prior
967 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
968 completion of a following broadcasted operation if the second
969 operation is received by a CPU before the ICIALLUIS has completed,
970 potentially leading to corrupted entries in the cache or TLB.
972 config ARM_ERRATA_754322
973 bool "ARM errata: possible faulty MMU translations following an ASID switch"
976 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
977 r3p*) erratum. A speculative memory access may cause a page table walk
978 which starts prior to an ASID switch but completes afterwards. This
979 can populate the micro-TLB with a stale entry which may be hit with
980 the new ASID. This workaround places two dsb instructions in the mm
981 switching code so that no page table walks can cross the ASID switch.
983 config ARM_ERRATA_754327
984 bool "ARM errata: no automatic Store Buffer drain"
985 depends on CPU_V7 && SMP
987 This option enables the workaround for the 754327 Cortex-A9 (prior to
988 r2p0) erratum. The Store Buffer does not have any automatic draining
989 mechanism and therefore a livelock may occur if an external agent
990 continuously polls a memory location waiting to observe an update.
991 This workaround defines cpu_relax() as smp_mb(), preventing correctly
992 written polling loops from denying visibility of updates to memory.
994 config ARM_ERRATA_364296
995 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
998 This options enables the workaround for the 364296 ARM1136
999 r0p2 erratum (possible cache data corruption with
1000 hit-under-miss enabled). It sets the undocumented bit 31 in
1001 the auxiliary control register and the FI bit in the control
1002 register, thus disabling hit-under-miss without putting the
1003 processor into full low interrupt latency mode. ARM11MPCore
1006 config ARM_ERRATA_764369
1007 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1008 depends on CPU_V7 && SMP
1010 This option enables the workaround for erratum 764369
1011 affecting Cortex-A9 MPCore with two or more processors (all
1012 current revisions). Under certain timing circumstances, a data
1013 cache line maintenance operation by MVA targeting an Inner
1014 Shareable memory region may fail to proceed up to either the
1015 Point of Coherency or to the Point of Unification of the
1016 system. This workaround adds a DSB instruction before the
1017 relevant cache maintenance functions and sets a specific bit
1018 in the diagnostic control register of the SCU.
1020 config ARM_ERRATA_775420
1021 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1024 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1025 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1026 operation aborts with MMU exception, it might cause the processor
1027 to deadlock. This workaround puts DSB before executing ISB if
1028 an abort may occur on cache maintenance.
1030 config ARM_ERRATA_798181
1031 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1032 depends on CPU_V7 && SMP
1034 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1035 adequately shooting down all use of the old entries. This
1036 option enables the Linux kernel workaround for this erratum
1037 which sends an IPI to the CPUs that are running the same ASID
1038 as the one being invalidated.
1040 config ARM_ERRATA_773022
1041 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1044 This option enables the workaround for the 773022 Cortex-A15
1045 (up to r0p4) erratum. In certain rare sequences of code, the
1046 loop buffer may deliver incorrect instructions. This
1047 workaround disables the loop buffer to avoid the erratum.
1049 config ARM_ERRATA_818325_852422
1050 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1053 This option enables the workaround for:
1054 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1055 instruction might deadlock. Fixed in r0p1.
1056 - Cortex-A12 852422: Execution of a sequence of instructions might
1057 lead to either a data corruption or a CPU deadlock. Not fixed in
1058 any Cortex-A12 cores yet.
1059 This workaround for all both errata involves setting bit[12] of the
1060 Feature Register. This bit disables an optimisation applied to a
1061 sequence of 2 instructions that use opposing condition codes.
1063 config ARM_ERRATA_821420
1064 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1067 This option enables the workaround for the 821420 Cortex-A12
1068 (all revs) erratum. In very rare timing conditions, a sequence
1069 of VMOV to Core registers instructions, for which the second
1070 one is in the shadow of a branch or abort, can lead to a
1071 deadlock when the VMOV instructions are issued out-of-order.
1073 config ARM_ERRATA_825619
1074 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1077 This option enables the workaround for the 825619 Cortex-A12
1078 (all revs) erratum. Within rare timing constraints, executing a
1079 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1080 and Device/Strongly-Ordered loads and stores might cause deadlock
1082 config ARM_ERRATA_857271
1083 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1086 This option enables the workaround for the 857271 Cortex-A12
1087 (all revs) erratum. Under very rare timing conditions, the CPU might
1088 hang. The workaround is expected to have a < 1% performance impact.
1090 config ARM_ERRATA_852421
1091 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1094 This option enables the workaround for the 852421 Cortex-A17
1095 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1096 execution of a DMB ST instruction might fail to properly order
1097 stores from GroupA and stores from GroupB.
1099 config ARM_ERRATA_852423
1100 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1103 This option enables the workaround for:
1104 - Cortex-A17 852423: Execution of a sequence of instructions might
1105 lead to either a data corruption or a CPU deadlock. Not fixed in
1106 any Cortex-A17 cores yet.
1107 This is identical to Cortex-A12 erratum 852422. It is a separate
1108 config option from the A12 erratum due to the way errata are checked
1111 config ARM_ERRATA_857272
1112 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1115 This option enables the workaround for the 857272 Cortex-A17 erratum.
1116 This erratum is not known to be fixed in any A17 revision.
1117 This is identical to Cortex-A12 erratum 857271. It is a separate
1118 config option from the A12 erratum due to the way errata are checked
1123 source "arch/arm/common/Kconfig"
1130 Find out whether you have ISA slots on your motherboard. ISA is the
1131 name of a bus system, i.e. the way the CPU talks to the other stuff
1132 inside your box. Other bus systems are PCI, EISA, MicroChannel
1133 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1134 newer boards don't support it. If you have ISA, say Y, otherwise N.
1136 # Select ISA DMA controller support
1141 # Select ISA DMA interface
1145 config PCI_NANOENGINE
1146 bool "BSE nanoEngine PCI support"
1147 depends on SA1100_NANOENGINE
1149 Enable PCI on the BSE nanoEngine board.
1151 config PCI_HOST_ITE8152
1153 depends on PCI && MACH_ARMCORE
1157 config ARM_ERRATA_814220
1158 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1161 The v7 ARM states that all cache and branch predictor maintenance
1162 operations that do not specify an address execute, relative to
1163 each other, in program order.
1164 However, because of this erratum, an L2 set/way cache maintenance
1165 operation can overtake an L1 set/way cache maintenance operation.
1166 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1171 menu "Kernel Features"
1176 This option should be selected by machines which have an SMP-
1179 The only effect of this option is to make the SMP-related
1180 options available to the user for configuration.
1183 bool "Symmetric Multi-Processing"
1184 depends on CPU_V6K || CPU_V7
1185 depends on GENERIC_CLOCKEVENTS
1187 depends on MMU || ARM_MPU
1190 This enables support for systems with more than one CPU. If you have
1191 a system with only one CPU, say N. If you have a system with more
1192 than one CPU, say Y.
1194 If you say N here, the kernel will run on uni- and multiprocessor
1195 machines, but will use only one CPU of a multiprocessor machine. If
1196 you say Y here, the kernel will run on many, but not all,
1197 uniprocessor machines. On a uniprocessor machine, the kernel
1198 will run faster if you say N here.
1200 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1201 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1202 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1204 If you don't know what to do here, say N.
1207 bool "Allow booting SMP kernel on uniprocessor systems"
1208 depends on SMP && !XIP_KERNEL && MMU
1211 SMP kernels contain instructions which fail on non-SMP processors.
1212 Enabling this option allows the kernel to modify itself to make
1213 these instructions safe. Disabling it allows about 1K of space
1216 If you don't know what to do here, say Y.
1218 config ARM_CPU_TOPOLOGY
1219 bool "Support cpu topology definition"
1220 depends on SMP && CPU_V7
1223 Support ARM cpu topology definition. The MPIDR register defines
1224 affinity between processors which is then used to describe the cpu
1225 topology of an ARM System.
1228 bool "Multi-core scheduler support"
1229 depends on ARM_CPU_TOPOLOGY
1231 Multi-core scheduler support improves the CPU scheduler's decision
1232 making when dealing with multi-core CPU chips at a cost of slightly
1233 increased overhead in some places. If unsure say N here.
1236 bool "SMT scheduler support"
1237 depends on ARM_CPU_TOPOLOGY
1239 Improves the CPU scheduler's decision making when dealing with
1240 MultiThreading at a cost of slightly increased overhead in some
1241 places. If unsure say N here.
1246 This option enables support for the ARM snoop control unit
1248 config HAVE_ARM_ARCH_TIMER
1249 bool "Architected timer support"
1251 select ARM_ARCH_TIMER
1252 select GENERIC_CLOCKEVENTS
1254 This option enables support for the ARM architected timer
1259 This options enables support for the ARM timer and watchdog unit
1262 bool "Multi-Cluster Power Management"
1263 depends on CPU_V7 && SMP
1265 This option provides the common power management infrastructure
1266 for (multi-)cluster based systems, such as big.LITTLE based
1269 config MCPM_QUAD_CLUSTER
1273 To avoid wasting resources unnecessarily, MCPM only supports up
1274 to 2 clusters by default.
1275 Platforms with 3 or 4 clusters that use MCPM must select this
1276 option to allow the additional clusters to be managed.
1279 bool "big.LITTLE support (Experimental)"
1280 depends on CPU_V7 && SMP
1283 This option enables support selections for the big.LITTLE
1284 system architecture.
1287 bool "big.LITTLE switcher support"
1288 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1291 The big.LITTLE "switcher" provides the core functionality to
1292 transparently handle transition between a cluster of A15's
1293 and a cluster of A7's in a big.LITTLE system.
1295 config BL_SWITCHER_DUMMY_IF
1296 tristate "Simple big.LITTLE switcher user interface"
1297 depends on BL_SWITCHER && DEBUG_KERNEL
1299 This is a simple and dummy char dev interface to control
1300 the big.LITTLE switcher core code. It is meant for
1301 debugging purposes only.
1304 prompt "Memory split"
1308 Select the desired split between kernel and user memory.
1310 If you are not absolutely sure what you are doing, leave this
1314 bool "3G/1G user/kernel split"
1315 config VMSPLIT_3G_OPT
1316 depends on !ARM_LPAE
1317 bool "3G/1G user/kernel split (for full 1G low memory)"
1319 bool "2G/2G user/kernel split"
1321 bool "1G/3G user/kernel split"
1326 default PHYS_OFFSET if !MMU
1327 default 0x40000000 if VMSPLIT_1G
1328 default 0x80000000 if VMSPLIT_2G
1329 default 0xB0000000 if VMSPLIT_3G_OPT
1333 int "Maximum number of CPUs (2-32)"
1339 bool "Support for hot-pluggable CPUs"
1341 select GENERIC_IRQ_MIGRATION
1343 Say Y here to experiment with turning CPUs off and on. CPUs
1344 can be controlled through /sys/devices/system/cpu.
1347 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1348 depends on HAVE_ARM_SMCCC
1351 Say Y here if you want Linux to communicate with system firmware
1352 implementing the PSCI specification for CPU-centric power
1353 management operations described in ARM document number ARM DEN
1354 0022A ("Power State Coordination Interface System Software on
1357 # The GPIO number here must be sorted by descending number. In case of
1358 # a multiplatform kernel, we just want the highest value required by the
1359 # selected platforms.
1362 default 2048 if ARCH_SOCFPGA
1363 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1365 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1366 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1367 default 416 if ARCH_SUNXI
1368 default 392 if ARCH_U8500
1369 default 352 if ARCH_VT8500
1370 default 288 if ARCH_ROCKCHIP
1371 default 264 if MACH_H4700
1374 Maximum number of GPIOs in the system.
1376 If unsure, leave the default value.
1380 default 200 if ARCH_EBSA110
1381 default 128 if SOC_AT91RM9200
1385 depends on HZ_FIXED = 0
1386 prompt "Timer frequency"
1410 default HZ_FIXED if HZ_FIXED != 0
1411 default 100 if HZ_100
1412 default 200 if HZ_200
1413 default 250 if HZ_250
1414 default 300 if HZ_300
1415 default 500 if HZ_500
1419 def_bool HIGH_RES_TIMERS
1421 config THUMB2_KERNEL
1422 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1423 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1424 default y if CPU_THUMBONLY
1427 By enabling this option, the kernel will be compiled in
1432 config THUMB2_AVOID_R_ARM_THM_JUMP11
1433 bool "Work around buggy Thumb-2 short branch relocations in gas"
1434 depends on THUMB2_KERNEL && MODULES
1437 Various binutils versions can resolve Thumb-2 branches to
1438 locally-defined, preemptible global symbols as short-range "b.n"
1439 branch instructions.
1441 This is a problem, because there's no guarantee the final
1442 destination of the symbol, or any candidate locations for a
1443 trampoline, are within range of the branch. For this reason, the
1444 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1445 relocation in modules at all, and it makes little sense to add
1448 The symptom is that the kernel fails with an "unsupported
1449 relocation" error when loading some modules.
1451 Until fixed tools are available, passing
1452 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1453 code which hits this problem, at the cost of a bit of extra runtime
1454 stack usage in some cases.
1456 The problem is described in more detail at:
1457 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1459 Only Thumb-2 kernels are affected.
1461 Unless you are sure your tools don't have this problem, say Y.
1463 config ARM_PATCH_IDIV
1464 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1465 depends on CPU_32v7 && !XIP_KERNEL
1468 The ARM compiler inserts calls to __aeabi_idiv() and
1469 __aeabi_uidiv() when it needs to perform division on signed
1470 and unsigned integers. Some v7 CPUs have support for the sdiv
1471 and udiv instructions that can be used to implement those
1474 Enabling this option allows the kernel to modify itself to
1475 replace the first two instructions of these library functions
1476 with the sdiv or udiv plus "bx lr" instructions when the CPU
1477 it is running on supports them. Typically this will be faster
1478 and less power intensive than running the original library
1479 code to do integer division.
1482 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1483 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1484 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1486 This option allows for the kernel to be compiled using the latest
1487 ARM ABI (aka EABI). This is only useful if you are using a user
1488 space environment that is also compiled with EABI.
1490 Since there are major incompatibilities between the legacy ABI and
1491 EABI, especially with regard to structure member alignment, this
1492 option also changes the kernel syscall calling convention to
1493 disambiguate both ABIs and allow for backward compatibility support
1494 (selected with CONFIG_OABI_COMPAT).
1496 To use this you need GCC version 4.0.0 or later.
1499 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1500 depends on AEABI && !THUMB2_KERNEL
1502 This option preserves the old syscall interface along with the
1503 new (ARM EABI) one. It also provides a compatibility layer to
1504 intercept syscalls that have structure arguments which layout
1505 in memory differs between the legacy ABI and the new ARM EABI
1506 (only for non "thumb" binaries). This option adds a tiny
1507 overhead to all syscalls and produces a slightly larger kernel.
1509 The seccomp filter system will not be available when this is
1510 selected, since there is no way yet to sensibly distinguish
1511 between calling conventions during filtering.
1513 If you know you'll be using only pure EABI user space then you
1514 can say N here. If this option is not selected and you attempt
1515 to execute a legacy ABI binary then the result will be
1516 UNPREDICTABLE (in fact it can be predicted that it won't work
1517 at all). If in doubt say N.
1519 config ARCH_SPARSEMEM_ENABLE
1522 config ARCH_SPARSEMEM_DEFAULT
1523 def_bool ARCH_SPARSEMEM_ENABLE
1525 config HAVE_ARCH_PFN_VALID
1529 bool "High Memory Support"
1532 The address space of ARM processors is only 4 Gigabytes large
1533 and it has to accommodate user address space, kernel address
1534 space as well as some memory mapped IO. That means that, if you
1535 have a large amount of physical memory and/or IO, not all of the
1536 memory can be "permanently mapped" by the kernel. The physical
1537 memory that is not permanently mapped is called "high memory".
1539 Depending on the selected kernel/user memory split, minimum
1540 vmalloc space and actual amount of RAM, you may not need this
1541 option which should result in a slightly faster kernel.
1546 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1550 The VM uses one page of physical memory for each page table.
1551 For systems with a lot of processes, this can use a lot of
1552 precious low memory, eventually leading to low memory being
1553 consumed by page tables. Setting this option will allow
1554 user-space 2nd level page tables to reside in high memory.
1556 config CPU_SW_DOMAIN_PAN
1557 bool "Enable use of CPU domains to implement privileged no-access"
1558 depends on MMU && !ARM_LPAE
1561 Increase kernel security by ensuring that normal kernel accesses
1562 are unable to access userspace addresses. This can help prevent
1563 use-after-free bugs becoming an exploitable privilege escalation
1564 by ensuring that magic values (such as LIST_POISON) will always
1565 fault when dereferenced.
1567 CPUs with low-vector mappings use a best-efforts implementation.
1568 Their lower 1MB needs to remain accessible for the vectors, but
1569 the remainder of userspace will become appropriately inaccessible.
1571 config HW_PERF_EVENTS
1575 config SYS_SUPPORTS_HUGETLBFS
1579 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1583 config ARCH_WANT_GENERAL_HUGETLB
1586 config ARM_MODULE_PLTS
1587 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1591 Allocate PLTs when loading modules so that jumps and calls whose
1592 targets are too far away for their relative offsets to be encoded
1593 in the instructions themselves can be bounced via veneers in the
1594 module's PLT. This allows modules to be allocated in the generic
1595 vmalloc area after the dedicated module memory area has been
1596 exhausted. The modules will use slightly more memory, but after
1597 rounding up to page size, the actual memory footprint is usually
1600 Disabling this is usually safe for small single-platform
1601 configurations. If unsure, say y.
1603 config FORCE_MAX_ZONEORDER
1604 int "Maximum zone order"
1605 default "12" if SOC_AM33XX
1606 default "9" if SA1111 || ARCH_EFM32
1609 The kernel memory allocator divides physically contiguous memory
1610 blocks into "zones", where each zone is a power of two number of
1611 pages. This option selects the largest power of two that the kernel
1612 keeps in the memory allocator. If you need to allocate very large
1613 blocks of physically contiguous memory, then you may need to
1614 increase this value.
1616 This config option is actually maximum order plus one. For example,
1617 a value of 11 means that the largest free memory block is 2^10 pages.
1619 config ALIGNMENT_TRAP
1621 depends on CPU_CP15_MMU
1622 default y if !ARCH_EBSA110
1623 select HAVE_PROC_CPU if PROC_FS
1625 ARM processors cannot fetch/store information which is not
1626 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1627 address divisible by 4. On 32-bit ARM processors, these non-aligned
1628 fetch/store instructions will be emulated in software if you say
1629 here, which has a severe performance impact. This is necessary for
1630 correct operation of some network protocols. With an IP-only
1631 configuration it is safe to say N, otherwise say Y.
1633 config UACCESS_WITH_MEMCPY
1634 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1636 default y if CPU_FEROCEON
1638 Implement faster copy_to_user and clear_user methods for CPU
1639 cores where a 8-word STM instruction give significantly higher
1640 memory write throughput than a sequence of individual 32bit stores.
1642 A possible side effect is a slight increase in scheduling latency
1643 between threads sharing the same address space if they invoke
1644 such copy operations with large buffers.
1646 However, if the CPU data cache is using a write-allocate mode,
1647 this option is unlikely to provide any performance gain.
1651 prompt "Enable seccomp to safely compute untrusted bytecode"
1653 This kernel feature is useful for number crunching applications
1654 that may need to compute untrusted bytecode during their
1655 execution. By using pipes or other transports made available to
1656 the process as file descriptors supporting the read/write
1657 syscalls, it's possible to isolate those applications in
1658 their own address space using seccomp. Once seccomp is
1659 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1660 and the task is only allowed to execute a few safe syscalls
1661 defined by each seccomp mode.
1664 bool "Enable paravirtualization code"
1666 This changes the kernel so it can modify itself when it is run
1667 under a hypervisor, potentially improving performance significantly
1668 over full virtualization.
1670 config PARAVIRT_TIME_ACCOUNTING
1671 bool "Paravirtual steal time accounting"
1674 Select this option to enable fine granularity task steal time
1675 accounting. Time spent executing other tasks in parallel with
1676 the current vCPU is discounted from the vCPU power. To account for
1677 that, there can be a small performance impact.
1679 If in doubt, say N here.
1686 bool "Xen guest support on ARM"
1687 depends on ARM && AEABI && OF
1688 depends on CPU_V7 && !CPU_V6
1689 depends on !GENERIC_ATOMIC64
1691 select ARCH_DMA_ADDR_T_64BIT
1697 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1699 config STACKPROTECTOR_PER_TASK
1700 bool "Use a unique stack canary value for each task"
1701 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1702 select GCC_PLUGIN_ARM_SSP_PER_TASK
1705 Due to the fact that GCC uses an ordinary symbol reference from
1706 which to load the value of the stack canary, this value can only
1707 change at reboot time on SMP systems, and all tasks running in the
1708 kernel's address space are forced to use the same canary value for
1709 the entire duration that the system is up.
1711 Enable this option to switch to a different method that uses a
1712 different canary value for each task.
1719 bool "Flattened Device Tree support"
1723 Include support for flattened device tree machine descriptions.
1726 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1729 This is the traditional way of passing data to the kernel at boot
1730 time. If you are solely relying on the flattened device tree (or
1731 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1732 to remove ATAGS support from your kernel binary. If unsure,
1735 config DEPRECATED_PARAM_STRUCT
1736 bool "Provide old way to pass kernel parameters"
1739 This was deprecated in 2001 and announced to live on for 5 years.
1740 Some old boot loaders still use this way.
1742 # Compressed boot loader in ROM. Yes, we really want to ask about
1743 # TEXT and BSS so we preserve their values in the config files.
1744 config ZBOOT_ROM_TEXT
1745 hex "Compressed ROM boot loader base address"
1748 The physical address at which the ROM-able zImage is to be
1749 placed in the target. Platforms which normally make use of
1750 ROM-able zImage formats normally set this to a suitable
1751 value in their defconfig file.
1753 If ZBOOT_ROM is not enabled, this has no effect.
1755 config ZBOOT_ROM_BSS
1756 hex "Compressed ROM boot loader BSS address"
1759 The base address of an area of read/write memory in the target
1760 for the ROM-able zImage which must be available while the
1761 decompressor is running. It must be large enough to hold the
1762 entire decompressed kernel plus an additional 128 KiB.
1763 Platforms which normally make use of ROM-able zImage formats
1764 normally set this to a suitable value in their defconfig file.
1766 If ZBOOT_ROM is not enabled, this has no effect.
1769 bool "Compressed boot loader in ROM/flash"
1770 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1771 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1773 Say Y here if you intend to execute your compressed kernel image
1774 (zImage) directly from ROM or flash. If unsure, say N.
1776 config ARM_APPENDED_DTB
1777 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1780 With this option, the boot code will look for a device tree binary
1781 (DTB) appended to zImage
1782 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1784 This is meant as a backward compatibility convenience for those
1785 systems with a bootloader that can't be upgraded to accommodate
1786 the documented boot protocol using a device tree.
1788 Beware that there is very little in terms of protection against
1789 this option being confused by leftover garbage in memory that might
1790 look like a DTB header after a reboot if no actual DTB is appended
1791 to zImage. Do not leave this option active in a production kernel
1792 if you don't intend to always append a DTB. Proper passing of the
1793 location into r2 of a bootloader provided DTB is always preferable
1796 config ARM_ATAG_DTB_COMPAT
1797 bool "Supplement the appended DTB with traditional ATAG information"
1798 depends on ARM_APPENDED_DTB
1800 Some old bootloaders can't be updated to a DTB capable one, yet
1801 they provide ATAGs with memory configuration, the ramdisk address,
1802 the kernel cmdline string, etc. Such information is dynamically
1803 provided by the bootloader and can't always be stored in a static
1804 DTB. To allow a device tree enabled kernel to be used with such
1805 bootloaders, this option allows zImage to extract the information
1806 from the ATAG list and store it at run time into the appended DTB.
1809 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1810 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1812 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1813 bool "Use bootloader kernel arguments if available"
1815 Uses the command-line options passed by the boot loader instead of
1816 the device tree bootargs property. If the boot loader doesn't provide
1817 any, the device tree bootargs property will be used.
1819 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1820 bool "Extend with bootloader kernel arguments"
1822 The command-line arguments provided by the boot loader will be
1823 appended to the the device tree bootargs property.
1828 string "Default kernel command string"
1831 On some architectures (EBSA110 and CATS), there is currently no way
1832 for the boot loader to pass arguments to the kernel. For these
1833 architectures, you should supply some command-line options at build
1834 time by entering them here. As a minimum, you should specify the
1835 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1838 prompt "Kernel command line type" if CMDLINE != ""
1839 default CMDLINE_FROM_BOOTLOADER
1841 config CMDLINE_FROM_BOOTLOADER
1842 bool "Use bootloader kernel arguments if available"
1844 Uses the command-line options passed by the boot loader. If
1845 the boot loader doesn't provide any, the default kernel command
1846 string provided in CMDLINE will be used.
1848 config CMDLINE_EXTEND
1849 bool "Extend bootloader kernel arguments"
1851 The command-line arguments provided by the boot loader will be
1852 appended to the default kernel command string.
1854 config CMDLINE_FORCE
1855 bool "Always use the default kernel command string"
1857 Always use the default kernel command string, even if the boot
1858 loader passes other arguments to the kernel.
1859 This is useful if you cannot or don't want to change the
1860 command-line options your boot loader passes to the kernel.
1864 bool "Kernel Execute-In-Place from ROM"
1865 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1867 Execute-In-Place allows the kernel to run from non-volatile storage
1868 directly addressable by the CPU, such as NOR flash. This saves RAM
1869 space since the text section of the kernel is not loaded from flash
1870 to RAM. Read-write sections, such as the data section and stack,
1871 are still copied to RAM. The XIP kernel is not compressed since
1872 it has to run directly from flash, so it will take more space to
1873 store it. The flash address used to link the kernel object files,
1874 and for storing it, is configuration dependent. Therefore, if you
1875 say Y here, you must know the proper physical address where to
1876 store the kernel image depending on your own flash memory usage.
1878 Also note that the make target becomes "make xipImage" rather than
1879 "make zImage" or "make Image". The final kernel binary to put in
1880 ROM memory will be arch/arm/boot/xipImage.
1884 config XIP_PHYS_ADDR
1885 hex "XIP Kernel Physical Location"
1886 depends on XIP_KERNEL
1887 default "0x00080000"
1889 This is the physical address in your flash memory the kernel will
1890 be linked for and stored to. This address is dependent on your
1893 config XIP_DEFLATED_DATA
1894 bool "Store kernel .data section compressed in ROM"
1895 depends on XIP_KERNEL
1898 Before the kernel is actually executed, its .data section has to be
1899 copied to RAM from ROM. This option allows for storing that data
1900 in compressed form and decompressed to RAM rather than merely being
1901 copied, saving some precious ROM space. A possible drawback is a
1902 slightly longer boot delay.
1905 bool "Kexec system call (EXPERIMENTAL)"
1906 depends on (!SMP || PM_SLEEP_SMP)
1910 kexec is a system call that implements the ability to shutdown your
1911 current kernel, and to start another kernel. It is like a reboot
1912 but it is independent of the system firmware. And like a reboot
1913 you can start any kernel with it, not just Linux.
1915 It is an ongoing process to be certain the hardware in a machine
1916 is properly shutdown, so do not be surprised if this code does not
1917 initially work for you.
1920 bool "Export atags in procfs"
1921 depends on ATAGS && KEXEC
1924 Should the atags used to boot the kernel be exported in an "atags"
1925 file in procfs. Useful with kexec.
1928 bool "Build kdump crash kernel (EXPERIMENTAL)"
1930 Generate crash dump after being started by kexec. This should
1931 be normally only set in special crash dump kernels which are
1932 loaded in the main kernel with kexec-tools into a specially
1933 reserved region and then later executed after a crash by
1934 kdump/kexec. The crash dump kernel must be compiled to a
1935 memory address not used by the main kernel
1937 For more details see Documentation/admin-guide/kdump/kdump.rst
1939 config AUTO_ZRELADDR
1940 bool "Auto calculation of the decompressed kernel image address"
1942 ZRELADDR is the physical address where the decompressed kernel
1943 image will be placed. If AUTO_ZRELADDR is selected, the address
1944 will be determined at run-time by masking the current IP with
1945 0xf8000000. This assumes the zImage being placed in the first 128MB
1946 from start of memory.
1952 bool "UEFI runtime support"
1953 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1955 select EFI_PARAMS_FROM_FDT
1958 select EFI_RUNTIME_WRAPPERS
1960 This option provides support for runtime services provided
1961 by UEFI firmware (such as non-volatile variables, realtime
1962 clock, and platform reset). A UEFI stub is also provided to
1963 allow the kernel to be booted as an EFI application. This
1964 is only useful for kernels that may run on systems that have
1968 bool "Enable support for SMBIOS (DMI) tables"
1972 This enables SMBIOS/DMI feature for systems.
1974 This option is only useful on systems that have UEFI firmware.
1975 However, even with this option, the resultant kernel should
1976 continue to boot on existing non-UEFI platforms.
1978 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1979 i.e., the the practice of identifying the platform via DMI to
1980 decide whether certain workarounds for buggy hardware and/or
1981 firmware need to be enabled. This would require the DMI subsystem
1982 to be enabled much earlier than we do on ARM, which is non-trivial.
1986 menu "CPU Power Management"
1988 source "drivers/cpufreq/Kconfig"
1990 source "drivers/cpuidle/Kconfig"
1994 menu "Floating point emulation"
1996 comment "At least one emulation must be selected"
1999 bool "NWFPE math emulation"
2000 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2002 Say Y to include the NWFPE floating point emulator in the kernel.
2003 This is necessary to run most binaries. Linux does not currently
2004 support floating point hardware so you need to say Y here even if
2005 your machine has an FPA or floating point co-processor podule.
2007 You may say N here if you are going to load the Acorn FPEmulator
2008 early in the bootup.
2011 bool "Support extended precision"
2012 depends on FPE_NWFPE
2014 Say Y to include 80-bit support in the kernel floating-point
2015 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2016 Note that gcc does not generate 80-bit operations by default,
2017 so in most cases this option only enlarges the size of the
2018 floating point emulator without any good reason.
2020 You almost surely want to say N here.
2023 bool "FastFPE math emulation (EXPERIMENTAL)"
2024 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2026 Say Y here to include the FAST floating point emulator in the kernel.
2027 This is an experimental much faster emulator which now also has full
2028 precision for the mantissa. It does not support any exceptions.
2029 It is very simple, and approximately 3-6 times faster than NWFPE.
2031 It should be sufficient for most programs. It may be not suitable
2032 for scientific calculations, but you have to check this for yourself.
2033 If you do not feel you need a faster FP emulation you should better
2037 bool "VFP-format floating point maths"
2038 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2040 Say Y to include VFP support code in the kernel. This is needed
2041 if your hardware includes a VFP unit.
2043 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2044 release notes and additional status information.
2046 Say N if your target does not have VFP hardware.
2054 bool "Advanced SIMD (NEON) Extension support"
2055 depends on VFPv3 && CPU_V7
2057 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2060 config KERNEL_MODE_NEON
2061 bool "Support for NEON in kernel mode"
2062 depends on NEON && AEABI
2064 Say Y to include support for NEON in kernel mode.
2068 menu "Power management options"
2070 source "kernel/power/Kconfig"
2072 config ARCH_SUSPEND_POSSIBLE
2073 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2074 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2077 config ARM_CPU_SUSPEND
2078 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2079 depends on ARCH_SUSPEND_POSSIBLE
2081 config ARCH_HIBERNATION_POSSIBLE
2084 default y if ARCH_SUSPEND_POSSIBLE
2088 source "drivers/firmware/Kconfig"
2091 source "arch/arm/crypto/Kconfig"
2094 source "arch/arm/kvm/Kconfig"