1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
15 select ARCH_HAS_PHYS_TO_DMA
16 select ARCH_HAS_SET_MEMORY
17 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
18 select ARCH_HAS_STRICT_MODULE_RWX if MMU
19 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
20 select ARCH_HAVE_CUSTOM_GPIO_H
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_MIGHT_HAVE_PC_PARPORT
23 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
24 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
25 select ARCH_SUPPORTS_ATOMIC_RMW
26 select ARCH_USE_BUILTIN_BSWAP
27 select ARCH_USE_CMPXCHG_LOCKREF
28 select ARCH_WANT_IPC_PARSE_VERSION
29 select BUILDTIME_EXTABLE_SORT if MMU
30 select CLONE_BACKWARDS
31 select CPU_PM if (SUSPEND || CPU_IDLE)
32 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
33 select DMA_DIRECT_OPS if !MMU
35 select EDAC_ATOMIC_SCRUB
36 select GENERIC_ALLOCATOR
37 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
38 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
39 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
40 select GENERIC_CPU_AUTOPROBE
41 select GENERIC_EARLY_IOREMAP
42 select GENERIC_IDLE_POLL_SETUP
43 select GENERIC_IRQ_PROBE
44 select GENERIC_IRQ_SHOW
45 select GENERIC_IRQ_SHOW_LEVEL
46 select GENERIC_PCI_IOMAP
47 select GENERIC_SCHED_CLOCK
48 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select HANDLE_DOMAIN_IRQ
52 select HARDIRQS_SW_RESEND
53 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
54 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
55 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
56 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
57 select HAVE_ARCH_MMAP_RND_BITS if MMU
58 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
59 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
60 select HAVE_ARCH_TRACEHOOK
61 select HAVE_ARM_SMCCC if CPU_V7
62 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
63 select HAVE_CONTEXT_TRACKING
64 select HAVE_C_RECORDMCOUNT
65 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
66 select HAVE_DMA_CONTIGUOUS if MMU
67 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
68 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
69 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
70 select HAVE_EXIT_THREAD
71 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
72 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL && !CC_IS_CLANG)
73 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
74 select HAVE_FUTEX_CMPXCHG if FUTEX
75 select HAVE_GCC_PLUGINS
76 select HAVE_GENERIC_DMA_COHERENT
77 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
78 select HAVE_IDE if PCI || ISA || PCMCIA
79 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_KERNEL_GZIP
81 select HAVE_KERNEL_LZ4
82 select HAVE_KERNEL_LZMA
83 select HAVE_KERNEL_LZO
85 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
86 select HAVE_KRETPROBES if (HAVE_KPROBES)
88 select HAVE_MOD_ARCH_SPECIFIC
90 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
91 select HAVE_OPTPROBES if !THUMB2_KERNEL
92 select HAVE_PERF_EVENTS
94 select HAVE_PERF_USER_STACK_DUMP
95 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
96 select HAVE_REGS_AND_STACK_ACCESS_API
98 select HAVE_STACKPROTECTOR
99 select HAVE_SYSCALL_TRACEPOINTS
101 select HAVE_VIRT_CPU_ACCOUNTING_GEN
102 select IRQ_FORCED_THREADING
103 select MODULES_USE_ELF_REL
104 select NEED_DMA_MAP_STATE
106 select OF_EARLY_FLATTREE if OF
107 select OF_RESERVED_MEM if OF
109 select OLD_SIGSUSPEND3
110 select PERF_USE_VMALLOC
113 select SYS_SUPPORTS_APM_EMULATION
114 # Above selects are sorted alphabetically; please add new ones
115 # according to that. Thanks.
117 The ARM series is a line of low-power-consumption RISC chip designs
118 licensed by ARM Ltd and targeted at embedded applications and
119 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
120 manufactured, but legacy ARM-based PC hardware remains popular in
121 Europe. There is an ARM Linux project with a web page at
122 <http://www.arm.linux.org.uk/>.
124 config ARM_HAS_SG_CHAIN
125 select ARCH_HAS_SG_CHAIN
128 config ARM_DMA_USE_IOMMU
130 select ARM_HAS_SG_CHAIN
131 select NEED_SG_DMA_LENGTH
135 config ARM_DMA_IOMMU_ALIGNMENT
136 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
140 DMA mapping framework by default aligns all buffers to the smallest
141 PAGE_SIZE order which is greater than or equal to the requested buffer
142 size. This works well for buffers up to a few hundreds kilobytes, but
143 for larger buffers it just a waste of address space. Drivers which has
144 relatively small addressing window (like 64Mib) might run out of
145 virtual space with just a few allocations.
147 With this parameter you can specify the maximum PAGE_SIZE order for
148 DMA IOMMU buffers. Larger buffers will be aligned only to this
149 specified order. The order is expressed as a power of two multiplied
154 config MIGHT_HAVE_PCI
157 config SYS_SUPPORTS_APM_EMULATION
162 select GENERIC_ALLOCATOR
173 The Extended Industry Standard Architecture (EISA) bus was
174 developed as an open alternative to the IBM MicroChannel bus.
176 The EISA bus provided some of the features of the IBM MicroChannel
177 bus while maintaining backward compatibility with cards made for
178 the older ISA bus. The EISA bus saw limited use between 1988 and
179 1995 when it was made obsolete by the PCI bus.
181 Say Y here if you are building a kernel for an EISA-based machine.
188 config STACKTRACE_SUPPORT
192 config LOCKDEP_SUPPORT
196 config TRACE_IRQFLAGS_SUPPORT
200 config RWSEM_XCHGADD_ALGORITHM
204 config ARCH_HAS_ILOG2_U32
207 config ARCH_HAS_ILOG2_U64
210 config ARCH_HAS_BANDGAP
213 config FIX_EARLYCON_MEM
216 config GENERIC_HWEIGHT
220 config GENERIC_CALIBRATE_DELAY
224 config ARCH_MAY_HAVE_PC_FDC
230 config ARCH_SUPPORTS_UPROBES
233 config ARCH_HAS_DMA_SET_COHERENT_MASK
236 config GENERIC_ISA_DMA
242 config NEED_RET_TO_USER
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
251 depends on !XIP_KERNEL && MMU
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 16MB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_EBSA110 || \
288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
289 default 0x20000000 if ARCH_S5PV210
290 default 0xc0000000 if ARCH_SA1100
292 Please provide the physical address corresponding to the
293 location of main memory in your system.
299 config PGTABLE_LEVELS
301 default 3 if ARM_LPAE
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
313 config ARCH_MMAP_RND_BITS_MIN
316 config ARCH_MMAP_RND_BITS_MAX
317 default 14 if PAGE_OFFSET=0x40000000
318 default 15 if PAGE_OFFSET=0x80000000
322 # The "ARM system type" choice list is ordered alphabetically by option
323 # text. Please add new entries in the option alphabetic order.
326 prompt "ARM system type"
327 default ARM_SINGLE_ARMV7M if !MMU
328 default ARCH_MULTIPLATFORM if MMU
330 config ARCH_MULTIPLATFORM
331 bool "Allow multiple platforms to be selected"
333 select ARM_HAS_SG_CHAIN
334 select ARM_PATCH_PHYS_VIRT
338 select GENERIC_CLOCKEVENTS
339 select GENERIC_IRQ_MULTI_HANDLER
340 select MIGHT_HAVE_PCI
341 select PCI_DOMAINS if PCI
345 config ARM_SINGLE_ARMV7M
346 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
353 select GENERIC_CLOCKEVENTS
360 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_IO_H
364 select NEED_MACH_MEMORY_H
367 This is an evaluation board for the StrongARM processor available
368 from Digital. It has limited hardware on-board, including an
369 Ethernet interface, two PCMCIA sockets, two serial ports and a
374 select ARCH_SPARSEMEM_ENABLE
376 imply ARM_PATCH_PHYS_VIRT
382 select GENERIC_CLOCKEVENTS
385 This enables support for the Cirrus EP93xx series of CPUs.
387 config ARCH_FOOTBRIDGE
391 select GENERIC_CLOCKEVENTS
393 select NEED_MACH_IO_H if !MMU
394 select NEED_MACH_MEMORY_H
396 Support for systems based on the DC21285 companion chip
397 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
400 bool "Hilscher NetX based"
404 select GENERIC_CLOCKEVENTS
406 This enables support for systems based on the Hilscher NetX Soc
412 select NEED_MACH_MEMORY_H
413 select NEED_RET_TO_USER
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select NEED_RET_TO_USER
431 Support for Intel's 80219 and IOP32X (XScale) family of
440 select NEED_RET_TO_USER
444 Support for Intel's IOP33X (XScale) family of processors.
449 select ARCH_HAS_DMA_SET_COHERENT_MASK
450 select ARCH_SUPPORTS_BIG_ENDIAN
453 select DMABOUNCE if PCI
454 select GENERIC_CLOCKEVENTS
456 select MIGHT_HAVE_PCI
457 select NEED_MACH_IO_H
458 select USB_EHCI_BIG_ENDIAN_DESC
459 select USB_EHCI_BIG_ENDIAN_MMIO
461 Support for Intel's IXP4XX (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select GENERIC_IRQ_MULTI_HANDLER
469 select MIGHT_HAVE_PCI
473 select PLAT_ORION_LEGACY
475 select PM_GENERIC_DOMAINS if PM
477 Support for the Marvell Dove SoC 88AP510
480 bool "Micrel/Kendin KS8695"
483 select GENERIC_CLOCKEVENTS
485 select NEED_MACH_MEMORY_H
487 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
488 System-on-Chip devices.
491 bool "Nuvoton W90X900 CPU"
495 select GENERIC_CLOCKEVENTS
498 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
499 At present, the w90x900 has been renamed nuc900, regarding
500 the ARM series product line, you can login the following
501 link address to know more.
503 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
504 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
510 select CLKSRC_LPC32XX
513 select GENERIC_CLOCKEVENTS
514 select GENERIC_IRQ_MULTI_HANDLER
519 Support for the NXP LPC32XX family of processors
522 bool "PXA2xx/PXA3xx-based"
525 select ARM_CPU_SUSPEND if PM
532 select CPU_XSCALE if !CPU_XSC3
533 select GENERIC_CLOCKEVENTS
534 select GENERIC_IRQ_MULTI_HANDLER
542 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
548 select ARCH_MAY_HAVE_PC_FDC
549 select ARCH_SPARSEMEM_ENABLE
550 select ARCH_USES_GETTIMEOFFSET
554 select HAVE_PATA_PLATFORM
556 select NEED_MACH_IO_H
557 select NEED_MACH_MEMORY_H
560 On the Acorn Risc-PC, Linux can support the internal IDE disk and
561 CD-ROM interface, serial and parallel port, and the floppy drive.
566 select ARCH_SPARSEMEM_ENABLE
570 select TIMER_OF if OF
573 select GENERIC_CLOCKEVENTS
574 select GENERIC_IRQ_MULTI_HANDLER
579 select NEED_MACH_MEMORY_H
582 Support for StrongARM 11x0 based boards.
585 bool "Samsung S3C24XX SoCs"
588 select CLKSRC_SAMSUNG_PWM
589 select GENERIC_CLOCKEVENTS
592 select GENERIC_IRQ_MULTI_HANDLER
593 select HAVE_S3C2410_I2C if I2C
594 select HAVE_S3C2410_WATCHDOG if WATCHDOG
595 select HAVE_S3C_RTC if RTC_CLASS
596 select NEED_MACH_IO_H
597 select S3C2410_WATCHDOG
602 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
603 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
604 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
605 Samsung SMDK2410 development board (and derivatives).
609 select ARCH_HAS_HOLES_MEMORYMODEL
612 select GENERIC_ALLOCATOR
613 select GENERIC_CLOCKEVENTS
614 select GENERIC_IRQ_CHIP
617 select PM_GENERIC_DOMAINS if PM
618 select PM_GENERIC_DOMAINS_OF if PM && OF
620 select RESET_CONTROLLER
624 Support for TI's DaVinci platform.
629 select ARCH_HAS_HOLES_MEMORYMODEL
633 select GENERIC_CLOCKEVENTS
634 select GENERIC_IRQ_CHIP
635 select GENERIC_IRQ_MULTI_HANDLER
639 select NEED_MACH_IO_H if PCCARD
640 select NEED_MACH_MEMORY_H
643 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
647 menu "Multiple platform selection"
648 depends on ARCH_MULTIPLATFORM
650 comment "CPU Core family selection"
653 bool "ARMv4 based platforms (FA526)"
654 depends on !ARCH_MULTI_V6_V7
655 select ARCH_MULTI_V4_V5
658 config ARCH_MULTI_V4T
659 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
660 depends on !ARCH_MULTI_V6_V7
661 select ARCH_MULTI_V4_V5
662 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
663 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
664 CPU_ARM925T || CPU_ARM940T)
667 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
668 depends on !ARCH_MULTI_V6_V7
669 select ARCH_MULTI_V4_V5
670 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
671 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
672 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
674 config ARCH_MULTI_V4_V5
678 bool "ARMv6 based platforms (ARM11)"
679 select ARCH_MULTI_V6_V7
683 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
685 select ARCH_MULTI_V6_V7
689 config ARCH_MULTI_V6_V7
691 select MIGHT_HAVE_CACHE_L2X0
693 config ARCH_MULTI_CPU_AUTO
694 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
700 bool "Dummy Virtual Machine"
701 depends on ARCH_MULTI_V7
704 select ARM_GIC_V2M if PCI
706 select ARM_GIC_V3_ITS if PCI
708 select HAVE_ARM_ARCH_TIMER
711 # This is sorted alphabetically by mach-* pathname. However, plat-*
712 # Kconfigs may be included either alphabetically (according to the
713 # plat- suffix) or along side the corresponding mach-* source.
715 source "arch/arm/mach-actions/Kconfig"
717 source "arch/arm/mach-alpine/Kconfig"
719 source "arch/arm/mach-artpec/Kconfig"
721 source "arch/arm/mach-asm9260/Kconfig"
723 source "arch/arm/mach-aspeed/Kconfig"
725 source "arch/arm/mach-at91/Kconfig"
727 source "arch/arm/mach-axxia/Kconfig"
729 source "arch/arm/mach-bcm/Kconfig"
731 source "arch/arm/mach-berlin/Kconfig"
733 source "arch/arm/mach-clps711x/Kconfig"
735 source "arch/arm/mach-cns3xxx/Kconfig"
737 source "arch/arm/mach-davinci/Kconfig"
739 source "arch/arm/mach-digicolor/Kconfig"
741 source "arch/arm/mach-dove/Kconfig"
743 source "arch/arm/mach-ep93xx/Kconfig"
745 source "arch/arm/mach-exynos/Kconfig"
746 source "arch/arm/plat-samsung/Kconfig"
748 source "arch/arm/mach-footbridge/Kconfig"
750 source "arch/arm/mach-gemini/Kconfig"
752 source "arch/arm/mach-highbank/Kconfig"
754 source "arch/arm/mach-hisi/Kconfig"
756 source "arch/arm/mach-imx/Kconfig"
758 source "arch/arm/mach-integrator/Kconfig"
760 source "arch/arm/mach-iop13xx/Kconfig"
762 source "arch/arm/mach-iop32x/Kconfig"
764 source "arch/arm/mach-iop33x/Kconfig"
766 source "arch/arm/mach-ixp4xx/Kconfig"
768 source "arch/arm/mach-keystone/Kconfig"
770 source "arch/arm/mach-ks8695/Kconfig"
772 source "arch/arm/mach-mediatek/Kconfig"
774 source "arch/arm/mach-meson/Kconfig"
776 source "arch/arm/mach-mmp/Kconfig"
778 source "arch/arm/mach-moxart/Kconfig"
780 source "arch/arm/mach-mv78xx0/Kconfig"
782 source "arch/arm/mach-mvebu/Kconfig"
784 source "arch/arm/mach-mxs/Kconfig"
786 source "arch/arm/mach-netx/Kconfig"
788 source "arch/arm/mach-nomadik/Kconfig"
790 source "arch/arm/mach-npcm/Kconfig"
792 source "arch/arm/mach-nspire/Kconfig"
794 source "arch/arm/plat-omap/Kconfig"
796 source "arch/arm/mach-omap1/Kconfig"
798 source "arch/arm/mach-omap2/Kconfig"
800 source "arch/arm/mach-orion5x/Kconfig"
802 source "arch/arm/mach-oxnas/Kconfig"
804 source "arch/arm/mach-picoxcell/Kconfig"
806 source "arch/arm/mach-prima2/Kconfig"
808 source "arch/arm/mach-pxa/Kconfig"
809 source "arch/arm/plat-pxa/Kconfig"
811 source "arch/arm/mach-qcom/Kconfig"
813 source "arch/arm/mach-realview/Kconfig"
815 source "arch/arm/mach-rockchip/Kconfig"
817 source "arch/arm/mach-s3c24xx/Kconfig"
819 source "arch/arm/mach-s3c64xx/Kconfig"
821 source "arch/arm/mach-s5pv210/Kconfig"
823 source "arch/arm/mach-sa1100/Kconfig"
825 source "arch/arm/mach-shmobile/Kconfig"
827 source "arch/arm/mach-socfpga/Kconfig"
829 source "arch/arm/mach-spear/Kconfig"
831 source "arch/arm/mach-sti/Kconfig"
833 source "arch/arm/mach-stm32/Kconfig"
835 source "arch/arm/mach-sunxi/Kconfig"
837 source "arch/arm/mach-tango/Kconfig"
839 source "arch/arm/mach-tegra/Kconfig"
841 source "arch/arm/mach-u300/Kconfig"
843 source "arch/arm/mach-uniphier/Kconfig"
845 source "arch/arm/mach-ux500/Kconfig"
847 source "arch/arm/mach-versatile/Kconfig"
849 source "arch/arm/mach-vexpress/Kconfig"
850 source "arch/arm/plat-versatile/Kconfig"
852 source "arch/arm/mach-vt8500/Kconfig"
854 source "arch/arm/mach-w90x900/Kconfig"
856 source "arch/arm/mach-zx/Kconfig"
858 source "arch/arm/mach-zynq/Kconfig"
860 # ARMv7-M architecture
862 bool "Energy Micro efm32"
863 depends on ARM_SINGLE_ARMV7M
866 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
870 bool "NXP LPC18xx/LPC43xx"
871 depends on ARM_SINGLE_ARMV7M
872 select ARCH_HAS_RESET_CONTROLLER
874 select CLKSRC_LPC32XX
877 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
878 high performance microcontrollers.
881 bool "ARM MPS2 platform"
882 depends on ARM_SINGLE_ARMV7M
886 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
887 with a range of available cores like Cortex-M3/M4/M7.
889 Please, note that depends which Application Note is used memory map
890 for the platform may vary, so adjustment of RAM base might be needed.
892 # Definitions to make life easier
898 select GENERIC_CLOCKEVENTS
904 select GENERIC_IRQ_CHIP
907 config PLAT_ORION_LEGACY
914 config PLAT_VERSATILE
917 source "arch/arm/firmware/Kconfig"
919 source arch/arm/mm/Kconfig
922 bool "Enable iWMMXt support"
923 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
924 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
926 Enable support for iWMMXt context switching at run time if
927 running on a CPU that supports it.
930 source "arch/arm/Kconfig-nommu"
933 config PJ4B_ERRATA_4742
934 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
935 depends on CPU_PJ4B && MACH_ARMADA_370
938 When coming out of either a Wait for Interrupt (WFI) or a Wait for
939 Event (WFE) IDLE states, a specific timing sensitivity exists between
940 the retiring WFI/WFE instructions and the newly issued subsequent
941 instructions. This sensitivity can result in a CPU hang scenario.
943 The software must insert either a Data Synchronization Barrier (DSB)
944 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
947 config ARM_ERRATA_326103
948 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
951 Executing a SWP instruction to read-only memory does not set bit 11
952 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
953 treat the access as a read, preventing a COW from occurring and
954 causing the faulting task to livelock.
956 config ARM_ERRATA_411920
957 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
958 depends on CPU_V6 || CPU_V6K
960 Invalidation of the Instruction Cache operation can
961 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
962 It does not affect the MPCore. This option enables the ARM Ltd.
963 recommended workaround.
965 config ARM_ERRATA_430973
966 bool "ARM errata: Stale prediction on replaced interworking branch"
969 This option enables the workaround for the 430973 Cortex-A8
970 r1p* erratum. If a code sequence containing an ARM/Thumb
971 interworking branch is replaced with another code sequence at the
972 same virtual address, whether due to self-modifying code or virtual
973 to physical address re-mapping, Cortex-A8 does not recover from the
974 stale interworking branch prediction. This results in Cortex-A8
975 executing the new code sequence in the incorrect ARM or Thumb state.
976 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
977 and also flushes the branch target cache at every context switch.
978 Note that setting specific bits in the ACTLR register may not be
979 available in non-secure mode.
981 config ARM_ERRATA_458693
982 bool "ARM errata: Processor deadlock when a false hazard is created"
984 depends on !ARCH_MULTIPLATFORM
986 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
987 erratum. For very specific sequences of memory operations, it is
988 possible for a hazard condition intended for a cache line to instead
989 be incorrectly associated with a different cache line. This false
990 hazard might then cause a processor deadlock. The workaround enables
991 the L1 caching of the NEON accesses and disables the PLD instruction
992 in the ACTLR register. Note that setting specific bits in the ACTLR
993 register may not be available in non-secure mode.
995 config ARM_ERRATA_460075
996 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
998 depends on !ARCH_MULTIPLATFORM
1000 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1001 erratum. Any asynchronous access to the L2 cache may encounter a
1002 situation in which recent store transactions to the L2 cache are lost
1003 and overwritten with stale memory contents from external memory. The
1004 workaround disables the write-allocate mode for the L2 cache via the
1005 ACTLR register. Note that setting specific bits in the ACTLR register
1006 may not be available in non-secure mode.
1008 config ARM_ERRATA_742230
1009 bool "ARM errata: DMB operation may be faulty"
1010 depends on CPU_V7 && SMP
1011 depends on !ARCH_MULTIPLATFORM
1013 This option enables the workaround for the 742230 Cortex-A9
1014 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1015 between two write operations may not ensure the correct visibility
1016 ordering of the two writes. This workaround sets a specific bit in
1017 the diagnostic register of the Cortex-A9 which causes the DMB
1018 instruction to behave as a DSB, ensuring the correct behaviour of
1021 config ARM_ERRATA_742231
1022 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1023 depends on CPU_V7 && SMP
1024 depends on !ARCH_MULTIPLATFORM
1026 This option enables the workaround for the 742231 Cortex-A9
1027 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1028 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1029 accessing some data located in the same cache line, may get corrupted
1030 data due to bad handling of the address hazard when the line gets
1031 replaced from one of the CPUs at the same time as another CPU is
1032 accessing it. This workaround sets specific bits in the diagnostic
1033 register of the Cortex-A9 which reduces the linefill issuing
1034 capabilities of the processor.
1036 config ARM_ERRATA_643719
1037 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1038 depends on CPU_V7 && SMP
1041 This option enables the workaround for the 643719 Cortex-A9 (prior to
1042 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1043 register returns zero when it should return one. The workaround
1044 corrects this value, ensuring cache maintenance operations which use
1045 it behave as intended and avoiding data corruption.
1047 config ARM_ERRATA_720789
1048 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1051 This option enables the workaround for the 720789 Cortex-A9 (prior to
1052 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1053 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1054 As a consequence of this erratum, some TLB entries which should be
1055 invalidated are not, resulting in an incoherency in the system page
1056 tables. The workaround changes the TLB flushing routines to invalidate
1057 entries regardless of the ASID.
1059 config ARM_ERRATA_743622
1060 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1062 depends on !ARCH_MULTIPLATFORM
1064 This option enables the workaround for the 743622 Cortex-A9
1065 (r2p*) erratum. Under very rare conditions, a faulty
1066 optimisation in the Cortex-A9 Store Buffer may lead to data
1067 corruption. This workaround sets a specific bit in the diagnostic
1068 register of the Cortex-A9 which disables the Store Buffer
1069 optimisation, preventing the defect from occurring. This has no
1070 visible impact on the overall performance or power consumption of the
1073 config ARM_ERRATA_751472
1074 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1076 depends on !ARCH_MULTIPLATFORM
1078 This option enables the workaround for the 751472 Cortex-A9 (prior
1079 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1080 completion of a following broadcasted operation if the second
1081 operation is received by a CPU before the ICIALLUIS has completed,
1082 potentially leading to corrupted entries in the cache or TLB.
1084 config ARM_ERRATA_754322
1085 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1088 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1089 r3p*) erratum. A speculative memory access may cause a page table walk
1090 which starts prior to an ASID switch but completes afterwards. This
1091 can populate the micro-TLB with a stale entry which may be hit with
1092 the new ASID. This workaround places two dsb instructions in the mm
1093 switching code so that no page table walks can cross the ASID switch.
1095 config ARM_ERRATA_754327
1096 bool "ARM errata: no automatic Store Buffer drain"
1097 depends on CPU_V7 && SMP
1099 This option enables the workaround for the 754327 Cortex-A9 (prior to
1100 r2p0) erratum. The Store Buffer does not have any automatic draining
1101 mechanism and therefore a livelock may occur if an external agent
1102 continuously polls a memory location waiting to observe an update.
1103 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1104 written polling loops from denying visibility of updates to memory.
1106 config ARM_ERRATA_364296
1107 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1110 This options enables the workaround for the 364296 ARM1136
1111 r0p2 erratum (possible cache data corruption with
1112 hit-under-miss enabled). It sets the undocumented bit 31 in
1113 the auxiliary control register and the FI bit in the control
1114 register, thus disabling hit-under-miss without putting the
1115 processor into full low interrupt latency mode. ARM11MPCore
1118 config ARM_ERRATA_764369
1119 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1120 depends on CPU_V7 && SMP
1122 This option enables the workaround for erratum 764369
1123 affecting Cortex-A9 MPCore with two or more processors (all
1124 current revisions). Under certain timing circumstances, a data
1125 cache line maintenance operation by MVA targeting an Inner
1126 Shareable memory region may fail to proceed up to either the
1127 Point of Coherency or to the Point of Unification of the
1128 system. This workaround adds a DSB instruction before the
1129 relevant cache maintenance functions and sets a specific bit
1130 in the diagnostic control register of the SCU.
1132 config ARM_ERRATA_775420
1133 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1136 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1137 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1138 operation aborts with MMU exception, it might cause the processor
1139 to deadlock. This workaround puts DSB before executing ISB if
1140 an abort may occur on cache maintenance.
1142 config ARM_ERRATA_798181
1143 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1144 depends on CPU_V7 && SMP
1146 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1147 adequately shooting down all use of the old entries. This
1148 option enables the Linux kernel workaround for this erratum
1149 which sends an IPI to the CPUs that are running the same ASID
1150 as the one being invalidated.
1152 config ARM_ERRATA_773022
1153 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1156 This option enables the workaround for the 773022 Cortex-A15
1157 (up to r0p4) erratum. In certain rare sequences of code, the
1158 loop buffer may deliver incorrect instructions. This
1159 workaround disables the loop buffer to avoid the erratum.
1161 config ARM_ERRATA_818325_852422
1162 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1165 This option enables the workaround for:
1166 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1167 instruction might deadlock. Fixed in r0p1.
1168 - Cortex-A12 852422: Execution of a sequence of instructions might
1169 lead to either a data corruption or a CPU deadlock. Not fixed in
1170 any Cortex-A12 cores yet.
1171 This workaround for all both errata involves setting bit[12] of the
1172 Feature Register. This bit disables an optimisation applied to a
1173 sequence of 2 instructions that use opposing condition codes.
1175 config ARM_ERRATA_821420
1176 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1179 This option enables the workaround for the 821420 Cortex-A12
1180 (all revs) erratum. In very rare timing conditions, a sequence
1181 of VMOV to Core registers instructions, for which the second
1182 one is in the shadow of a branch or abort, can lead to a
1183 deadlock when the VMOV instructions are issued out-of-order.
1185 config ARM_ERRATA_825619
1186 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1189 This option enables the workaround for the 825619 Cortex-A12
1190 (all revs) erratum. Within rare timing constraints, executing a
1191 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1192 and Device/Strongly-Ordered loads and stores might cause deadlock
1194 config ARM_ERRATA_852421
1195 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1198 This option enables the workaround for the 852421 Cortex-A17
1199 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1200 execution of a DMB ST instruction might fail to properly order
1201 stores from GroupA and stores from GroupB.
1203 config ARM_ERRATA_852423
1204 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1207 This option enables the workaround for:
1208 - Cortex-A17 852423: Execution of a sequence of instructions might
1209 lead to either a data corruption or a CPU deadlock. Not fixed in
1210 any Cortex-A17 cores yet.
1211 This is identical to Cortex-A12 erratum 852422. It is a separate
1212 config option from the A12 erratum due to the way errata are checked
1217 source "arch/arm/common/Kconfig"
1224 Find out whether you have ISA slots on your motherboard. ISA is the
1225 name of a bus system, i.e. the way the CPU talks to the other stuff
1226 inside your box. Other bus systems are PCI, EISA, MicroChannel
1227 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1228 newer boards don't support it. If you have ISA, say Y, otherwise N.
1230 # Select ISA DMA controller support
1235 # Select ISA DMA interface
1240 bool "PCI support" if MIGHT_HAVE_PCI
1242 Find out whether you have a PCI motherboard. PCI is the name of a
1243 bus system, i.e. the way the CPU talks to the other stuff inside
1244 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1245 VESA. If you have PCI, say Y, otherwise N.
1248 bool "Support for multiple PCI domains"
1251 Enable PCI domains kernel management. Say Y if your machine
1252 has a PCI bus hierarchy that requires more than one PCI
1253 domain (aka segment) to be correctly managed. Say N otherwise.
1255 If you don't know what to do here, say N.
1257 config PCI_DOMAINS_GENERIC
1258 def_bool PCI_DOMAINS
1260 config PCI_NANOENGINE
1261 bool "BSE nanoEngine PCI support"
1262 depends on SA1100_NANOENGINE
1264 Enable PCI on the BSE nanoEngine board.
1269 config PCI_HOST_ITE8152
1271 depends on PCI && MACH_ARMCORE
1275 source "drivers/pci/Kconfig"
1277 source "drivers/pcmcia/Kconfig"
1281 menu "Kernel Features"
1286 This option should be selected by machines which have an SMP-
1289 The only effect of this option is to make the SMP-related
1290 options available to the user for configuration.
1293 bool "Symmetric Multi-Processing"
1294 depends on CPU_V6K || CPU_V7
1295 depends on GENERIC_CLOCKEVENTS
1297 depends on MMU || ARM_MPU
1300 This enables support for systems with more than one CPU. If you have
1301 a system with only one CPU, say N. If you have a system with more
1302 than one CPU, say Y.
1304 If you say N here, the kernel will run on uni- and multiprocessor
1305 machines, but will use only one CPU of a multiprocessor machine. If
1306 you say Y here, the kernel will run on many, but not all,
1307 uniprocessor machines. On a uniprocessor machine, the kernel
1308 will run faster if you say N here.
1310 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1311 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1312 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1314 If you don't know what to do here, say N.
1317 bool "Allow booting SMP kernel on uniprocessor systems"
1318 depends on SMP && !XIP_KERNEL && MMU
1321 SMP kernels contain instructions which fail on non-SMP processors.
1322 Enabling this option allows the kernel to modify itself to make
1323 these instructions safe. Disabling it allows about 1K of space
1326 If you don't know what to do here, say Y.
1328 config ARM_CPU_TOPOLOGY
1329 bool "Support cpu topology definition"
1330 depends on SMP && CPU_V7
1333 Support ARM cpu topology definition. The MPIDR register defines
1334 affinity between processors which is then used to describe the cpu
1335 topology of an ARM System.
1338 bool "Multi-core scheduler support"
1339 depends on ARM_CPU_TOPOLOGY
1341 Multi-core scheduler support improves the CPU scheduler's decision
1342 making when dealing with multi-core CPU chips at a cost of slightly
1343 increased overhead in some places. If unsure say N here.
1346 bool "SMT scheduler support"
1347 depends on ARM_CPU_TOPOLOGY
1349 Improves the CPU scheduler's decision making when dealing with
1350 MultiThreading at a cost of slightly increased overhead in some
1351 places. If unsure say N here.
1356 This option enables support for the ARM system coherency unit
1358 config HAVE_ARM_ARCH_TIMER
1359 bool "Architected timer support"
1361 select ARM_ARCH_TIMER
1362 select GENERIC_CLOCKEVENTS
1364 This option enables support for the ARM architected timer
1368 select TIMER_OF if OF
1370 This options enables support for the ARM timer and watchdog unit
1373 bool "Multi-Cluster Power Management"
1374 depends on CPU_V7 && SMP
1376 This option provides the common power management infrastructure
1377 for (multi-)cluster based systems, such as big.LITTLE based
1380 config MCPM_QUAD_CLUSTER
1384 To avoid wasting resources unnecessarily, MCPM only supports up
1385 to 2 clusters by default.
1386 Platforms with 3 or 4 clusters that use MCPM must select this
1387 option to allow the additional clusters to be managed.
1390 bool "big.LITTLE support (Experimental)"
1391 depends on CPU_V7 && SMP
1394 This option enables support selections for the big.LITTLE
1395 system architecture.
1398 bool "big.LITTLE switcher support"
1399 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1402 The big.LITTLE "switcher" provides the core functionality to
1403 transparently handle transition between a cluster of A15's
1404 and a cluster of A7's in a big.LITTLE system.
1406 config BL_SWITCHER_DUMMY_IF
1407 tristate "Simple big.LITTLE switcher user interface"
1408 depends on BL_SWITCHER && DEBUG_KERNEL
1410 This is a simple and dummy char dev interface to control
1411 the big.LITTLE switcher core code. It is meant for
1412 debugging purposes only.
1415 prompt "Memory split"
1419 Select the desired split between kernel and user memory.
1421 If you are not absolutely sure what you are doing, leave this
1425 bool "3G/1G user/kernel split"
1426 config VMSPLIT_3G_OPT
1427 depends on !ARM_LPAE
1428 bool "3G/1G user/kernel split (for full 1G low memory)"
1430 bool "2G/2G user/kernel split"
1432 bool "1G/3G user/kernel split"
1437 default PHYS_OFFSET if !MMU
1438 default 0x40000000 if VMSPLIT_1G
1439 default 0x80000000 if VMSPLIT_2G
1440 default 0xB0000000 if VMSPLIT_3G_OPT
1444 int "Maximum number of CPUs (2-32)"
1450 bool "Support for hot-pluggable CPUs"
1452 select GENERIC_IRQ_MIGRATION
1454 Say Y here to experiment with turning CPUs off and on. CPUs
1455 can be controlled through /sys/devices/system/cpu.
1458 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1459 depends on HAVE_ARM_SMCCC
1462 Say Y here if you want Linux to communicate with system firmware
1463 implementing the PSCI specification for CPU-centric power
1464 management operations described in ARM document number ARM DEN
1465 0022A ("Power State Coordination Interface System Software on
1468 # The GPIO number here must be sorted by descending number. In case of
1469 # a multiplatform kernel, we just want the highest value required by the
1470 # selected platforms.
1473 default 2048 if ARCH_SOCFPGA
1474 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1476 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1477 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1478 default 416 if ARCH_SUNXI
1479 default 392 if ARCH_U8500
1480 default 352 if ARCH_VT8500
1481 default 288 if ARCH_ROCKCHIP
1482 default 264 if MACH_H4700
1485 Maximum number of GPIOs in the system.
1487 If unsure, leave the default value.
1491 default 200 if ARCH_EBSA110
1492 default 128 if SOC_AT91RM9200
1496 depends on HZ_FIXED = 0
1497 prompt "Timer frequency"
1521 default HZ_FIXED if HZ_FIXED != 0
1522 default 100 if HZ_100
1523 default 200 if HZ_200
1524 default 250 if HZ_250
1525 default 300 if HZ_300
1526 default 500 if HZ_500
1530 def_bool HIGH_RES_TIMERS
1532 config THUMB2_KERNEL
1533 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1534 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1535 default y if CPU_THUMBONLY
1538 By enabling this option, the kernel will be compiled in
1543 config THUMB2_AVOID_R_ARM_THM_JUMP11
1544 bool "Work around buggy Thumb-2 short branch relocations in gas"
1545 depends on THUMB2_KERNEL && MODULES
1548 Various binutils versions can resolve Thumb-2 branches to
1549 locally-defined, preemptible global symbols as short-range "b.n"
1550 branch instructions.
1552 This is a problem, because there's no guarantee the final
1553 destination of the symbol, or any candidate locations for a
1554 trampoline, are within range of the branch. For this reason, the
1555 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1556 relocation in modules at all, and it makes little sense to add
1559 The symptom is that the kernel fails with an "unsupported
1560 relocation" error when loading some modules.
1562 Until fixed tools are available, passing
1563 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1564 code which hits this problem, at the cost of a bit of extra runtime
1565 stack usage in some cases.
1567 The problem is described in more detail at:
1568 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1570 Only Thumb-2 kernels are affected.
1572 Unless you are sure your tools don't have this problem, say Y.
1574 config ARM_PATCH_IDIV
1575 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1576 depends on CPU_32v7 && !XIP_KERNEL
1579 The ARM compiler inserts calls to __aeabi_idiv() and
1580 __aeabi_uidiv() when it needs to perform division on signed
1581 and unsigned integers. Some v7 CPUs have support for the sdiv
1582 and udiv instructions that can be used to implement those
1585 Enabling this option allows the kernel to modify itself to
1586 replace the first two instructions of these library functions
1587 with the sdiv or udiv plus "bx lr" instructions when the CPU
1588 it is running on supports them. Typically this will be faster
1589 and less power intensive than running the original library
1590 code to do integer division.
1593 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1594 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1595 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1597 This option allows for the kernel to be compiled using the latest
1598 ARM ABI (aka EABI). This is only useful if you are using a user
1599 space environment that is also compiled with EABI.
1601 Since there are major incompatibilities between the legacy ABI and
1602 EABI, especially with regard to structure member alignment, this
1603 option also changes the kernel syscall calling convention to
1604 disambiguate both ABIs and allow for backward compatibility support
1605 (selected with CONFIG_OABI_COMPAT).
1607 To use this you need GCC version 4.0.0 or later.
1610 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1611 depends on AEABI && !THUMB2_KERNEL
1613 This option preserves the old syscall interface along with the
1614 new (ARM EABI) one. It also provides a compatibility layer to
1615 intercept syscalls that have structure arguments which layout
1616 in memory differs between the legacy ABI and the new ARM EABI
1617 (only for non "thumb" binaries). This option adds a tiny
1618 overhead to all syscalls and produces a slightly larger kernel.
1620 The seccomp filter system will not be available when this is
1621 selected, since there is no way yet to sensibly distinguish
1622 between calling conventions during filtering.
1624 If you know you'll be using only pure EABI user space then you
1625 can say N here. If this option is not selected and you attempt
1626 to execute a legacy ABI binary then the result will be
1627 UNPREDICTABLE (in fact it can be predicted that it won't work
1628 at all). If in doubt say N.
1630 config ARCH_HAS_HOLES_MEMORYMODEL
1633 config ARCH_SPARSEMEM_ENABLE
1636 config ARCH_SPARSEMEM_DEFAULT
1637 def_bool ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SELECT_MEMORY_MODEL
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config HAVE_ARCH_PFN_VALID
1643 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1645 config HAVE_GENERIC_GUP
1650 bool "High Memory Support"
1653 The address space of ARM processors is only 4 Gigabytes large
1654 and it has to accommodate user address space, kernel address
1655 space as well as some memory mapped IO. That means that, if you
1656 have a large amount of physical memory and/or IO, not all of the
1657 memory can be "permanently mapped" by the kernel. The physical
1658 memory that is not permanently mapped is called "high memory".
1660 Depending on the selected kernel/user memory split, minimum
1661 vmalloc space and actual amount of RAM, you may not need this
1662 option which should result in a slightly faster kernel.
1667 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1671 The VM uses one page of physical memory for each page table.
1672 For systems with a lot of processes, this can use a lot of
1673 precious low memory, eventually leading to low memory being
1674 consumed by page tables. Setting this option will allow
1675 user-space 2nd level page tables to reside in high memory.
1677 config CPU_SW_DOMAIN_PAN
1678 bool "Enable use of CPU domains to implement privileged no-access"
1679 depends on MMU && !ARM_LPAE
1682 Increase kernel security by ensuring that normal kernel accesses
1683 are unable to access userspace addresses. This can help prevent
1684 use-after-free bugs becoming an exploitable privilege escalation
1685 by ensuring that magic values (such as LIST_POISON) will always
1686 fault when dereferenced.
1688 CPUs with low-vector mappings use a best-efforts implementation.
1689 Their lower 1MB needs to remain accessible for the vectors, but
1690 the remainder of userspace will become appropriately inaccessible.
1692 config HW_PERF_EVENTS
1696 config SYS_SUPPORTS_HUGETLBFS
1700 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1704 config ARCH_WANT_GENERAL_HUGETLB
1707 config ARM_MODULE_PLTS
1708 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1712 Allocate PLTs when loading modules so that jumps and calls whose
1713 targets are too far away for their relative offsets to be encoded
1714 in the instructions themselves can be bounced via veneers in the
1715 module's PLT. This allows modules to be allocated in the generic
1716 vmalloc area after the dedicated module memory area has been
1717 exhausted. The modules will use slightly more memory, but after
1718 rounding up to page size, the actual memory footprint is usually
1721 Disabling this is usually safe for small single-platform
1722 configurations. If unsure, say y.
1724 config FORCE_MAX_ZONEORDER
1725 int "Maximum zone order"
1726 default "12" if SOC_AM33XX
1727 default "9" if SA1111 || ARCH_EFM32
1730 The kernel memory allocator divides physically contiguous memory
1731 blocks into "zones", where each zone is a power of two number of
1732 pages. This option selects the largest power of two that the kernel
1733 keeps in the memory allocator. If you need to allocate very large
1734 blocks of physically contiguous memory, then you may need to
1735 increase this value.
1737 This config option is actually maximum order plus one. For example,
1738 a value of 11 means that the largest free memory block is 2^10 pages.
1740 config ALIGNMENT_TRAP
1742 depends on CPU_CP15_MMU
1743 default y if !ARCH_EBSA110
1744 select HAVE_PROC_CPU if PROC_FS
1746 ARM processors cannot fetch/store information which is not
1747 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1748 address divisible by 4. On 32-bit ARM processors, these non-aligned
1749 fetch/store instructions will be emulated in software if you say
1750 here, which has a severe performance impact. This is necessary for
1751 correct operation of some network protocols. With an IP-only
1752 configuration it is safe to say N, otherwise say Y.
1754 config UACCESS_WITH_MEMCPY
1755 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1757 default y if CPU_FEROCEON
1759 Implement faster copy_to_user and clear_user methods for CPU
1760 cores where a 8-word STM instruction give significantly higher
1761 memory write throughput than a sequence of individual 32bit stores.
1763 A possible side effect is a slight increase in scheduling latency
1764 between threads sharing the same address space if they invoke
1765 such copy operations with large buffers.
1767 However, if the CPU data cache is using a write-allocate mode,
1768 this option is unlikely to provide any performance gain.
1772 prompt "Enable seccomp to safely compute untrusted bytecode"
1774 This kernel feature is useful for number crunching applications
1775 that may need to compute untrusted bytecode during their
1776 execution. By using pipes or other transports made available to
1777 the process as file descriptors supporting the read/write
1778 syscalls, it's possible to isolate those applications in
1779 their own address space using seccomp. Once seccomp is
1780 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1781 and the task is only allowed to execute a few safe syscalls
1782 defined by each seccomp mode.
1785 bool "Enable paravirtualization code"
1787 This changes the kernel so it can modify itself when it is run
1788 under a hypervisor, potentially improving performance significantly
1789 over full virtualization.
1791 config PARAVIRT_TIME_ACCOUNTING
1792 bool "Paravirtual steal time accounting"
1796 Select this option to enable fine granularity task steal time
1797 accounting. Time spent executing other tasks in parallel with
1798 the current vCPU is discounted from the vCPU power. To account for
1799 that, there can be a small performance impact.
1801 If in doubt, say N here.
1808 bool "Xen guest support on ARM"
1809 depends on ARM && AEABI && OF
1810 depends on CPU_V7 && !CPU_V6
1811 depends on !GENERIC_ATOMIC64
1813 select ARCH_DMA_ADDR_T_64BIT
1819 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1826 bool "Flattened Device Tree support"
1830 Include support for flattened device tree machine descriptions.
1833 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836 This is the traditional way of passing data to the kernel at boot
1837 time. If you are solely relying on the flattened device tree (or
1838 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1839 to remove ATAGS support from your kernel binary. If unsure,
1842 config DEPRECATED_PARAM_STRUCT
1843 bool "Provide old way to pass kernel parameters"
1846 This was deprecated in 2001 and announced to live on for 5 years.
1847 Some old boot loaders still use this way.
1849 # Compressed boot loader in ROM. Yes, we really want to ask about
1850 # TEXT and BSS so we preserve their values in the config files.
1851 config ZBOOT_ROM_TEXT
1852 hex "Compressed ROM boot loader base address"
1855 The physical address at which the ROM-able zImage is to be
1856 placed in the target. Platforms which normally make use of
1857 ROM-able zImage formats normally set this to a suitable
1858 value in their defconfig file.
1860 If ZBOOT_ROM is not enabled, this has no effect.
1862 config ZBOOT_ROM_BSS
1863 hex "Compressed ROM boot loader BSS address"
1866 The base address of an area of read/write memory in the target
1867 for the ROM-able zImage which must be available while the
1868 decompressor is running. It must be large enough to hold the
1869 entire decompressed kernel plus an additional 128 KiB.
1870 Platforms which normally make use of ROM-able zImage formats
1871 normally set this to a suitable value in their defconfig file.
1873 If ZBOOT_ROM is not enabled, this has no effect.
1876 bool "Compressed boot loader in ROM/flash"
1877 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1878 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1880 Say Y here if you intend to execute your compressed kernel image
1881 (zImage) directly from ROM or flash. If unsure, say N.
1883 config ARM_APPENDED_DTB
1884 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887 With this option, the boot code will look for a device tree binary
1888 (DTB) appended to zImage
1889 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1891 This is meant as a backward compatibility convenience for those
1892 systems with a bootloader that can't be upgraded to accommodate
1893 the documented boot protocol using a device tree.
1895 Beware that there is very little in terms of protection against
1896 this option being confused by leftover garbage in memory that might
1897 look like a DTB header after a reboot if no actual DTB is appended
1898 to zImage. Do not leave this option active in a production kernel
1899 if you don't intend to always append a DTB. Proper passing of the
1900 location into r2 of a bootloader provided DTB is always preferable
1903 config ARM_ATAG_DTB_COMPAT
1904 bool "Supplement the appended DTB with traditional ATAG information"
1905 depends on ARM_APPENDED_DTB
1907 Some old bootloaders can't be updated to a DTB capable one, yet
1908 they provide ATAGs with memory configuration, the ramdisk address,
1909 the kernel cmdline string, etc. Such information is dynamically
1910 provided by the bootloader and can't always be stored in a static
1911 DTB. To allow a device tree enabled kernel to be used with such
1912 bootloaders, this option allows zImage to extract the information
1913 from the ATAG list and store it at run time into the appended DTB.
1916 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1917 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 bool "Use bootloader kernel arguments if available"
1922 Uses the command-line options passed by the boot loader instead of
1923 the device tree bootargs property. If the boot loader doesn't provide
1924 any, the device tree bootargs property will be used.
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1927 bool "Extend with bootloader kernel arguments"
1929 The command-line arguments provided by the boot loader will be
1930 appended to the the device tree bootargs property.
1935 string "Default kernel command string"
1938 On some architectures (EBSA110 and CATS), there is currently no way
1939 for the boot loader to pass arguments to the kernel. For these
1940 architectures, you should supply some command-line options at build
1941 time by entering them here. As a minimum, you should specify the
1942 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945 prompt "Kernel command line type" if CMDLINE != ""
1946 default CMDLINE_FROM_BOOTLOADER
1948 config CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1951 Uses the command-line options passed by the boot loader. If
1952 the boot loader doesn't provide any, the default kernel command
1953 string provided in CMDLINE will be used.
1955 config CMDLINE_EXTEND
1956 bool "Extend bootloader kernel arguments"
1958 The command-line arguments provided by the boot loader will be
1959 appended to the default kernel command string.
1961 config CMDLINE_FORCE
1962 bool "Always use the default kernel command string"
1964 Always use the default kernel command string, even if the boot
1965 loader passes other arguments to the kernel.
1966 This is useful if you cannot or don't want to change the
1967 command-line options your boot loader passes to the kernel.
1971 bool "Kernel Execute-In-Place from ROM"
1972 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1974 Execute-In-Place allows the kernel to run from non-volatile storage
1975 directly addressable by the CPU, such as NOR flash. This saves RAM
1976 space since the text section of the kernel is not loaded from flash
1977 to RAM. Read-write sections, such as the data section and stack,
1978 are still copied to RAM. The XIP kernel is not compressed since
1979 it has to run directly from flash, so it will take more space to
1980 store it. The flash address used to link the kernel object files,
1981 and for storing it, is configuration dependent. Therefore, if you
1982 say Y here, you must know the proper physical address where to
1983 store the kernel image depending on your own flash memory usage.
1985 Also note that the make target becomes "make xipImage" rather than
1986 "make zImage" or "make Image". The final kernel binary to put in
1987 ROM memory will be arch/arm/boot/xipImage.
1991 config XIP_PHYS_ADDR
1992 hex "XIP Kernel Physical Location"
1993 depends on XIP_KERNEL
1994 default "0x00080000"
1996 This is the physical address in your flash memory the kernel will
1997 be linked for and stored to. This address is dependent on your
2000 config XIP_DEFLATED_DATA
2001 bool "Store kernel .data section compressed in ROM"
2002 depends on XIP_KERNEL
2005 Before the kernel is actually executed, its .data section has to be
2006 copied to RAM from ROM. This option allows for storing that data
2007 in compressed form and decompressed to RAM rather than merely being
2008 copied, saving some precious ROM space. A possible drawback is a
2009 slightly longer boot delay.
2012 bool "Kexec system call (EXPERIMENTAL)"
2013 depends on (!SMP || PM_SLEEP_SMP)
2017 kexec is a system call that implements the ability to shutdown your
2018 current kernel, and to start another kernel. It is like a reboot
2019 but it is independent of the system firmware. And like a reboot
2020 you can start any kernel with it, not just Linux.
2022 It is an ongoing process to be certain the hardware in a machine
2023 is properly shutdown, so do not be surprised if this code does not
2024 initially work for you.
2027 bool "Export atags in procfs"
2028 depends on ATAGS && KEXEC
2031 Should the atags used to boot the kernel be exported in an "atags"
2032 file in procfs. Useful with kexec.
2035 bool "Build kdump crash kernel (EXPERIMENTAL)"
2037 Generate crash dump after being started by kexec. This should
2038 be normally only set in special crash dump kernels which are
2039 loaded in the main kernel with kexec-tools into a specially
2040 reserved region and then later executed after a crash by
2041 kdump/kexec. The crash dump kernel must be compiled to a
2042 memory address not used by the main kernel
2044 For more details see Documentation/kdump/kdump.txt
2046 config AUTO_ZRELADDR
2047 bool "Auto calculation of the decompressed kernel image address"
2049 ZRELADDR is the physical address where the decompressed kernel
2050 image will be placed. If AUTO_ZRELADDR is selected, the address
2051 will be determined at run-time by masking the current IP with
2052 0xf8000000. This assumes the zImage being placed in the first 128MB
2053 from start of memory.
2059 bool "UEFI runtime support"
2060 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2062 select EFI_PARAMS_FROM_FDT
2065 select EFI_RUNTIME_WRAPPERS
2067 This option provides support for runtime services provided
2068 by UEFI firmware (such as non-volatile variables, realtime
2069 clock, and platform reset). A UEFI stub is also provided to
2070 allow the kernel to be booted as an EFI application. This
2071 is only useful for kernels that may run on systems that have
2075 bool "Enable support for SMBIOS (DMI) tables"
2079 This enables SMBIOS/DMI feature for systems.
2081 This option is only useful on systems that have UEFI firmware.
2082 However, even with this option, the resultant kernel should
2083 continue to boot on existing non-UEFI platforms.
2085 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2086 i.e., the the practice of identifying the platform via DMI to
2087 decide whether certain workarounds for buggy hardware and/or
2088 firmware need to be enabled. This would require the DMI subsystem
2089 to be enabled much earlier than we do on ARM, which is non-trivial.
2093 menu "CPU Power Management"
2095 source "drivers/cpufreq/Kconfig"
2097 source "drivers/cpuidle/Kconfig"
2101 menu "Floating point emulation"
2103 comment "At least one emulation must be selected"
2106 bool "NWFPE math emulation"
2107 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2109 Say Y to include the NWFPE floating point emulator in the kernel.
2110 This is necessary to run most binaries. Linux does not currently
2111 support floating point hardware so you need to say Y here even if
2112 your machine has an FPA or floating point co-processor podule.
2114 You may say N here if you are going to load the Acorn FPEmulator
2115 early in the bootup.
2118 bool "Support extended precision"
2119 depends on FPE_NWFPE
2121 Say Y to include 80-bit support in the kernel floating-point
2122 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2123 Note that gcc does not generate 80-bit operations by default,
2124 so in most cases this option only enlarges the size of the
2125 floating point emulator without any good reason.
2127 You almost surely want to say N here.
2130 bool "FastFPE math emulation (EXPERIMENTAL)"
2131 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2133 Say Y here to include the FAST floating point emulator in the kernel.
2134 This is an experimental much faster emulator which now also has full
2135 precision for the mantissa. It does not support any exceptions.
2136 It is very simple, and approximately 3-6 times faster than NWFPE.
2138 It should be sufficient for most programs. It may be not suitable
2139 for scientific calculations, but you have to check this for yourself.
2140 If you do not feel you need a faster FP emulation you should better
2144 bool "VFP-format floating point maths"
2145 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2147 Say Y to include VFP support code in the kernel. This is needed
2148 if your hardware includes a VFP unit.
2150 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2151 release notes and additional status information.
2153 Say N if your target does not have VFP hardware.
2161 bool "Advanced SIMD (NEON) Extension support"
2162 depends on VFPv3 && CPU_V7
2164 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2167 config KERNEL_MODE_NEON
2168 bool "Support for NEON in kernel mode"
2169 depends on NEON && AEABI
2171 Say Y to include support for NEON in kernel mode.
2175 menu "Power management options"
2177 source "kernel/power/Kconfig"
2179 config ARCH_SUSPEND_POSSIBLE
2180 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2181 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2184 config ARM_CPU_SUSPEND
2185 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2186 depends on ARCH_SUSPEND_POSSIBLE
2188 config ARCH_HIBERNATION_POSSIBLE
2191 default y if ARCH_SUSPEND_POSSIBLE
2195 source "drivers/firmware/Kconfig"
2198 source "arch/arm/crypto/Kconfig"
2201 source "arch/arm/kvm/Kconfig"