4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
40 select HAVE_ARM_SMCCC if CPU_V7
42 select HAVE_CC_STACKPROTECTOR
43 select HAVE_CONTEXT_TRACKING
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_DEBUG_KMEMLEAK
46 select HAVE_DMA_API_DEBUG
48 select HAVE_DMA_CONTIGUOUS if MMU
49 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
50 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
51 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
52 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
53 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
54 select HAVE_FUTEX_CMPXCHG if FUTEX
55 select HAVE_GENERIC_DMA_COHERENT
56 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
57 select HAVE_IDE if PCI || ISA || PCMCIA
58 select HAVE_IRQ_TIME_ACCOUNTING
59 select HAVE_KERNEL_GZIP
60 select HAVE_KERNEL_LZ4
61 select HAVE_KERNEL_LZMA
62 select HAVE_KERNEL_LZO
64 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
65 select HAVE_KRETPROBES if (HAVE_KPROBES)
67 select HAVE_MOD_ARCH_SPECIFIC
68 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
69 select HAVE_OPTPROBES if !THUMB2_KERNEL
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
74 select HAVE_REGS_AND_STACK_ACCESS_API
75 select HAVE_SYSCALL_TRACEPOINTS
77 select HAVE_VIRT_CPU_ACCOUNTING_GEN
78 select IRQ_FORCED_THREADING
79 select MODULES_USE_ELF_REL
81 select OF_EARLY_FLATTREE if OF
82 select OF_RESERVED_MEM if OF
84 select OLD_SIGSUSPEND3
85 select PERF_USE_VMALLOC
87 select SYS_SUPPORTS_APM_EMULATION
88 # Above selects are sorted alphabetically; please add new ones
89 # according to that. Thanks.
91 The ARM series is a line of low-power-consumption RISC chip designs
92 licensed by ARM Ltd and targeted at embedded applications and
93 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
94 manufactured, but legacy ARM-based PC hardware remains popular in
95 Europe. There is an ARM Linux project with a web page at
96 <http://www.arm.linux.org.uk/>.
98 config ARM_HAS_SG_CHAIN
99 select ARCH_HAS_SG_CHAIN
102 config NEED_SG_DMA_LENGTH
105 config ARM_DMA_USE_IOMMU
107 select ARM_HAS_SG_CHAIN
108 select NEED_SG_DMA_LENGTH
112 config ARM_DMA_IOMMU_ALIGNMENT
113 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
117 DMA mapping framework by default aligns all buffers to the smallest
118 PAGE_SIZE order which is greater than or equal to the requested buffer
119 size. This works well for buffers up to a few hundreds kilobytes, but
120 for larger buffers it just a waste of address space. Drivers which has
121 relatively small addressing window (like 64Mib) might run out of
122 virtual space with just a few allocations.
124 With this parameter you can specify the maximum PAGE_SIZE order for
125 DMA IOMMU buffers. Larger buffers will be aligned only to this
126 specified order. The order is expressed as a power of two multiplied
131 config MIGHT_HAVE_PCI
134 config SYS_SUPPORTS_APM_EMULATION
139 select GENERIC_ALLOCATOR
150 The Extended Industry Standard Architecture (EISA) bus was
151 developed as an open alternative to the IBM MicroChannel bus.
153 The EISA bus provided some of the features of the IBM MicroChannel
154 bus while maintaining backward compatibility with cards made for
155 the older ISA bus. The EISA bus saw limited use between 1988 and
156 1995 when it was made obsolete by the PCI bus.
158 Say Y here if you are building a kernel for an EISA-based machine.
165 config STACKTRACE_SUPPORT
169 config HAVE_LATENCYTOP_SUPPORT
174 config LOCKDEP_SUPPORT
178 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
186 config ARCH_HAS_ILOG2_U32
189 config ARCH_HAS_ILOG2_U64
192 config ARCH_HAS_BANDGAP
195 config FIX_EARLYCON_MEM
198 config GENERIC_HWEIGHT
202 config GENERIC_CALIBRATE_DELAY
206 config ARCH_MAY_HAVE_PC_FDC
212 config NEED_DMA_MAP_STATE
215 config ARCH_SUPPORTS_UPROBES
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
221 config GENERIC_ISA_DMA
227 config NEED_RET_TO_USER
235 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
236 default DRAM_BASE if REMAP_VECTORS_TO_RAM
239 The base address of exception vectors. This must be two pages
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
246 depends on !ARCH_REALVIEW || !SPARSEMEM
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
282 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
286 default 0xc0000000 if ARCH_SA1100
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
295 config PGTABLE_LEVELS
297 default 3 if ARM_LPAE
300 source "init/Kconfig"
302 source "kernel/Kconfig.freezer"
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
314 # The "ARM system type" choice list is ordered alphabetically by option
315 # text. Please add new entries in the option alphabetic order.
318 prompt "ARM system type"
319 default ARCH_VERSATILE if !MMU
320 default ARCH_MULTIPLATFORM if MMU
322 config ARCH_MULTIPLATFORM
323 bool "Allow multiple platforms to be selected"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
326 select ARM_HAS_SG_CHAIN
327 select ARM_PATCH_PHYS_VIRT
331 select GENERIC_CLOCKEVENTS
332 select MIGHT_HAVE_PCI
333 select MULTI_IRQ_HANDLER
337 config ARM_SINGLE_ARMV7M
338 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select GENERIC_CLOCKEVENTS
352 bool "ARM Ltd. RealView family"
353 select ARCH_WANT_OPTIONAL_GPIOLIB
355 select ARM_TIMER_SP804
357 select COMMON_CLK_VERSATILE
358 select GENERIC_CLOCKEVENTS
359 select GPIO_PL061 if GPIOLIB
361 select NEED_MACH_MEMORY_H
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_SCHED_CLOCK
365 This enables support for ARM Ltd RealView boards.
367 config ARCH_VERSATILE
368 bool "ARM Ltd. Versatile family"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
371 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select HAVE_MACH_CLKDEV
377 select PLAT_VERSATILE
378 select PLAT_VERSATILE_CLOCK
379 select PLAT_VERSATILE_SCHED_CLOCK
380 select VERSATILE_FPGA_IRQ
382 This enables support for ARM Ltd Versatile board.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cortina Systems Gemini"
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
404 Support for the Cortina Systems Gemini family SoCs
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_REQUIRE_GPIOLIB
425 select ARM_PATCH_PHYS_VIRT
431 select GENERIC_CLOCKEVENTS
433 This enables support for the Cirrus EP93xx series of CPUs.
435 config ARCH_FOOTBRIDGE
439 select GENERIC_CLOCKEVENTS
441 select NEED_MACH_IO_H if !MMU
442 select NEED_MACH_MEMORY_H
444 Support for systems based on the DC21285 companion chip
445 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
448 bool "Hilscher NetX based"
452 select GENERIC_CLOCKEVENTS
454 This enables support for systems based on the Hilscher NetX Soc
460 select NEED_MACH_MEMORY_H
461 select NEED_RET_TO_USER
467 Support for Intel's IOP13XX (XScale) family of processors.
472 select ARCH_REQUIRE_GPIOLIB
475 select NEED_RET_TO_USER
479 Support for Intel's 80219 and IOP32X (XScale) family of
485 select ARCH_REQUIRE_GPIOLIB
488 select NEED_RET_TO_USER
492 Support for Intel's IOP33X (XScale) family of processors.
497 select ARCH_HAS_DMA_SET_COHERENT_MASK
498 select ARCH_REQUIRE_GPIOLIB
499 select ARCH_SUPPORTS_BIG_ENDIAN
502 select DMABOUNCE if PCI
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
505 select NEED_MACH_IO_H
506 select USB_EHCI_BIG_ENDIAN_DESC
507 select USB_EHCI_BIG_ENDIAN_MMIO
509 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
516 select MIGHT_HAVE_PCI
520 select PLAT_ORION_LEGACY
522 Support for the Marvell Dove SoC 88AP510
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
545 select MULTI_IRQ_HANDLER
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select MULTI_IRQ_HANDLER
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
605 Support for the NXP LPC32XX family of processors
608 bool "PXA2xx/PXA3xx-based"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
618 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
632 select ARCH_MAY_HAVE_PC_FDC
633 select ARCH_SPARSEMEM_ENABLE
634 select ARCH_USES_GETTIMEOFFSET
638 select HAVE_PATA_PLATFORM
640 select NEED_MACH_IO_H
641 select NEED_MACH_MEMORY_H
645 On the Acorn Risc-PC, Linux can support the internal IDE disk and
646 CD-ROM interface, serial and parallel port, and the floppy drive.
651 select ARCH_REQUIRE_GPIOLIB
652 select ARCH_SPARSEMEM_ENABLE
657 select GENERIC_CLOCKEVENTS
661 select MULTI_IRQ_HANDLER
662 select NEED_MACH_MEMORY_H
665 Support for StrongARM 11x0 based boards.
668 bool "Samsung S3C24XX SoCs"
669 select ARCH_REQUIRE_GPIOLIB
672 select CLKSRC_SAMSUNG_PWM
673 select GENERIC_CLOCKEVENTS
675 select HAVE_S3C2410_I2C if I2C
676 select HAVE_S3C2410_WATCHDOG if WATCHDOG
677 select HAVE_S3C_RTC if RTC_CLASS
678 select MULTI_IRQ_HANDLER
679 select NEED_MACH_IO_H
680 select S3C2410_WATCHDOG
684 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
685 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
686 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
687 Samsung SMDK2410 development board (and derivatives).
690 bool "Samsung S3C64XX"
691 select ARCH_REQUIRE_GPIOLIB
696 select CLKSRC_SAMSUNG_PWM
697 select COMMON_CLK_SAMSUNG
699 select GENERIC_CLOCKEVENTS
701 select HAVE_S3C2410_I2C if I2C
702 select HAVE_S3C2410_WATCHDOG if WATCHDOG
706 select PM_GENERIC_DOMAINS if PM
708 select S3C_GPIO_TRACK
710 select SAMSUNG_WAKEMASK
711 select SAMSUNG_WDT_RESET
713 Samsung S3C64XX series based systems
717 select ARCH_HAS_HOLES_MEMORYMODEL
718 select ARCH_REQUIRE_GPIOLIB
720 select GENERIC_ALLOCATOR
721 select GENERIC_CLOCKEVENTS
722 select GENERIC_IRQ_CHIP
727 Support for TI's DaVinci platform.
732 select ARCH_HAS_HOLES_MEMORYMODEL
734 select ARCH_REQUIRE_GPIOLIB
737 select GENERIC_CLOCKEVENTS
738 select GENERIC_IRQ_CHIP
741 select MULTI_IRQ_HANDLER
742 select NEED_MACH_IO_H if PCCARD
743 select NEED_MACH_MEMORY_H
746 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
750 menu "Multiple platform selection"
751 depends on ARCH_MULTIPLATFORM
753 comment "CPU Core family selection"
756 bool "ARMv4 based platforms (FA526)"
757 depends on !ARCH_MULTI_V6_V7
758 select ARCH_MULTI_V4_V5
761 config ARCH_MULTI_V4T
762 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
763 depends on !ARCH_MULTI_V6_V7
764 select ARCH_MULTI_V4_V5
765 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
766 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
767 CPU_ARM925T || CPU_ARM940T)
770 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
771 depends on !ARCH_MULTI_V6_V7
772 select ARCH_MULTI_V4_V5
773 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
774 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
775 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
777 config ARCH_MULTI_V4_V5
781 bool "ARMv6 based platforms (ARM11)"
782 select ARCH_MULTI_V6_V7
786 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
788 select ARCH_MULTI_V6_V7
792 config ARCH_MULTI_V6_V7
794 select MIGHT_HAVE_CACHE_L2X0
796 config ARCH_MULTI_CPU_AUTO
797 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
803 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
808 select HAVE_ARM_ARCH_TIMER
811 # This is sorted alphabetically by mach-* pathname. However, plat-*
812 # Kconfigs may be included either alphabetically (according to the
813 # plat- suffix) or along side the corresponding mach-* source.
815 source "arch/arm/mach-mvebu/Kconfig"
817 source "arch/arm/mach-alpine/Kconfig"
819 source "arch/arm/mach-asm9260/Kconfig"
821 source "arch/arm/mach-at91/Kconfig"
823 source "arch/arm/mach-axxia/Kconfig"
825 source "arch/arm/mach-bcm/Kconfig"
827 source "arch/arm/mach-berlin/Kconfig"
829 source "arch/arm/mach-clps711x/Kconfig"
831 source "arch/arm/mach-cns3xxx/Kconfig"
833 source "arch/arm/mach-davinci/Kconfig"
835 source "arch/arm/mach-digicolor/Kconfig"
837 source "arch/arm/mach-dove/Kconfig"
839 source "arch/arm/mach-ep93xx/Kconfig"
841 source "arch/arm/mach-footbridge/Kconfig"
843 source "arch/arm/mach-gemini/Kconfig"
845 source "arch/arm/mach-highbank/Kconfig"
847 source "arch/arm/mach-hisi/Kconfig"
849 source "arch/arm/mach-integrator/Kconfig"
851 source "arch/arm/mach-iop32x/Kconfig"
853 source "arch/arm/mach-iop33x/Kconfig"
855 source "arch/arm/mach-iop13xx/Kconfig"
857 source "arch/arm/mach-ixp4xx/Kconfig"
859 source "arch/arm/mach-keystone/Kconfig"
861 source "arch/arm/mach-ks8695/Kconfig"
863 source "arch/arm/mach-meson/Kconfig"
865 source "arch/arm/mach-moxart/Kconfig"
867 source "arch/arm/mach-mv78xx0/Kconfig"
869 source "arch/arm/mach-imx/Kconfig"
871 source "arch/arm/mach-mediatek/Kconfig"
873 source "arch/arm/mach-mxs/Kconfig"
875 source "arch/arm/mach-netx/Kconfig"
877 source "arch/arm/mach-nomadik/Kconfig"
879 source "arch/arm/mach-nspire/Kconfig"
881 source "arch/arm/plat-omap/Kconfig"
883 source "arch/arm/mach-omap1/Kconfig"
885 source "arch/arm/mach-omap2/Kconfig"
887 source "arch/arm/mach-orion5x/Kconfig"
889 source "arch/arm/mach-picoxcell/Kconfig"
891 source "arch/arm/mach-pxa/Kconfig"
892 source "arch/arm/plat-pxa/Kconfig"
894 source "arch/arm/mach-mmp/Kconfig"
896 source "arch/arm/mach-qcom/Kconfig"
898 source "arch/arm/mach-realview/Kconfig"
900 source "arch/arm/mach-rockchip/Kconfig"
902 source "arch/arm/mach-sa1100/Kconfig"
904 source "arch/arm/mach-socfpga/Kconfig"
906 source "arch/arm/mach-spear/Kconfig"
908 source "arch/arm/mach-sti/Kconfig"
910 source "arch/arm/mach-s3c24xx/Kconfig"
912 source "arch/arm/mach-s3c64xx/Kconfig"
914 source "arch/arm/mach-s5pv210/Kconfig"
916 source "arch/arm/mach-exynos/Kconfig"
917 source "arch/arm/plat-samsung/Kconfig"
919 source "arch/arm/mach-shmobile/Kconfig"
921 source "arch/arm/mach-sunxi/Kconfig"
923 source "arch/arm/mach-prima2/Kconfig"
925 source "arch/arm/mach-tegra/Kconfig"
927 source "arch/arm/mach-u300/Kconfig"
929 source "arch/arm/mach-uniphier/Kconfig"
931 source "arch/arm/mach-ux500/Kconfig"
933 source "arch/arm/mach-versatile/Kconfig"
935 source "arch/arm/mach-vexpress/Kconfig"
936 source "arch/arm/plat-versatile/Kconfig"
938 source "arch/arm/mach-vt8500/Kconfig"
940 source "arch/arm/mach-w90x900/Kconfig"
942 source "arch/arm/mach-zx/Kconfig"
944 source "arch/arm/mach-zynq/Kconfig"
946 # ARMv7-M architecture
948 bool "Energy Micro efm32"
949 depends on ARM_SINGLE_ARMV7M
950 select ARCH_REQUIRE_GPIOLIB
952 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
956 bool "NXP LPC18xx/LPC43xx"
957 depends on ARM_SINGLE_ARMV7M
958 select ARCH_HAS_RESET_CONTROLLER
960 select CLKSRC_LPC32XX
963 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
964 high performance microcontrollers.
967 bool "STMicrolectronics STM32"
968 depends on ARM_SINGLE_ARMV7M
969 select ARCH_HAS_RESET_CONTROLLER
970 select ARMV7M_SYSTICK
972 select RESET_CONTROLLER
974 Support for STMicroelectronics STM32 processors.
976 # Definitions to make life easier
982 select GENERIC_CLOCKEVENTS
988 select GENERIC_IRQ_CHIP
991 config PLAT_ORION_LEGACY
998 config PLAT_VERSATILE
1001 source "arch/arm/firmware/Kconfig"
1003 source arch/arm/mm/Kconfig
1006 bool "Enable iWMMXt support"
1007 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1008 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1010 Enable support for iWMMXt context switching at run time if
1011 running on a CPU that supports it.
1013 config MULTI_IRQ_HANDLER
1016 Allow each machine to specify it's own IRQ handler at run time.
1019 source "arch/arm/Kconfig-nommu"
1022 config PJ4B_ERRATA_4742
1023 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1024 depends on CPU_PJ4B && MACH_ARMADA_370
1027 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1028 Event (WFE) IDLE states, a specific timing sensitivity exists between
1029 the retiring WFI/WFE instructions and the newly issued subsequent
1030 instructions. This sensitivity can result in a CPU hang scenario.
1032 The software must insert either a Data Synchronization Barrier (DSB)
1033 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1036 config ARM_ERRATA_326103
1037 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1040 Executing a SWP instruction to read-only memory does not set bit 11
1041 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1042 treat the access as a read, preventing a COW from occurring and
1043 causing the faulting task to livelock.
1045 config ARM_ERRATA_411920
1046 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1047 depends on CPU_V6 || CPU_V6K
1049 Invalidation of the Instruction Cache operation can
1050 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1051 It does not affect the MPCore. This option enables the ARM Ltd.
1052 recommended workaround.
1054 config ARM_ERRATA_430973
1055 bool "ARM errata: Stale prediction on replaced interworking branch"
1058 This option enables the workaround for the 430973 Cortex-A8
1059 r1p* erratum. If a code sequence containing an ARM/Thumb
1060 interworking branch is replaced with another code sequence at the
1061 same virtual address, whether due to self-modifying code or virtual
1062 to physical address re-mapping, Cortex-A8 does not recover from the
1063 stale interworking branch prediction. This results in Cortex-A8
1064 executing the new code sequence in the incorrect ARM or Thumb state.
1065 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1066 and also flushes the branch target cache at every context switch.
1067 Note that setting specific bits in the ACTLR register may not be
1068 available in non-secure mode.
1070 config ARM_ERRATA_458693
1071 bool "ARM errata: Processor deadlock when a false hazard is created"
1073 depends on !ARCH_MULTIPLATFORM
1075 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1076 erratum. For very specific sequences of memory operations, it is
1077 possible for a hazard condition intended for a cache line to instead
1078 be incorrectly associated with a different cache line. This false
1079 hazard might then cause a processor deadlock. The workaround enables
1080 the L1 caching of the NEON accesses and disables the PLD instruction
1081 in the ACTLR register. Note that setting specific bits in the ACTLR
1082 register may not be available in non-secure mode.
1084 config ARM_ERRATA_460075
1085 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1087 depends on !ARCH_MULTIPLATFORM
1089 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1090 erratum. Any asynchronous access to the L2 cache may encounter a
1091 situation in which recent store transactions to the L2 cache are lost
1092 and overwritten with stale memory contents from external memory. The
1093 workaround disables the write-allocate mode for the L2 cache via the
1094 ACTLR register. Note that setting specific bits in the ACTLR register
1095 may not be available in non-secure mode.
1097 config ARM_ERRATA_742230
1098 bool "ARM errata: DMB operation may be faulty"
1099 depends on CPU_V7 && SMP
1100 depends on !ARCH_MULTIPLATFORM
1102 This option enables the workaround for the 742230 Cortex-A9
1103 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1104 between two write operations may not ensure the correct visibility
1105 ordering of the two writes. This workaround sets a specific bit in
1106 the diagnostic register of the Cortex-A9 which causes the DMB
1107 instruction to behave as a DSB, ensuring the correct behaviour of
1110 config ARM_ERRATA_742231
1111 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1112 depends on CPU_V7 && SMP
1113 depends on !ARCH_MULTIPLATFORM
1115 This option enables the workaround for the 742231 Cortex-A9
1116 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1117 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1118 accessing some data located in the same cache line, may get corrupted
1119 data due to bad handling of the address hazard when the line gets
1120 replaced from one of the CPUs at the same time as another CPU is
1121 accessing it. This workaround sets specific bits in the diagnostic
1122 register of the Cortex-A9 which reduces the linefill issuing
1123 capabilities of the processor.
1125 config ARM_ERRATA_643719
1126 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1127 depends on CPU_V7 && SMP
1130 This option enables the workaround for the 643719 Cortex-A9 (prior to
1131 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1132 register returns zero when it should return one. The workaround
1133 corrects this value, ensuring cache maintenance operations which use
1134 it behave as intended and avoiding data corruption.
1136 config ARM_ERRATA_720789
1137 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1140 This option enables the workaround for the 720789 Cortex-A9 (prior to
1141 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1142 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1143 As a consequence of this erratum, some TLB entries which should be
1144 invalidated are not, resulting in an incoherency in the system page
1145 tables. The workaround changes the TLB flushing routines to invalidate
1146 entries regardless of the ASID.
1148 config ARM_ERRATA_743622
1149 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1151 depends on !ARCH_MULTIPLATFORM
1153 This option enables the workaround for the 743622 Cortex-A9
1154 (r2p*) erratum. Under very rare conditions, a faulty
1155 optimisation in the Cortex-A9 Store Buffer may lead to data
1156 corruption. This workaround sets a specific bit in the diagnostic
1157 register of the Cortex-A9 which disables the Store Buffer
1158 optimisation, preventing the defect from occurring. This has no
1159 visible impact on the overall performance or power consumption of the
1162 config ARM_ERRATA_751472
1163 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 751472 Cortex-A9 (prior
1168 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1169 completion of a following broadcasted operation if the second
1170 operation is received by a CPU before the ICIALLUIS has completed,
1171 potentially leading to corrupted entries in the cache or TLB.
1173 config ARM_ERRATA_754322
1174 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1177 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1178 r3p*) erratum. A speculative memory access may cause a page table walk
1179 which starts prior to an ASID switch but completes afterwards. This
1180 can populate the micro-TLB with a stale entry which may be hit with
1181 the new ASID. This workaround places two dsb instructions in the mm
1182 switching code so that no page table walks can cross the ASID switch.
1184 config ARM_ERRATA_754327
1185 bool "ARM errata: no automatic Store Buffer drain"
1186 depends on CPU_V7 && SMP
1188 This option enables the workaround for the 754327 Cortex-A9 (prior to
1189 r2p0) erratum. The Store Buffer does not have any automatic draining
1190 mechanism and therefore a livelock may occur if an external agent
1191 continuously polls a memory location waiting to observe an update.
1192 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1193 written polling loops from denying visibility of updates to memory.
1195 config ARM_ERRATA_364296
1196 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1199 This options enables the workaround for the 364296 ARM1136
1200 r0p2 erratum (possible cache data corruption with
1201 hit-under-miss enabled). It sets the undocumented bit 31 in
1202 the auxiliary control register and the FI bit in the control
1203 register, thus disabling hit-under-miss without putting the
1204 processor into full low interrupt latency mode. ARM11MPCore
1207 config ARM_ERRATA_764369
1208 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for erratum 764369
1212 affecting Cortex-A9 MPCore with two or more processors (all
1213 current revisions). Under certain timing circumstances, a data
1214 cache line maintenance operation by MVA targeting an Inner
1215 Shareable memory region may fail to proceed up to either the
1216 Point of Coherency or to the Point of Unification of the
1217 system. This workaround adds a DSB instruction before the
1218 relevant cache maintenance functions and sets a specific bit
1219 in the diagnostic control register of the SCU.
1221 config ARM_ERRATA_775420
1222 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1225 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1226 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1227 operation aborts with MMU exception, it might cause the processor
1228 to deadlock. This workaround puts DSB before executing ISB if
1229 an abort may occur on cache maintenance.
1231 config ARM_ERRATA_798181
1232 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1233 depends on CPU_V7 && SMP
1235 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1236 adequately shooting down all use of the old entries. This
1237 option enables the Linux kernel workaround for this erratum
1238 which sends an IPI to the CPUs that are running the same ASID
1239 as the one being invalidated.
1241 config ARM_ERRATA_773022
1242 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1245 This option enables the workaround for the 773022 Cortex-A15
1246 (up to r0p4) erratum. In certain rare sequences of code, the
1247 loop buffer may deliver incorrect instructions. This
1248 workaround disables the loop buffer to avoid the erratum.
1252 source "arch/arm/common/Kconfig"
1259 Find out whether you have ISA slots on your motherboard. ISA is the
1260 name of a bus system, i.e. the way the CPU talks to the other stuff
1261 inside your box. Other bus systems are PCI, EISA, MicroChannel
1262 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1263 newer boards don't support it. If you have ISA, say Y, otherwise N.
1265 # Select ISA DMA controller support
1270 # Select ISA DMA interface
1275 bool "PCI support" if MIGHT_HAVE_PCI
1277 Find out whether you have a PCI motherboard. PCI is the name of a
1278 bus system, i.e. the way the CPU talks to the other stuff inside
1279 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1280 VESA. If you have PCI, say Y, otherwise N.
1286 config PCI_DOMAINS_GENERIC
1287 def_bool PCI_DOMAINS
1289 config PCI_NANOENGINE
1290 bool "BSE nanoEngine PCI support"
1291 depends on SA1100_NANOENGINE
1293 Enable PCI on the BSE nanoEngine board.
1298 config PCI_HOST_ITE8152
1300 depends on PCI && MACH_ARMCORE
1304 source "drivers/pci/Kconfig"
1305 source "drivers/pci/pcie/Kconfig"
1307 source "drivers/pcmcia/Kconfig"
1311 menu "Kernel Features"
1316 This option should be selected by machines which have an SMP-
1319 The only effect of this option is to make the SMP-related
1320 options available to the user for configuration.
1323 bool "Symmetric Multi-Processing"
1324 depends on CPU_V6K || CPU_V7
1325 depends on GENERIC_CLOCKEVENTS
1327 depends on MMU || ARM_MPU
1330 This enables support for systems with more than one CPU. If you have
1331 a system with only one CPU, say N. If you have a system with more
1332 than one CPU, say Y.
1334 If you say N here, the kernel will run on uni- and multiprocessor
1335 machines, but will use only one CPU of a multiprocessor machine. If
1336 you say Y here, the kernel will run on many, but not all,
1337 uniprocessor machines. On a uniprocessor machine, the kernel
1338 will run faster if you say N here.
1340 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1341 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1342 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1344 If you don't know what to do here, say N.
1347 bool "Allow booting SMP kernel on uniprocessor systems"
1348 depends on SMP && !XIP_KERNEL && MMU
1351 SMP kernels contain instructions which fail on non-SMP processors.
1352 Enabling this option allows the kernel to modify itself to make
1353 these instructions safe. Disabling it allows about 1K of space
1356 If you don't know what to do here, say Y.
1358 config ARM_CPU_TOPOLOGY
1359 bool "Support cpu topology definition"
1360 depends on SMP && CPU_V7
1363 Support ARM cpu topology definition. The MPIDR register defines
1364 affinity between processors which is then used to describe the cpu
1365 topology of an ARM System.
1368 bool "Multi-core scheduler support"
1369 depends on ARM_CPU_TOPOLOGY
1371 Multi-core scheduler support improves the CPU scheduler's decision
1372 making when dealing with multi-core CPU chips at a cost of slightly
1373 increased overhead in some places. If unsure say N here.
1376 bool "SMT scheduler support"
1377 depends on ARM_CPU_TOPOLOGY
1379 Improves the CPU scheduler's decision making when dealing with
1380 MultiThreading at a cost of slightly increased overhead in some
1381 places. If unsure say N here.
1386 This option enables support for the ARM system coherency unit
1388 config HAVE_ARM_ARCH_TIMER
1389 bool "Architected timer support"
1391 select ARM_ARCH_TIMER
1392 select GENERIC_CLOCKEVENTS
1394 This option enables support for the ARM architected timer
1398 select CLKSRC_OF if OF
1400 This options enables support for the ARM timer and watchdog unit
1403 bool "Multi-Cluster Power Management"
1404 depends on CPU_V7 && SMP
1406 This option provides the common power management infrastructure
1407 for (multi-)cluster based systems, such as big.LITTLE based
1410 config MCPM_QUAD_CLUSTER
1414 To avoid wasting resources unnecessarily, MCPM only supports up
1415 to 2 clusters by default.
1416 Platforms with 3 or 4 clusters that use MCPM must select this
1417 option to allow the additional clusters to be managed.
1420 bool "big.LITTLE support (Experimental)"
1421 depends on CPU_V7 && SMP
1424 This option enables support selections for the big.LITTLE
1425 system architecture.
1428 bool "big.LITTLE switcher support"
1429 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1432 The big.LITTLE "switcher" provides the core functionality to
1433 transparently handle transition between a cluster of A15's
1434 and a cluster of A7's in a big.LITTLE system.
1436 config BL_SWITCHER_DUMMY_IF
1437 tristate "Simple big.LITTLE switcher user interface"
1438 depends on BL_SWITCHER && DEBUG_KERNEL
1440 This is a simple and dummy char dev interface to control
1441 the big.LITTLE switcher core code. It is meant for
1442 debugging purposes only.
1445 prompt "Memory split"
1449 Select the desired split between kernel and user memory.
1451 If you are not absolutely sure what you are doing, leave this
1455 bool "3G/1G user/kernel split"
1456 config VMSPLIT_3G_OPT
1457 bool "3G/1G user/kernel split (for full 1G low memory)"
1459 bool "2G/2G user/kernel split"
1461 bool "1G/3G user/kernel split"
1466 default PHYS_OFFSET if !MMU
1467 default 0x40000000 if VMSPLIT_1G
1468 default 0x80000000 if VMSPLIT_2G
1469 default 0xB0000000 if VMSPLIT_3G_OPT
1473 int "Maximum number of CPUs (2-32)"
1479 bool "Support for hot-pluggable CPUs"
1481 select GENERIC_IRQ_MIGRATION
1483 Say Y here to experiment with turning CPUs off and on. CPUs
1484 can be controlled through /sys/devices/system/cpu.
1487 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1488 depends on HAVE_ARM_SMCCC
1491 Say Y here if you want Linux to communicate with system firmware
1492 implementing the PSCI specification for CPU-centric power
1493 management operations described in ARM document number ARM DEN
1494 0022A ("Power State Coordination Interface System Software on
1497 # The GPIO number here must be sorted by descending number. In case of
1498 # a multiplatform kernel, we just want the highest value required by the
1499 # selected platforms.
1502 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1504 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1505 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1506 default 416 if ARCH_SUNXI
1507 default 392 if ARCH_U8500
1508 default 352 if ARCH_VT8500
1509 default 288 if ARCH_ROCKCHIP
1510 default 264 if MACH_H4700
1513 Maximum number of GPIOs in the system.
1515 If unsure, leave the default value.
1517 source kernel/Kconfig.preempt
1521 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1522 ARCH_S5PV210 || ARCH_EXYNOS4
1523 default 128 if SOC_AT91RM9200
1527 depends on HZ_FIXED = 0
1528 prompt "Timer frequency"
1552 default HZ_FIXED if HZ_FIXED != 0
1553 default 100 if HZ_100
1554 default 200 if HZ_200
1555 default 250 if HZ_250
1556 default 300 if HZ_300
1557 default 500 if HZ_500
1561 def_bool HIGH_RES_TIMERS
1563 config THUMB2_KERNEL
1564 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1565 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1566 default y if CPU_THUMBONLY
1568 select ARM_ASM_UNIFIED
1571 By enabling this option, the kernel will be compiled in
1572 Thumb-2 mode. A compiler/assembler that understand the unified
1573 ARM-Thumb syntax is needed.
1577 config THUMB2_AVOID_R_ARM_THM_JUMP11
1578 bool "Work around buggy Thumb-2 short branch relocations in gas"
1579 depends on THUMB2_KERNEL && MODULES
1582 Various binutils versions can resolve Thumb-2 branches to
1583 locally-defined, preemptible global symbols as short-range "b.n"
1584 branch instructions.
1586 This is a problem, because there's no guarantee the final
1587 destination of the symbol, or any candidate locations for a
1588 trampoline, are within range of the branch. For this reason, the
1589 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1590 relocation in modules at all, and it makes little sense to add
1593 The symptom is that the kernel fails with an "unsupported
1594 relocation" error when loading some modules.
1596 Until fixed tools are available, passing
1597 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1598 code which hits this problem, at the cost of a bit of extra runtime
1599 stack usage in some cases.
1601 The problem is described in more detail at:
1602 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1604 Only Thumb-2 kernels are affected.
1606 Unless you are sure your tools don't have this problem, say Y.
1608 config ARM_ASM_UNIFIED
1612 bool "Use the ARM EABI to compile the kernel"
1614 This option allows for the kernel to be compiled using the latest
1615 ARM ABI (aka EABI). This is only useful if you are using a user
1616 space environment that is also compiled with EABI.
1618 Since there are major incompatibilities between the legacy ABI and
1619 EABI, especially with regard to structure member alignment, this
1620 option also changes the kernel syscall calling convention to
1621 disambiguate both ABIs and allow for backward compatibility support
1622 (selected with CONFIG_OABI_COMPAT).
1624 To use this you need GCC version 4.0.0 or later.
1627 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1628 depends on AEABI && !THUMB2_KERNEL
1630 This option preserves the old syscall interface along with the
1631 new (ARM EABI) one. It also provides a compatibility layer to
1632 intercept syscalls that have structure arguments which layout
1633 in memory differs between the legacy ABI and the new ARM EABI
1634 (only for non "thumb" binaries). This option adds a tiny
1635 overhead to all syscalls and produces a slightly larger kernel.
1637 The seccomp filter system will not be available when this is
1638 selected, since there is no way yet to sensibly distinguish
1639 between calling conventions during filtering.
1641 If you know you'll be using only pure EABI user space then you
1642 can say N here. If this option is not selected and you attempt
1643 to execute a legacy ABI binary then the result will be
1644 UNPREDICTABLE (in fact it can be predicted that it won't work
1645 at all). If in doubt say N.
1647 config ARCH_HAS_HOLES_MEMORYMODEL
1650 config ARCH_SPARSEMEM_ENABLE
1653 config ARCH_SPARSEMEM_DEFAULT
1654 def_bool ARCH_SPARSEMEM_ENABLE
1656 config ARCH_SELECT_MEMORY_MODEL
1657 def_bool ARCH_SPARSEMEM_ENABLE
1659 config HAVE_ARCH_PFN_VALID
1660 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1662 config HAVE_GENERIC_RCU_GUP
1667 bool "High Memory Support"
1670 The address space of ARM processors is only 4 Gigabytes large
1671 and it has to accommodate user address space, kernel address
1672 space as well as some memory mapped IO. That means that, if you
1673 have a large amount of physical memory and/or IO, not all of the
1674 memory can be "permanently mapped" by the kernel. The physical
1675 memory that is not permanently mapped is called "high memory".
1677 Depending on the selected kernel/user memory split, minimum
1678 vmalloc space and actual amount of RAM, you may not need this
1679 option which should result in a slightly faster kernel.
1684 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1688 The VM uses one page of physical memory for each page table.
1689 For systems with a lot of processes, this can use a lot of
1690 precious low memory, eventually leading to low memory being
1691 consumed by page tables. Setting this option will allow
1692 user-space 2nd level page tables to reside in high memory.
1694 config CPU_SW_DOMAIN_PAN
1695 bool "Enable use of CPU domains to implement privileged no-access"
1696 depends on MMU && !ARM_LPAE
1699 Increase kernel security by ensuring that normal kernel accesses
1700 are unable to access userspace addresses. This can help prevent
1701 use-after-free bugs becoming an exploitable privilege escalation
1702 by ensuring that magic values (such as LIST_POISON) will always
1703 fault when dereferenced.
1705 CPUs with low-vector mappings use a best-efforts implementation.
1706 Their lower 1MB needs to remain accessible for the vectors, but
1707 the remainder of userspace will become appropriately inaccessible.
1709 config HW_PERF_EVENTS
1713 config SYS_SUPPORTS_HUGETLBFS
1717 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1721 config ARCH_WANT_GENERAL_HUGETLB
1724 config ARM_MODULE_PLTS
1725 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1728 Allocate PLTs when loading modules so that jumps and calls whose
1729 targets are too far away for their relative offsets to be encoded
1730 in the instructions themselves can be bounced via veneers in the
1731 module's PLT. This allows modules to be allocated in the generic
1732 vmalloc area after the dedicated module memory area has been
1733 exhausted. The modules will use slightly more memory, but after
1734 rounding up to page size, the actual memory footprint is usually
1737 Say y if you are getting out of memory errors while loading modules
1741 config FORCE_MAX_ZONEORDER
1742 int "Maximum zone order"
1743 default "12" if SOC_AM33XX
1744 default "9" if SA1111 || ARCH_EFM32
1747 The kernel memory allocator divides physically contiguous memory
1748 blocks into "zones", where each zone is a power of two number of
1749 pages. This option selects the largest power of two that the kernel
1750 keeps in the memory allocator. If you need to allocate very large
1751 blocks of physically contiguous memory, then you may need to
1752 increase this value.
1754 This config option is actually maximum order plus one. For example,
1755 a value of 11 means that the largest free memory block is 2^10 pages.
1757 config ALIGNMENT_TRAP
1759 depends on CPU_CP15_MMU
1760 default y if !ARCH_EBSA110
1761 select HAVE_PROC_CPU if PROC_FS
1763 ARM processors cannot fetch/store information which is not
1764 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1765 address divisible by 4. On 32-bit ARM processors, these non-aligned
1766 fetch/store instructions will be emulated in software if you say
1767 here, which has a severe performance impact. This is necessary for
1768 correct operation of some network protocols. With an IP-only
1769 configuration it is safe to say N, otherwise say Y.
1771 config UACCESS_WITH_MEMCPY
1772 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1774 default y if CPU_FEROCEON
1776 Implement faster copy_to_user and clear_user methods for CPU
1777 cores where a 8-word STM instruction give significantly higher
1778 memory write throughput than a sequence of individual 32bit stores.
1780 A possible side effect is a slight increase in scheduling latency
1781 between threads sharing the same address space if they invoke
1782 such copy operations with large buffers.
1784 However, if the CPU data cache is using a write-allocate mode,
1785 this option is unlikely to provide any performance gain.
1789 prompt "Enable seccomp to safely compute untrusted bytecode"
1791 This kernel feature is useful for number crunching applications
1792 that may need to compute untrusted bytecode during their
1793 execution. By using pipes or other transports made available to
1794 the process as file descriptors supporting the read/write
1795 syscalls, it's possible to isolate those applications in
1796 their own address space using seccomp. Once seccomp is
1797 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1798 and the task is only allowed to execute a few safe syscalls
1799 defined by each seccomp mode.
1812 bool "Xen guest support on ARM"
1813 depends on ARM && AEABI && OF
1814 depends on CPU_V7 && !CPU_V6
1815 depends on !GENERIC_ATOMIC64
1817 select ARCH_DMA_ADDR_T_64BIT
1821 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1828 bool "Flattened Device Tree support"
1832 Include support for flattened device tree machine descriptions.
1835 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1838 This is the traditional way of passing data to the kernel at boot
1839 time. If you are solely relying on the flattened device tree (or
1840 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841 to remove ATAGS support from your kernel binary. If unsure,
1844 config DEPRECATED_PARAM_STRUCT
1845 bool "Provide old way to pass kernel parameters"
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1851 # Compressed boot loader in ROM. Yes, we really want to ask about
1852 # TEXT and BSS so we preserve their values in the config files.
1853 config ZBOOT_ROM_TEXT
1854 hex "Compressed ROM boot loader base address"
1857 The physical address at which the ROM-able zImage is to be
1858 placed in the target. Platforms which normally make use of
1859 ROM-able zImage formats normally set this to a suitable
1860 value in their defconfig file.
1862 If ZBOOT_ROM is not enabled, this has no effect.
1864 config ZBOOT_ROM_BSS
1865 hex "Compressed ROM boot loader BSS address"
1868 The base address of an area of read/write memory in the target
1869 for the ROM-able zImage which must be available while the
1870 decompressor is running. It must be large enough to hold the
1871 entire decompressed kernel plus an additional 128 KiB.
1872 Platforms which normally make use of ROM-able zImage formats
1873 normally set this to a suitable value in their defconfig file.
1875 If ZBOOT_ROM is not enabled, this has no effect.
1878 bool "Compressed boot loader in ROM/flash"
1879 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1880 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1885 config ARM_APPENDED_DTB
1886 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1889 With this option, the boot code will look for a device tree binary
1890 (DTB) appended to zImage
1891 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1893 This is meant as a backward compatibility convenience for those
1894 systems with a bootloader that can't be upgraded to accommodate
1895 the documented boot protocol using a device tree.
1897 Beware that there is very little in terms of protection against
1898 this option being confused by leftover garbage in memory that might
1899 look like a DTB header after a reboot if no actual DTB is appended
1900 to zImage. Do not leave this option active in a production kernel
1901 if you don't intend to always append a DTB. Proper passing of the
1902 location into r2 of a bootloader provided DTB is always preferable
1905 config ARM_ATAG_DTB_COMPAT
1906 bool "Supplement the appended DTB with traditional ATAG information"
1907 depends on ARM_APPENDED_DTB
1909 Some old bootloaders can't be updated to a DTB capable one, yet
1910 they provide ATAGs with memory configuration, the ramdisk address,
1911 the kernel cmdline string, etc. Such information is dynamically
1912 provided by the bootloader and can't always be stored in a static
1913 DTB. To allow a device tree enabled kernel to be used with such
1914 bootloaders, this option allows zImage to extract the information
1915 from the ATAG list and store it at run time into the appended DTB.
1918 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1919 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922 bool "Use bootloader kernel arguments if available"
1924 Uses the command-line options passed by the boot loader instead of
1925 the device tree bootargs property. If the boot loader doesn't provide
1926 any, the device tree bootargs property will be used.
1928 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1929 bool "Extend with bootloader kernel arguments"
1931 The command-line arguments provided by the boot loader will be
1932 appended to the the device tree bootargs property.
1937 string "Default kernel command string"
1940 On some architectures (EBSA110 and CATS), there is currently no way
1941 for the boot loader to pass arguments to the kernel. For these
1942 architectures, you should supply some command-line options at build
1943 time by entering them here. As a minimum, you should specify the
1944 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1947 prompt "Kernel command line type" if CMDLINE != ""
1948 default CMDLINE_FROM_BOOTLOADER
1951 config CMDLINE_FROM_BOOTLOADER
1952 bool "Use bootloader kernel arguments if available"
1954 Uses the command-line options passed by the boot loader. If
1955 the boot loader doesn't provide any, the default kernel command
1956 string provided in CMDLINE will be used.
1958 config CMDLINE_EXTEND
1959 bool "Extend bootloader kernel arguments"
1961 The command-line arguments provided by the boot loader will be
1962 appended to the default kernel command string.
1964 config CMDLINE_FORCE
1965 bool "Always use the default kernel command string"
1967 Always use the default kernel command string, even if the boot
1968 loader passes other arguments to the kernel.
1969 This is useful if you cannot or don't want to change the
1970 command-line options your boot loader passes to the kernel.
1974 bool "Kernel Execute-In-Place from ROM"
1975 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1977 Execute-In-Place allows the kernel to run from non-volatile storage
1978 directly addressable by the CPU, such as NOR flash. This saves RAM
1979 space since the text section of the kernel is not loaded from flash
1980 to RAM. Read-write sections, such as the data section and stack,
1981 are still copied to RAM. The XIP kernel is not compressed since
1982 it has to run directly from flash, so it will take more space to
1983 store it. The flash address used to link the kernel object files,
1984 and for storing it, is configuration dependent. Therefore, if you
1985 say Y here, you must know the proper physical address where to
1986 store the kernel image depending on your own flash memory usage.
1988 Also note that the make target becomes "make xipImage" rather than
1989 "make zImage" or "make Image". The final kernel binary to put in
1990 ROM memory will be arch/arm/boot/xipImage.
1994 config XIP_PHYS_ADDR
1995 hex "XIP Kernel Physical Location"
1996 depends on XIP_KERNEL
1997 default "0x00080000"
1999 This is the physical address in your flash memory the kernel will
2000 be linked for and stored to. This address is dependent on your
2004 bool "Kexec system call (EXPERIMENTAL)"
2005 depends on (!SMP || PM_SLEEP_SMP)
2009 kexec is a system call that implements the ability to shutdown your
2010 current kernel, and to start another kernel. It is like a reboot
2011 but it is independent of the system firmware. And like a reboot
2012 you can start any kernel with it, not just Linux.
2014 It is an ongoing process to be certain the hardware in a machine
2015 is properly shutdown, so do not be surprised if this code does not
2016 initially work for you.
2019 bool "Export atags in procfs"
2020 depends on ATAGS && KEXEC
2023 Should the atags used to boot the kernel be exported in an "atags"
2024 file in procfs. Useful with kexec.
2027 bool "Build kdump crash kernel (EXPERIMENTAL)"
2029 Generate crash dump after being started by kexec. This should
2030 be normally only set in special crash dump kernels which are
2031 loaded in the main kernel with kexec-tools into a specially
2032 reserved region and then later executed after a crash by
2033 kdump/kexec. The crash dump kernel must be compiled to a
2034 memory address not used by the main kernel
2036 For more details see Documentation/kdump/kdump.txt
2038 config AUTO_ZRELADDR
2039 bool "Auto calculation of the decompressed kernel image address"
2041 ZRELADDR is the physical address where the decompressed kernel
2042 image will be placed. If AUTO_ZRELADDR is selected, the address
2043 will be determined at run-time by masking the current IP with
2044 0xf8000000. This assumes the zImage being placed in the first 128MB
2045 from start of memory.
2049 menu "CPU Power Management"
2051 source "drivers/cpufreq/Kconfig"
2053 source "drivers/cpuidle/Kconfig"
2057 menu "Floating point emulation"
2059 comment "At least one emulation must be selected"
2062 bool "NWFPE math emulation"
2063 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2065 Say Y to include the NWFPE floating point emulator in the kernel.
2066 This is necessary to run most binaries. Linux does not currently
2067 support floating point hardware so you need to say Y here even if
2068 your machine has an FPA or floating point co-processor podule.
2070 You may say N here if you are going to load the Acorn FPEmulator
2071 early in the bootup.
2074 bool "Support extended precision"
2075 depends on FPE_NWFPE
2077 Say Y to include 80-bit support in the kernel floating-point
2078 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2079 Note that gcc does not generate 80-bit operations by default,
2080 so in most cases this option only enlarges the size of the
2081 floating point emulator without any good reason.
2083 You almost surely want to say N here.
2086 bool "FastFPE math emulation (EXPERIMENTAL)"
2087 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2089 Say Y here to include the FAST floating point emulator in the kernel.
2090 This is an experimental much faster emulator which now also has full
2091 precision for the mantissa. It does not support any exceptions.
2092 It is very simple, and approximately 3-6 times faster than NWFPE.
2094 It should be sufficient for most programs. It may be not suitable
2095 for scientific calculations, but you have to check this for yourself.
2096 If you do not feel you need a faster FP emulation you should better
2100 bool "VFP-format floating point maths"
2101 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2103 Say Y to include VFP support code in the kernel. This is needed
2104 if your hardware includes a VFP unit.
2106 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2107 release notes and additional status information.
2109 Say N if your target does not have VFP hardware.
2117 bool "Advanced SIMD (NEON) Extension support"
2118 depends on VFPv3 && CPU_V7
2120 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2123 config KERNEL_MODE_NEON
2124 bool "Support for NEON in kernel mode"
2125 depends on NEON && AEABI
2127 Say Y to include support for NEON in kernel mode.
2131 menu "Userspace binary formats"
2133 source "fs/Kconfig.binfmt"
2137 menu "Power management options"
2139 source "kernel/power/Kconfig"
2141 config ARCH_SUSPEND_POSSIBLE
2142 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2143 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2146 config ARM_CPU_SUSPEND
2147 def_bool PM_SLEEP || BL_SWITCHER
2148 depends on ARCH_SUSPEND_POSSIBLE
2150 config ARCH_HIBERNATION_POSSIBLE
2153 default y if ARCH_SUSPEND_POSSIBLE
2157 source "net/Kconfig"
2159 source "drivers/Kconfig"
2161 source "drivers/firmware/Kconfig"
2165 source "arch/arm/Kconfig.debug"
2167 source "security/Kconfig"
2169 source "crypto/Kconfig"
2171 source "arch/arm/crypto/Kconfig"
2174 source "lib/Kconfig"
2176 source "arch/arm/kvm/Kconfig"