1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DEVMEM_IS_ALLOWED
11 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
13 select ARCH_HAS_ELF_RANDOMIZE
14 select ARCH_HAS_FORTIFY_SOURCE
15 select ARCH_HAS_KEEPINITRD
17 select ARCH_HAS_MEMBARRIER_SYNC_CORE
18 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
19 select ARCH_HAS_PHYS_TO_DMA
20 select ARCH_HAS_SETUP_DMA_OPS
21 select ARCH_HAS_SET_MEMORY
22 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
23 select ARCH_HAS_STRICT_MODULE_RWX if MMU
24 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
25 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
26 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
28 select ARCH_HAVE_CUSTOM_GPIO_H
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_MIGHT_HAVE_PC_PARPORT
32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_USE_BUILTIN_BSWAP
37 select ARCH_USE_CMPXCHG_LOCKREF
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
41 select BUILDTIME_EXTABLE_SORT if MMU
42 select CLONE_BACKWARDS
43 select CPU_PM if SUSPEND || CPU_IDLE
44 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
45 select DMA_DECLARE_COHERENT
46 select DMA_REMAP if MMU
48 select EDAC_ATOMIC_SCRUB
49 select GENERIC_ALLOCATOR
50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
53 select GENERIC_CPU_AUTOPROBE
54 select GENERIC_EARLY_IOREMAP
55 select GENERIC_IDLE_POLL_SETUP
56 select GENERIC_IRQ_PROBE
57 select GENERIC_IRQ_SHOW
58 select GENERIC_IRQ_SHOW_LEVEL
59 select GENERIC_PCI_IOMAP
60 select GENERIC_SCHED_CLOCK
61 select GENERIC_SMP_IDLE_THREAD
62 select GENERIC_STRNCPY_FROM_USER
63 select GENERIC_STRNLEN_USER
64 select HANDLE_DOMAIN_IRQ
65 select HARDIRQS_SW_RESEND
66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
70 select HAVE_ARCH_MMAP_RND_BITS if MMU
71 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
72 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
73 select HAVE_ARCH_TRACEHOOK
74 select HAVE_ARM_SMCCC if CPU_V7
75 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
76 select HAVE_CONTEXT_TRACKING
77 select HAVE_COPY_THREAD_TLS
78 select HAVE_C_RECORDMCOUNT
79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
80 select HAVE_DMA_CONTIGUOUS if MMU
81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
84 select HAVE_EXIT_THREAD
85 select HAVE_FAST_GUP if ARM_LPAE
86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
89 select HAVE_FUTEX_CMPXCHG if FUTEX
90 select HAVE_GCC_PLUGINS
91 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
92 select HAVE_IDE if PCI || ISA || PCMCIA
93 select HAVE_IRQ_TIME_ACCOUNTING
94 select HAVE_KERNEL_GZIP
95 select HAVE_KERNEL_LZ4
96 select HAVE_KERNEL_LZMA
97 select HAVE_KERNEL_LZO
99 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
100 select HAVE_KRETPROBES if HAVE_KPROBES
101 select HAVE_MOD_ARCH_SPECIFIC
103 select HAVE_OPROFILE if HAVE_PERF_EVENTS
104 select HAVE_OPTPROBES if !THUMB2_KERNEL
105 select HAVE_PERF_EVENTS
106 select HAVE_PERF_REGS
107 select HAVE_PERF_USER_STACK_DUMP
108 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
109 select HAVE_REGS_AND_STACK_ACCESS_API
111 select HAVE_STACKPROTECTOR
112 select HAVE_SYSCALL_TRACEPOINTS
114 select HAVE_VIRT_CPU_ACCOUNTING_GEN
115 select IRQ_FORCED_THREADING
116 select MODULES_USE_ELF_REL
117 select NEED_DMA_MAP_STATE
118 select OF_EARLY_FLATTREE if OF
120 select OLD_SIGSUSPEND3
121 select PCI_SYSCALL if PCI
122 select PERF_USE_VMALLOC
124 select SYS_SUPPORTS_APM_EMULATION
125 # Above selects are sorted alphabetically; please add new ones
126 # according to that. Thanks.
128 The ARM series is a line of low-power-consumption RISC chip designs
129 licensed by ARM Ltd and targeted at embedded applications and
130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
131 manufactured, but legacy ARM-based PC hardware remains popular in
132 Europe. There is an ARM Linux project with a web page at
133 <http://www.arm.linux.org.uk/>.
135 config ARM_HAS_SG_CHAIN
138 config ARM_DMA_USE_IOMMU
140 select ARM_HAS_SG_CHAIN
141 select NEED_SG_DMA_LENGTH
145 config ARM_DMA_IOMMU_ALIGNMENT
146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
150 DMA mapping framework by default aligns all buffers to the smallest
151 PAGE_SIZE order which is greater than or equal to the requested buffer
152 size. This works well for buffers up to a few hundreds kilobytes, but
153 for larger buffers it just a waste of address space. Drivers which has
154 relatively small addressing window (like 64Mib) might run out of
155 virtual space with just a few allocations.
157 With this parameter you can specify the maximum PAGE_SIZE order for
158 DMA IOMMU buffers. Larger buffers will be aligned only to this
159 specified order. The order is expressed as a power of two multiplied
164 config SYS_SUPPORTS_APM_EMULATION
169 select GENERIC_ALLOCATOR
180 config STACKTRACE_SUPPORT
184 config LOCKDEP_SUPPORT
188 config TRACE_IRQFLAGS_SUPPORT
192 config ARCH_HAS_ILOG2_U32
195 config ARCH_HAS_ILOG2_U64
198 config ARCH_HAS_BANDGAP
201 config FIX_EARLYCON_MEM
204 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
212 config ARCH_MAY_HAVE_PC_FDC
218 config ARCH_SUPPORTS_UPROBES
221 config ARCH_HAS_DMA_SET_COHERENT_MASK
224 config GENERIC_ISA_DMA
230 config NEED_RET_TO_USER
236 config ARM_PATCH_PHYS_VIRT
237 bool "Patch physical to virtual translations at runtime" if EMBEDDED
239 depends on !XIP_KERNEL && MMU
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT
269 default DRAM_BASE if !MMU
270 default 0x00000000 if ARCH_EBSA110 || \
274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
275 default 0x20000000 if ARCH_S5PV210
276 default 0xc0000000 if ARCH_SA1100
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 config PGTABLE_LEVELS
287 default 3 if ARM_LPAE
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
299 config ARCH_MMAP_RND_BITS_MIN
302 config ARCH_MMAP_RND_BITS_MAX
303 default 14 if PAGE_OFFSET=0x40000000
304 default 15 if PAGE_OFFSET=0x80000000
308 # The "ARM system type" choice list is ordered alphabetically by option
309 # text. Please add new entries in the option alphabetic order.
312 prompt "ARM system type"
313 default ARM_SINGLE_ARMV7M if !MMU
314 default ARCH_MULTIPLATFORM if MMU
316 config ARCH_MULTIPLATFORM
317 bool "Allow multiple platforms to be selected"
319 select ARM_HAS_SG_CHAIN
320 select ARM_PATCH_PHYS_VIRT
324 select GENERIC_CLOCKEVENTS
325 select GENERIC_IRQ_MULTI_HANDLER
327 select PCI_DOMAINS_GENERIC if PCI
331 config ARM_SINGLE_ARMV7M
332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
339 select GENERIC_CLOCKEVENTS
346 select ARCH_USES_GETTIMEOFFSET
349 select NEED_MACH_IO_H
350 select NEED_MACH_MEMORY_H
353 This is an evaluation board for the StrongARM processor available
354 from Digital. It has limited hardware on-board, including an
355 Ethernet interface, two PCMCIA sockets, two serial ports and a
360 select ARCH_SPARSEMEM_ENABLE
362 imply ARM_PATCH_PHYS_VIRT
368 select GENERIC_CLOCKEVENTS
371 This enables support for the Cirrus EP93xx series of CPUs.
373 config ARCH_FOOTBRIDGE
377 select GENERIC_CLOCKEVENTS
379 select NEED_MACH_IO_H if !MMU
380 select NEED_MACH_MEMORY_H
382 Support for systems based on the DC21285 companion chip
383 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
391 select NEED_RET_TO_USER
395 Support for Intel's 80219 and IOP32X (XScale) family of
401 select ARCH_HAS_DMA_SET_COHERENT_MASK
402 select ARCH_SUPPORTS_BIG_ENDIAN
404 select DMABOUNCE if PCI
405 select GENERIC_CLOCKEVENTS
406 select GENERIC_IRQ_MULTI_HANDLER
412 select NEED_MACH_IO_H
413 select USB_EHCI_BIG_ENDIAN_DESC
414 select USB_EHCI_BIG_ENDIAN_MMIO
416 Support for Intel's IXP4XX (XScale) family of processors.
421 select GENERIC_CLOCKEVENTS
422 select GENERIC_IRQ_MULTI_HANDLER
428 select PLAT_ORION_LEGACY
430 select PM_GENERIC_DOMAINS if PM
432 Support for the Marvell Dove SoC 88AP510
435 bool "PXA2xx/PXA3xx-based"
438 select ARM_CPU_SUSPEND if PM
445 select CPU_XSCALE if !CPU_XSC3
446 select GENERIC_CLOCKEVENTS
447 select GENERIC_IRQ_MULTI_HANDLER
455 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
461 select ARCH_MAY_HAVE_PC_FDC
462 select ARCH_SPARSEMEM_ENABLE
463 select ARM_HAS_SG_CHAIN
467 select HAVE_PATA_PLATFORM
469 select NEED_MACH_IO_H
470 select NEED_MACH_MEMORY_H
473 On the Acorn Risc-PC, Linux can support the internal IDE disk and
474 CD-ROM interface, serial and parallel port, and the floppy drive.
479 select ARCH_SPARSEMEM_ENABLE
483 select TIMER_OF if OF
487 select GENERIC_CLOCKEVENTS
488 select GENERIC_IRQ_MULTI_HANDLER
493 select NEED_MACH_MEMORY_H
496 Support for StrongARM 11x0 based boards.
499 bool "Samsung S3C24XX SoCs"
502 select CLKSRC_SAMSUNG_PWM
503 select GENERIC_CLOCKEVENTS
506 select GENERIC_IRQ_MULTI_HANDLER
507 select HAVE_S3C2410_I2C if I2C
508 select HAVE_S3C2410_WATCHDOG if WATCHDOG
509 select HAVE_S3C_RTC if RTC_CLASS
510 select NEED_MACH_IO_H
511 select S3C2410_WATCHDOG
516 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
517 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
518 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
519 Samsung SMDK2410 development board (and derivatives).
527 select GENERIC_CLOCKEVENTS
528 select GENERIC_IRQ_CHIP
529 select GENERIC_IRQ_MULTI_HANDLER
533 select NEED_MACH_IO_H if PCCARD
534 select NEED_MACH_MEMORY_H
537 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
541 menu "Multiple platform selection"
542 depends on ARCH_MULTIPLATFORM
544 comment "CPU Core family selection"
547 bool "ARMv4 based platforms (FA526)"
548 depends on !ARCH_MULTI_V6_V7
549 select ARCH_MULTI_V4_V5
552 config ARCH_MULTI_V4T
553 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
554 depends on !ARCH_MULTI_V6_V7
555 select ARCH_MULTI_V4_V5
556 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
557 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
558 CPU_ARM925T || CPU_ARM940T)
561 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
562 depends on !ARCH_MULTI_V6_V7
563 select ARCH_MULTI_V4_V5
564 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
565 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
566 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
568 config ARCH_MULTI_V4_V5
572 bool "ARMv6 based platforms (ARM11)"
573 select ARCH_MULTI_V6_V7
577 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
579 select ARCH_MULTI_V6_V7
583 config ARCH_MULTI_V6_V7
585 select MIGHT_HAVE_CACHE_L2X0
587 config ARCH_MULTI_CPU_AUTO
588 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
594 bool "Dummy Virtual Machine"
595 depends on ARCH_MULTI_V7
598 select ARM_GIC_V2M if PCI
600 select ARM_GIC_V3_ITS if PCI
602 select HAVE_ARM_ARCH_TIMER
603 select ARCH_SUPPORTS_BIG_ENDIAN
606 # This is sorted alphabetically by mach-* pathname. However, plat-*
607 # Kconfigs may be included either alphabetically (according to the
608 # plat- suffix) or along side the corresponding mach-* source.
610 source "arch/arm/mach-actions/Kconfig"
612 source "arch/arm/mach-alpine/Kconfig"
614 source "arch/arm/mach-artpec/Kconfig"
616 source "arch/arm/mach-asm9260/Kconfig"
618 source "arch/arm/mach-aspeed/Kconfig"
620 source "arch/arm/mach-at91/Kconfig"
622 source "arch/arm/mach-axxia/Kconfig"
624 source "arch/arm/mach-bcm/Kconfig"
626 source "arch/arm/mach-berlin/Kconfig"
628 source "arch/arm/mach-clps711x/Kconfig"
630 source "arch/arm/mach-cns3xxx/Kconfig"
632 source "arch/arm/mach-davinci/Kconfig"
634 source "arch/arm/mach-digicolor/Kconfig"
636 source "arch/arm/mach-dove/Kconfig"
638 source "arch/arm/mach-ep93xx/Kconfig"
640 source "arch/arm/mach-exynos/Kconfig"
641 source "arch/arm/plat-samsung/Kconfig"
643 source "arch/arm/mach-footbridge/Kconfig"
645 source "arch/arm/mach-gemini/Kconfig"
647 source "arch/arm/mach-highbank/Kconfig"
649 source "arch/arm/mach-hisi/Kconfig"
651 source "arch/arm/mach-imx/Kconfig"
653 source "arch/arm/mach-integrator/Kconfig"
655 source "arch/arm/mach-iop32x/Kconfig"
657 source "arch/arm/mach-ixp4xx/Kconfig"
659 source "arch/arm/mach-keystone/Kconfig"
661 source "arch/arm/mach-lpc32xx/Kconfig"
663 source "arch/arm/mach-mediatek/Kconfig"
665 source "arch/arm/mach-meson/Kconfig"
667 source "arch/arm/mach-milbeaut/Kconfig"
669 source "arch/arm/mach-mmp/Kconfig"
671 source "arch/arm/mach-moxart/Kconfig"
673 source "arch/arm/mach-mv78xx0/Kconfig"
675 source "arch/arm/mach-mvebu/Kconfig"
677 source "arch/arm/mach-mxs/Kconfig"
679 source "arch/arm/mach-nomadik/Kconfig"
681 source "arch/arm/mach-npcm/Kconfig"
683 source "arch/arm/mach-nspire/Kconfig"
685 source "arch/arm/plat-omap/Kconfig"
687 source "arch/arm/mach-omap1/Kconfig"
689 source "arch/arm/mach-omap2/Kconfig"
691 source "arch/arm/mach-orion5x/Kconfig"
693 source "arch/arm/mach-oxnas/Kconfig"
695 source "arch/arm/mach-picoxcell/Kconfig"
697 source "arch/arm/mach-prima2/Kconfig"
699 source "arch/arm/mach-pxa/Kconfig"
700 source "arch/arm/plat-pxa/Kconfig"
702 source "arch/arm/mach-qcom/Kconfig"
704 source "arch/arm/mach-rda/Kconfig"
706 source "arch/arm/mach-realview/Kconfig"
708 source "arch/arm/mach-rockchip/Kconfig"
710 source "arch/arm/mach-s3c24xx/Kconfig"
712 source "arch/arm/mach-s3c64xx/Kconfig"
714 source "arch/arm/mach-s5pv210/Kconfig"
716 source "arch/arm/mach-sa1100/Kconfig"
718 source "arch/arm/mach-shmobile/Kconfig"
720 source "arch/arm/mach-socfpga/Kconfig"
722 source "arch/arm/mach-spear/Kconfig"
724 source "arch/arm/mach-sti/Kconfig"
726 source "arch/arm/mach-stm32/Kconfig"
728 source "arch/arm/mach-sunxi/Kconfig"
730 source "arch/arm/mach-tango/Kconfig"
732 source "arch/arm/mach-tegra/Kconfig"
734 source "arch/arm/mach-u300/Kconfig"
736 source "arch/arm/mach-uniphier/Kconfig"
738 source "arch/arm/mach-ux500/Kconfig"
740 source "arch/arm/mach-versatile/Kconfig"
742 source "arch/arm/mach-vexpress/Kconfig"
743 source "arch/arm/plat-versatile/Kconfig"
745 source "arch/arm/mach-vt8500/Kconfig"
747 source "arch/arm/mach-zx/Kconfig"
749 source "arch/arm/mach-zynq/Kconfig"
751 # ARMv7-M architecture
753 bool "Energy Micro efm32"
754 depends on ARM_SINGLE_ARMV7M
757 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
761 bool "NXP LPC18xx/LPC43xx"
762 depends on ARM_SINGLE_ARMV7M
763 select ARCH_HAS_RESET_CONTROLLER
765 select CLKSRC_LPC32XX
768 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
769 high performance microcontrollers.
772 bool "ARM MPS2 platform"
773 depends on ARM_SINGLE_ARMV7M
777 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
778 with a range of available cores like Cortex-M3/M4/M7.
780 Please, note that depends which Application Note is used memory map
781 for the platform may vary, so adjustment of RAM base might be needed.
783 # Definitions to make life easier
789 select GENERIC_CLOCKEVENTS
795 select GENERIC_IRQ_CHIP
798 config PLAT_ORION_LEGACY
805 config PLAT_VERSATILE
808 source "arch/arm/mm/Kconfig"
811 bool "Enable iWMMXt support"
812 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
813 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
815 Enable support for iWMMXt context switching at run time if
816 running on a CPU that supports it.
819 source "arch/arm/Kconfig-nommu"
822 config PJ4B_ERRATA_4742
823 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
824 depends on CPU_PJ4B && MACH_ARMADA_370
827 When coming out of either a Wait for Interrupt (WFI) or a Wait for
828 Event (WFE) IDLE states, a specific timing sensitivity exists between
829 the retiring WFI/WFE instructions and the newly issued subsequent
830 instructions. This sensitivity can result in a CPU hang scenario.
832 The software must insert either a Data Synchronization Barrier (DSB)
833 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
836 config ARM_ERRATA_326103
837 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
840 Executing a SWP instruction to read-only memory does not set bit 11
841 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
842 treat the access as a read, preventing a COW from occurring and
843 causing the faulting task to livelock.
845 config ARM_ERRATA_411920
846 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
847 depends on CPU_V6 || CPU_V6K
849 Invalidation of the Instruction Cache operation can
850 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
851 It does not affect the MPCore. This option enables the ARM Ltd.
852 recommended workaround.
854 config ARM_ERRATA_430973
855 bool "ARM errata: Stale prediction on replaced interworking branch"
858 This option enables the workaround for the 430973 Cortex-A8
859 r1p* erratum. If a code sequence containing an ARM/Thumb
860 interworking branch is replaced with another code sequence at the
861 same virtual address, whether due to self-modifying code or virtual
862 to physical address re-mapping, Cortex-A8 does not recover from the
863 stale interworking branch prediction. This results in Cortex-A8
864 executing the new code sequence in the incorrect ARM or Thumb state.
865 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
866 and also flushes the branch target cache at every context switch.
867 Note that setting specific bits in the ACTLR register may not be
868 available in non-secure mode.
870 config ARM_ERRATA_458693
871 bool "ARM errata: Processor deadlock when a false hazard is created"
873 depends on !ARCH_MULTIPLATFORM
875 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
876 erratum. For very specific sequences of memory operations, it is
877 possible for a hazard condition intended for a cache line to instead
878 be incorrectly associated with a different cache line. This false
879 hazard might then cause a processor deadlock. The workaround enables
880 the L1 caching of the NEON accesses and disables the PLD instruction
881 in the ACTLR register. Note that setting specific bits in the ACTLR
882 register may not be available in non-secure mode.
884 config ARM_ERRATA_460075
885 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
887 depends on !ARCH_MULTIPLATFORM
889 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
890 erratum. Any asynchronous access to the L2 cache may encounter a
891 situation in which recent store transactions to the L2 cache are lost
892 and overwritten with stale memory contents from external memory. The
893 workaround disables the write-allocate mode for the L2 cache via the
894 ACTLR register. Note that setting specific bits in the ACTLR register
895 may not be available in non-secure mode.
897 config ARM_ERRATA_742230
898 bool "ARM errata: DMB operation may be faulty"
899 depends on CPU_V7 && SMP
900 depends on !ARCH_MULTIPLATFORM
902 This option enables the workaround for the 742230 Cortex-A9
903 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
904 between two write operations may not ensure the correct visibility
905 ordering of the two writes. This workaround sets a specific bit in
906 the diagnostic register of the Cortex-A9 which causes the DMB
907 instruction to behave as a DSB, ensuring the correct behaviour of
910 config ARM_ERRATA_742231
911 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
912 depends on CPU_V7 && SMP
913 depends on !ARCH_MULTIPLATFORM
915 This option enables the workaround for the 742231 Cortex-A9
916 (r2p0..r2p2) erratum. Under certain conditions, specific to the
917 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
918 accessing some data located in the same cache line, may get corrupted
919 data due to bad handling of the address hazard when the line gets
920 replaced from one of the CPUs at the same time as another CPU is
921 accessing it. This workaround sets specific bits in the diagnostic
922 register of the Cortex-A9 which reduces the linefill issuing
923 capabilities of the processor.
925 config ARM_ERRATA_643719
926 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
927 depends on CPU_V7 && SMP
930 This option enables the workaround for the 643719 Cortex-A9 (prior to
931 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
932 register returns zero when it should return one. The workaround
933 corrects this value, ensuring cache maintenance operations which use
934 it behave as intended and avoiding data corruption.
936 config ARM_ERRATA_720789
937 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
940 This option enables the workaround for the 720789 Cortex-A9 (prior to
941 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
942 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
943 As a consequence of this erratum, some TLB entries which should be
944 invalidated are not, resulting in an incoherency in the system page
945 tables. The workaround changes the TLB flushing routines to invalidate
946 entries regardless of the ASID.
948 config ARM_ERRATA_743622
949 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
951 depends on !ARCH_MULTIPLATFORM
953 This option enables the workaround for the 743622 Cortex-A9
954 (r2p*) erratum. Under very rare conditions, a faulty
955 optimisation in the Cortex-A9 Store Buffer may lead to data
956 corruption. This workaround sets a specific bit in the diagnostic
957 register of the Cortex-A9 which disables the Store Buffer
958 optimisation, preventing the defect from occurring. This has no
959 visible impact on the overall performance or power consumption of the
962 config ARM_ERRATA_751472
963 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
965 depends on !ARCH_MULTIPLATFORM
967 This option enables the workaround for the 751472 Cortex-A9 (prior
968 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
969 completion of a following broadcasted operation if the second
970 operation is received by a CPU before the ICIALLUIS has completed,
971 potentially leading to corrupted entries in the cache or TLB.
973 config ARM_ERRATA_754322
974 bool "ARM errata: possible faulty MMU translations following an ASID switch"
977 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
978 r3p*) erratum. A speculative memory access may cause a page table walk
979 which starts prior to an ASID switch but completes afterwards. This
980 can populate the micro-TLB with a stale entry which may be hit with
981 the new ASID. This workaround places two dsb instructions in the mm
982 switching code so that no page table walks can cross the ASID switch.
984 config ARM_ERRATA_754327
985 bool "ARM errata: no automatic Store Buffer drain"
986 depends on CPU_V7 && SMP
988 This option enables the workaround for the 754327 Cortex-A9 (prior to
989 r2p0) erratum. The Store Buffer does not have any automatic draining
990 mechanism and therefore a livelock may occur if an external agent
991 continuously polls a memory location waiting to observe an update.
992 This workaround defines cpu_relax() as smp_mb(), preventing correctly
993 written polling loops from denying visibility of updates to memory.
995 config ARM_ERRATA_364296
996 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
999 This options enables the workaround for the 364296 ARM1136
1000 r0p2 erratum (possible cache data corruption with
1001 hit-under-miss enabled). It sets the undocumented bit 31 in
1002 the auxiliary control register and the FI bit in the control
1003 register, thus disabling hit-under-miss without putting the
1004 processor into full low interrupt latency mode. ARM11MPCore
1007 config ARM_ERRATA_764369
1008 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1009 depends on CPU_V7 && SMP
1011 This option enables the workaround for erratum 764369
1012 affecting Cortex-A9 MPCore with two or more processors (all
1013 current revisions). Under certain timing circumstances, a data
1014 cache line maintenance operation by MVA targeting an Inner
1015 Shareable memory region may fail to proceed up to either the
1016 Point of Coherency or to the Point of Unification of the
1017 system. This workaround adds a DSB instruction before the
1018 relevant cache maintenance functions and sets a specific bit
1019 in the diagnostic control register of the SCU.
1021 config ARM_ERRATA_775420
1022 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1025 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1026 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1027 operation aborts with MMU exception, it might cause the processor
1028 to deadlock. This workaround puts DSB before executing ISB if
1029 an abort may occur on cache maintenance.
1031 config ARM_ERRATA_798181
1032 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1033 depends on CPU_V7 && SMP
1035 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1036 adequately shooting down all use of the old entries. This
1037 option enables the Linux kernel workaround for this erratum
1038 which sends an IPI to the CPUs that are running the same ASID
1039 as the one being invalidated.
1041 config ARM_ERRATA_773022
1042 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1045 This option enables the workaround for the 773022 Cortex-A15
1046 (up to r0p4) erratum. In certain rare sequences of code, the
1047 loop buffer may deliver incorrect instructions. This
1048 workaround disables the loop buffer to avoid the erratum.
1050 config ARM_ERRATA_818325_852422
1051 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1054 This option enables the workaround for:
1055 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1056 instruction might deadlock. Fixed in r0p1.
1057 - Cortex-A12 852422: Execution of a sequence of instructions might
1058 lead to either a data corruption or a CPU deadlock. Not fixed in
1059 any Cortex-A12 cores yet.
1060 This workaround for all both errata involves setting bit[12] of the
1061 Feature Register. This bit disables an optimisation applied to a
1062 sequence of 2 instructions that use opposing condition codes.
1064 config ARM_ERRATA_821420
1065 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1068 This option enables the workaround for the 821420 Cortex-A12
1069 (all revs) erratum. In very rare timing conditions, a sequence
1070 of VMOV to Core registers instructions, for which the second
1071 one is in the shadow of a branch or abort, can lead to a
1072 deadlock when the VMOV instructions are issued out-of-order.
1074 config ARM_ERRATA_825619
1075 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1078 This option enables the workaround for the 825619 Cortex-A12
1079 (all revs) erratum. Within rare timing constraints, executing a
1080 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1081 and Device/Strongly-Ordered loads and stores might cause deadlock
1083 config ARM_ERRATA_857271
1084 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1087 This option enables the workaround for the 857271 Cortex-A12
1088 (all revs) erratum. Under very rare timing conditions, the CPU might
1089 hang. The workaround is expected to have a < 1% performance impact.
1091 config ARM_ERRATA_852421
1092 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1095 This option enables the workaround for the 852421 Cortex-A17
1096 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1097 execution of a DMB ST instruction might fail to properly order
1098 stores from GroupA and stores from GroupB.
1100 config ARM_ERRATA_852423
1101 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1104 This option enables the workaround for:
1105 - Cortex-A17 852423: Execution of a sequence of instructions might
1106 lead to either a data corruption or a CPU deadlock. Not fixed in
1107 any Cortex-A17 cores yet.
1108 This is identical to Cortex-A12 erratum 852422. It is a separate
1109 config option from the A12 erratum due to the way errata are checked
1112 config ARM_ERRATA_857272
1113 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1116 This option enables the workaround for the 857272 Cortex-A17 erratum.
1117 This erratum is not known to be fixed in any A17 revision.
1118 This is identical to Cortex-A12 erratum 857271. It is a separate
1119 config option from the A12 erratum due to the way errata are checked
1124 source "arch/arm/common/Kconfig"
1131 Find out whether you have ISA slots on your motherboard. ISA is the
1132 name of a bus system, i.e. the way the CPU talks to the other stuff
1133 inside your box. Other bus systems are PCI, EISA, MicroChannel
1134 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1135 newer boards don't support it. If you have ISA, say Y, otherwise N.
1137 # Select ISA DMA controller support
1142 # Select ISA DMA interface
1146 config PCI_NANOENGINE
1147 bool "BSE nanoEngine PCI support"
1148 depends on SA1100_NANOENGINE
1150 Enable PCI on the BSE nanoEngine board.
1152 config PCI_HOST_ITE8152
1154 depends on PCI && MACH_ARMCORE
1158 config ARM_ERRATA_814220
1159 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1162 The v7 ARM states that all cache and branch predictor maintenance
1163 operations that do not specify an address execute, relative to
1164 each other, in program order.
1165 However, because of this erratum, an L2 set/way cache maintenance
1166 operation can overtake an L1 set/way cache maintenance operation.
1167 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1172 menu "Kernel Features"
1177 This option should be selected by machines which have an SMP-
1180 The only effect of this option is to make the SMP-related
1181 options available to the user for configuration.
1184 bool "Symmetric Multi-Processing"
1185 depends on CPU_V6K || CPU_V7
1186 depends on GENERIC_CLOCKEVENTS
1188 depends on MMU || ARM_MPU
1191 This enables support for systems with more than one CPU. If you have
1192 a system with only one CPU, say N. If you have a system with more
1193 than one CPU, say Y.
1195 If you say N here, the kernel will run on uni- and multiprocessor
1196 machines, but will use only one CPU of a multiprocessor machine. If
1197 you say Y here, the kernel will run on many, but not all,
1198 uniprocessor machines. On a uniprocessor machine, the kernel
1199 will run faster if you say N here.
1201 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1202 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1203 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1205 If you don't know what to do here, say N.
1208 bool "Allow booting SMP kernel on uniprocessor systems"
1209 depends on SMP && !XIP_KERNEL && MMU
1212 SMP kernels contain instructions which fail on non-SMP processors.
1213 Enabling this option allows the kernel to modify itself to make
1214 these instructions safe. Disabling it allows about 1K of space
1217 If you don't know what to do here, say Y.
1219 config ARM_CPU_TOPOLOGY
1220 bool "Support cpu topology definition"
1221 depends on SMP && CPU_V7
1224 Support ARM cpu topology definition. The MPIDR register defines
1225 affinity between processors which is then used to describe the cpu
1226 topology of an ARM System.
1229 bool "Multi-core scheduler support"
1230 depends on ARM_CPU_TOPOLOGY
1232 Multi-core scheduler support improves the CPU scheduler's decision
1233 making when dealing with multi-core CPU chips at a cost of slightly
1234 increased overhead in some places. If unsure say N here.
1237 bool "SMT scheduler support"
1238 depends on ARM_CPU_TOPOLOGY
1240 Improves the CPU scheduler's decision making when dealing with
1241 MultiThreading at a cost of slightly increased overhead in some
1242 places. If unsure say N here.
1247 This option enables support for the ARM snoop control unit
1249 config HAVE_ARM_ARCH_TIMER
1250 bool "Architected timer support"
1252 select ARM_ARCH_TIMER
1253 select GENERIC_CLOCKEVENTS
1255 This option enables support for the ARM architected timer
1260 This options enables support for the ARM timer and watchdog unit
1263 bool "Multi-Cluster Power Management"
1264 depends on CPU_V7 && SMP
1266 This option provides the common power management infrastructure
1267 for (multi-)cluster based systems, such as big.LITTLE based
1270 config MCPM_QUAD_CLUSTER
1274 To avoid wasting resources unnecessarily, MCPM only supports up
1275 to 2 clusters by default.
1276 Platforms with 3 or 4 clusters that use MCPM must select this
1277 option to allow the additional clusters to be managed.
1280 bool "big.LITTLE support (Experimental)"
1281 depends on CPU_V7 && SMP
1284 This option enables support selections for the big.LITTLE
1285 system architecture.
1288 bool "big.LITTLE switcher support"
1289 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1292 The big.LITTLE "switcher" provides the core functionality to
1293 transparently handle transition between a cluster of A15's
1294 and a cluster of A7's in a big.LITTLE system.
1296 config BL_SWITCHER_DUMMY_IF
1297 tristate "Simple big.LITTLE switcher user interface"
1298 depends on BL_SWITCHER && DEBUG_KERNEL
1300 This is a simple and dummy char dev interface to control
1301 the big.LITTLE switcher core code. It is meant for
1302 debugging purposes only.
1305 prompt "Memory split"
1309 Select the desired split between kernel and user memory.
1311 If you are not absolutely sure what you are doing, leave this
1315 bool "3G/1G user/kernel split"
1316 config VMSPLIT_3G_OPT
1317 depends on !ARM_LPAE
1318 bool "3G/1G user/kernel split (for full 1G low memory)"
1320 bool "2G/2G user/kernel split"
1322 bool "1G/3G user/kernel split"
1327 default PHYS_OFFSET if !MMU
1328 default 0x40000000 if VMSPLIT_1G
1329 default 0x80000000 if VMSPLIT_2G
1330 default 0xB0000000 if VMSPLIT_3G_OPT
1334 int "Maximum number of CPUs (2-32)"
1340 bool "Support for hot-pluggable CPUs"
1342 select GENERIC_IRQ_MIGRATION
1344 Say Y here to experiment with turning CPUs off and on. CPUs
1345 can be controlled through /sys/devices/system/cpu.
1348 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1349 depends on HAVE_ARM_SMCCC
1352 Say Y here if you want Linux to communicate with system firmware
1353 implementing the PSCI specification for CPU-centric power
1354 management operations described in ARM document number ARM DEN
1355 0022A ("Power State Coordination Interface System Software on
1358 # The GPIO number here must be sorted by descending number. In case of
1359 # a multiplatform kernel, we just want the highest value required by the
1360 # selected platforms.
1363 default 2048 if ARCH_SOCFPGA
1364 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1366 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1367 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1368 default 416 if ARCH_SUNXI
1369 default 392 if ARCH_U8500
1370 default 352 if ARCH_VT8500
1371 default 288 if ARCH_ROCKCHIP
1372 default 264 if MACH_H4700
1375 Maximum number of GPIOs in the system.
1377 If unsure, leave the default value.
1381 default 200 if ARCH_EBSA110
1382 default 128 if SOC_AT91RM9200
1386 depends on HZ_FIXED = 0
1387 prompt "Timer frequency"
1411 default HZ_FIXED if HZ_FIXED != 0
1412 default 100 if HZ_100
1413 default 200 if HZ_200
1414 default 250 if HZ_250
1415 default 300 if HZ_300
1416 default 500 if HZ_500
1420 def_bool HIGH_RES_TIMERS
1422 config THUMB2_KERNEL
1423 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1424 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1425 default y if CPU_THUMBONLY
1428 By enabling this option, the kernel will be compiled in
1433 config THUMB2_AVOID_R_ARM_THM_JUMP11
1434 bool "Work around buggy Thumb-2 short branch relocations in gas"
1435 depends on THUMB2_KERNEL && MODULES
1438 Various binutils versions can resolve Thumb-2 branches to
1439 locally-defined, preemptible global symbols as short-range "b.n"
1440 branch instructions.
1442 This is a problem, because there's no guarantee the final
1443 destination of the symbol, or any candidate locations for a
1444 trampoline, are within range of the branch. For this reason, the
1445 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1446 relocation in modules at all, and it makes little sense to add
1449 The symptom is that the kernel fails with an "unsupported
1450 relocation" error when loading some modules.
1452 Until fixed tools are available, passing
1453 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1454 code which hits this problem, at the cost of a bit of extra runtime
1455 stack usage in some cases.
1457 The problem is described in more detail at:
1458 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1460 Only Thumb-2 kernels are affected.
1462 Unless you are sure your tools don't have this problem, say Y.
1464 config ARM_PATCH_IDIV
1465 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1466 depends on CPU_32v7 && !XIP_KERNEL
1469 The ARM compiler inserts calls to __aeabi_idiv() and
1470 __aeabi_uidiv() when it needs to perform division on signed
1471 and unsigned integers. Some v7 CPUs have support for the sdiv
1472 and udiv instructions that can be used to implement those
1475 Enabling this option allows the kernel to modify itself to
1476 replace the first two instructions of these library functions
1477 with the sdiv or udiv plus "bx lr" instructions when the CPU
1478 it is running on supports them. Typically this will be faster
1479 and less power intensive than running the original library
1480 code to do integer division.
1483 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1484 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1485 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1487 This option allows for the kernel to be compiled using the latest
1488 ARM ABI (aka EABI). This is only useful if you are using a user
1489 space environment that is also compiled with EABI.
1491 Since there are major incompatibilities between the legacy ABI and
1492 EABI, especially with regard to structure member alignment, this
1493 option also changes the kernel syscall calling convention to
1494 disambiguate both ABIs and allow for backward compatibility support
1495 (selected with CONFIG_OABI_COMPAT).
1497 To use this you need GCC version 4.0.0 or later.
1500 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1501 depends on AEABI && !THUMB2_KERNEL
1503 This option preserves the old syscall interface along with the
1504 new (ARM EABI) one. It also provides a compatibility layer to
1505 intercept syscalls that have structure arguments which layout
1506 in memory differs between the legacy ABI and the new ARM EABI
1507 (only for non "thumb" binaries). This option adds a tiny
1508 overhead to all syscalls and produces a slightly larger kernel.
1510 The seccomp filter system will not be available when this is
1511 selected, since there is no way yet to sensibly distinguish
1512 between calling conventions during filtering.
1514 If you know you'll be using only pure EABI user space then you
1515 can say N here. If this option is not selected and you attempt
1516 to execute a legacy ABI binary then the result will be
1517 UNPREDICTABLE (in fact it can be predicted that it won't work
1518 at all). If in doubt say N.
1520 config ARCH_SPARSEMEM_ENABLE
1523 config ARCH_SPARSEMEM_DEFAULT
1524 def_bool ARCH_SPARSEMEM_ENABLE
1526 config HAVE_ARCH_PFN_VALID
1530 bool "High Memory Support"
1533 The address space of ARM processors is only 4 Gigabytes large
1534 and it has to accommodate user address space, kernel address
1535 space as well as some memory mapped IO. That means that, if you
1536 have a large amount of physical memory and/or IO, not all of the
1537 memory can be "permanently mapped" by the kernel. The physical
1538 memory that is not permanently mapped is called "high memory".
1540 Depending on the selected kernel/user memory split, minimum
1541 vmalloc space and actual amount of RAM, you may not need this
1542 option which should result in a slightly faster kernel.
1547 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1551 The VM uses one page of physical memory for each page table.
1552 For systems with a lot of processes, this can use a lot of
1553 precious low memory, eventually leading to low memory being
1554 consumed by page tables. Setting this option will allow
1555 user-space 2nd level page tables to reside in high memory.
1557 config CPU_SW_DOMAIN_PAN
1558 bool "Enable use of CPU domains to implement privileged no-access"
1559 depends on MMU && !ARM_LPAE
1562 Increase kernel security by ensuring that normal kernel accesses
1563 are unable to access userspace addresses. This can help prevent
1564 use-after-free bugs becoming an exploitable privilege escalation
1565 by ensuring that magic values (such as LIST_POISON) will always
1566 fault when dereferenced.
1568 CPUs with low-vector mappings use a best-efforts implementation.
1569 Their lower 1MB needs to remain accessible for the vectors, but
1570 the remainder of userspace will become appropriately inaccessible.
1572 config HW_PERF_EVENTS
1576 config SYS_SUPPORTS_HUGETLBFS
1580 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1584 config ARCH_WANT_GENERAL_HUGETLB
1587 config ARM_MODULE_PLTS
1588 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1592 Allocate PLTs when loading modules so that jumps and calls whose
1593 targets are too far away for their relative offsets to be encoded
1594 in the instructions themselves can be bounced via veneers in the
1595 module's PLT. This allows modules to be allocated in the generic
1596 vmalloc area after the dedicated module memory area has been
1597 exhausted. The modules will use slightly more memory, but after
1598 rounding up to page size, the actual memory footprint is usually
1601 Disabling this is usually safe for small single-platform
1602 configurations. If unsure, say y.
1604 config FORCE_MAX_ZONEORDER
1605 int "Maximum zone order"
1606 default "12" if SOC_AM33XX
1607 default "9" if SA1111 || ARCH_EFM32
1610 The kernel memory allocator divides physically contiguous memory
1611 blocks into "zones", where each zone is a power of two number of
1612 pages. This option selects the largest power of two that the kernel
1613 keeps in the memory allocator. If you need to allocate very large
1614 blocks of physically contiguous memory, then you may need to
1615 increase this value.
1617 This config option is actually maximum order plus one. For example,
1618 a value of 11 means that the largest free memory block is 2^10 pages.
1620 config ALIGNMENT_TRAP
1622 depends on CPU_CP15_MMU
1623 default y if !ARCH_EBSA110
1624 select HAVE_PROC_CPU if PROC_FS
1626 ARM processors cannot fetch/store information which is not
1627 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1628 address divisible by 4. On 32-bit ARM processors, these non-aligned
1629 fetch/store instructions will be emulated in software if you say
1630 here, which has a severe performance impact. This is necessary for
1631 correct operation of some network protocols. With an IP-only
1632 configuration it is safe to say N, otherwise say Y.
1634 config UACCESS_WITH_MEMCPY
1635 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1637 default y if CPU_FEROCEON
1639 Implement faster copy_to_user and clear_user methods for CPU
1640 cores where a 8-word STM instruction give significantly higher
1641 memory write throughput than a sequence of individual 32bit stores.
1643 A possible side effect is a slight increase in scheduling latency
1644 between threads sharing the same address space if they invoke
1645 such copy operations with large buffers.
1647 However, if the CPU data cache is using a write-allocate mode,
1648 this option is unlikely to provide any performance gain.
1652 prompt "Enable seccomp to safely compute untrusted bytecode"
1654 This kernel feature is useful for number crunching applications
1655 that may need to compute untrusted bytecode during their
1656 execution. By using pipes or other transports made available to
1657 the process as file descriptors supporting the read/write
1658 syscalls, it's possible to isolate those applications in
1659 their own address space using seccomp. Once seccomp is
1660 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1661 and the task is only allowed to execute a few safe syscalls
1662 defined by each seccomp mode.
1665 bool "Enable paravirtualization code"
1667 This changes the kernel so it can modify itself when it is run
1668 under a hypervisor, potentially improving performance significantly
1669 over full virtualization.
1671 config PARAVIRT_TIME_ACCOUNTING
1672 bool "Paravirtual steal time accounting"
1675 Select this option to enable fine granularity task steal time
1676 accounting. Time spent executing other tasks in parallel with
1677 the current vCPU is discounted from the vCPU power. To account for
1678 that, there can be a small performance impact.
1680 If in doubt, say N here.
1687 bool "Xen guest support on ARM"
1688 depends on ARM && AEABI && OF
1689 depends on CPU_V7 && !CPU_V6
1690 depends on !GENERIC_ATOMIC64
1692 select ARCH_DMA_ADDR_T_64BIT
1698 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1700 config STACKPROTECTOR_PER_TASK
1701 bool "Use a unique stack canary value for each task"
1702 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1703 select GCC_PLUGIN_ARM_SSP_PER_TASK
1706 Due to the fact that GCC uses an ordinary symbol reference from
1707 which to load the value of the stack canary, this value can only
1708 change at reboot time on SMP systems, and all tasks running in the
1709 kernel's address space are forced to use the same canary value for
1710 the entire duration that the system is up.
1712 Enable this option to switch to a different method that uses a
1713 different canary value for each task.
1720 bool "Flattened Device Tree support"
1724 Include support for flattened device tree machine descriptions.
1727 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1730 This is the traditional way of passing data to the kernel at boot
1731 time. If you are solely relying on the flattened device tree (or
1732 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1733 to remove ATAGS support from your kernel binary. If unsure,
1736 config DEPRECATED_PARAM_STRUCT
1737 bool "Provide old way to pass kernel parameters"
1740 This was deprecated in 2001 and announced to live on for 5 years.
1741 Some old boot loaders still use this way.
1743 # Compressed boot loader in ROM. Yes, we really want to ask about
1744 # TEXT and BSS so we preserve their values in the config files.
1745 config ZBOOT_ROM_TEXT
1746 hex "Compressed ROM boot loader base address"
1749 The physical address at which the ROM-able zImage is to be
1750 placed in the target. Platforms which normally make use of
1751 ROM-able zImage formats normally set this to a suitable
1752 value in their defconfig file.
1754 If ZBOOT_ROM is not enabled, this has no effect.
1756 config ZBOOT_ROM_BSS
1757 hex "Compressed ROM boot loader BSS address"
1760 The base address of an area of read/write memory in the target
1761 for the ROM-able zImage which must be available while the
1762 decompressor is running. It must be large enough to hold the
1763 entire decompressed kernel plus an additional 128 KiB.
1764 Platforms which normally make use of ROM-able zImage formats
1765 normally set this to a suitable value in their defconfig file.
1767 If ZBOOT_ROM is not enabled, this has no effect.
1770 bool "Compressed boot loader in ROM/flash"
1771 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1772 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1774 Say Y here if you intend to execute your compressed kernel image
1775 (zImage) directly from ROM or flash. If unsure, say N.
1777 config ARM_APPENDED_DTB
1778 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1781 With this option, the boot code will look for a device tree binary
1782 (DTB) appended to zImage
1783 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1785 This is meant as a backward compatibility convenience for those
1786 systems with a bootloader that can't be upgraded to accommodate
1787 the documented boot protocol using a device tree.
1789 Beware that there is very little in terms of protection against
1790 this option being confused by leftover garbage in memory that might
1791 look like a DTB header after a reboot if no actual DTB is appended
1792 to zImage. Do not leave this option active in a production kernel
1793 if you don't intend to always append a DTB. Proper passing of the
1794 location into r2 of a bootloader provided DTB is always preferable
1797 config ARM_ATAG_DTB_COMPAT
1798 bool "Supplement the appended DTB with traditional ATAG information"
1799 depends on ARM_APPENDED_DTB
1801 Some old bootloaders can't be updated to a DTB capable one, yet
1802 they provide ATAGs with memory configuration, the ramdisk address,
1803 the kernel cmdline string, etc. Such information is dynamically
1804 provided by the bootloader and can't always be stored in a static
1805 DTB. To allow a device tree enabled kernel to be used with such
1806 bootloaders, this option allows zImage to extract the information
1807 from the ATAG list and store it at run time into the appended DTB.
1810 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1811 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1813 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1814 bool "Use bootloader kernel arguments if available"
1816 Uses the command-line options passed by the boot loader instead of
1817 the device tree bootargs property. If the boot loader doesn't provide
1818 any, the device tree bootargs property will be used.
1820 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1821 bool "Extend with bootloader kernel arguments"
1823 The command-line arguments provided by the boot loader will be
1824 appended to the the device tree bootargs property.
1829 string "Default kernel command string"
1832 On some architectures (EBSA110 and CATS), there is currently no way
1833 for the boot loader to pass arguments to the kernel. For these
1834 architectures, you should supply some command-line options at build
1835 time by entering them here. As a minimum, you should specify the
1836 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1839 prompt "Kernel command line type" if CMDLINE != ""
1840 default CMDLINE_FROM_BOOTLOADER
1842 config CMDLINE_FROM_BOOTLOADER
1843 bool "Use bootloader kernel arguments if available"
1845 Uses the command-line options passed by the boot loader. If
1846 the boot loader doesn't provide any, the default kernel command
1847 string provided in CMDLINE will be used.
1849 config CMDLINE_EXTEND
1850 bool "Extend bootloader kernel arguments"
1852 The command-line arguments provided by the boot loader will be
1853 appended to the default kernel command string.
1855 config CMDLINE_FORCE
1856 bool "Always use the default kernel command string"
1858 Always use the default kernel command string, even if the boot
1859 loader passes other arguments to the kernel.
1860 This is useful if you cannot or don't want to change the
1861 command-line options your boot loader passes to the kernel.
1865 bool "Kernel Execute-In-Place from ROM"
1866 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1868 Execute-In-Place allows the kernel to run from non-volatile storage
1869 directly addressable by the CPU, such as NOR flash. This saves RAM
1870 space since the text section of the kernel is not loaded from flash
1871 to RAM. Read-write sections, such as the data section and stack,
1872 are still copied to RAM. The XIP kernel is not compressed since
1873 it has to run directly from flash, so it will take more space to
1874 store it. The flash address used to link the kernel object files,
1875 and for storing it, is configuration dependent. Therefore, if you
1876 say Y here, you must know the proper physical address where to
1877 store the kernel image depending on your own flash memory usage.
1879 Also note that the make target becomes "make xipImage" rather than
1880 "make zImage" or "make Image". The final kernel binary to put in
1881 ROM memory will be arch/arm/boot/xipImage.
1885 config XIP_PHYS_ADDR
1886 hex "XIP Kernel Physical Location"
1887 depends on XIP_KERNEL
1888 default "0x00080000"
1890 This is the physical address in your flash memory the kernel will
1891 be linked for and stored to. This address is dependent on your
1894 config XIP_DEFLATED_DATA
1895 bool "Store kernel .data section compressed in ROM"
1896 depends on XIP_KERNEL
1899 Before the kernel is actually executed, its .data section has to be
1900 copied to RAM from ROM. This option allows for storing that data
1901 in compressed form and decompressed to RAM rather than merely being
1902 copied, saving some precious ROM space. A possible drawback is a
1903 slightly longer boot delay.
1906 bool "Kexec system call (EXPERIMENTAL)"
1907 depends on (!SMP || PM_SLEEP_SMP)
1911 kexec is a system call that implements the ability to shutdown your
1912 current kernel, and to start another kernel. It is like a reboot
1913 but it is independent of the system firmware. And like a reboot
1914 you can start any kernel with it, not just Linux.
1916 It is an ongoing process to be certain the hardware in a machine
1917 is properly shutdown, so do not be surprised if this code does not
1918 initially work for you.
1921 bool "Export atags in procfs"
1922 depends on ATAGS && KEXEC
1925 Should the atags used to boot the kernel be exported in an "atags"
1926 file in procfs. Useful with kexec.
1929 bool "Build kdump crash kernel (EXPERIMENTAL)"
1931 Generate crash dump after being started by kexec. This should
1932 be normally only set in special crash dump kernels which are
1933 loaded in the main kernel with kexec-tools into a specially
1934 reserved region and then later executed after a crash by
1935 kdump/kexec. The crash dump kernel must be compiled to a
1936 memory address not used by the main kernel
1938 For more details see Documentation/admin-guide/kdump/kdump.rst
1940 config AUTO_ZRELADDR
1941 bool "Auto calculation of the decompressed kernel image address"
1943 ZRELADDR is the physical address where the decompressed kernel
1944 image will be placed. If AUTO_ZRELADDR is selected, the address
1945 will be determined at run-time by masking the current IP with
1946 0xf8000000. This assumes the zImage being placed in the first 128MB
1947 from start of memory.
1953 bool "UEFI runtime support"
1954 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1956 select EFI_PARAMS_FROM_FDT
1959 select EFI_RUNTIME_WRAPPERS
1961 This option provides support for runtime services provided
1962 by UEFI firmware (such as non-volatile variables, realtime
1963 clock, and platform reset). A UEFI stub is also provided to
1964 allow the kernel to be booted as an EFI application. This
1965 is only useful for kernels that may run on systems that have
1969 bool "Enable support for SMBIOS (DMI) tables"
1973 This enables SMBIOS/DMI feature for systems.
1975 This option is only useful on systems that have UEFI firmware.
1976 However, even with this option, the resultant kernel should
1977 continue to boot on existing non-UEFI platforms.
1979 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1980 i.e., the the practice of identifying the platform via DMI to
1981 decide whether certain workarounds for buggy hardware and/or
1982 firmware need to be enabled. This would require the DMI subsystem
1983 to be enabled much earlier than we do on ARM, which is non-trivial.
1987 menu "CPU Power Management"
1989 source "drivers/cpufreq/Kconfig"
1991 source "drivers/cpuidle/Kconfig"
1995 menu "Floating point emulation"
1997 comment "At least one emulation must be selected"
2000 bool "NWFPE math emulation"
2001 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2003 Say Y to include the NWFPE floating point emulator in the kernel.
2004 This is necessary to run most binaries. Linux does not currently
2005 support floating point hardware so you need to say Y here even if
2006 your machine has an FPA or floating point co-processor podule.
2008 You may say N here if you are going to load the Acorn FPEmulator
2009 early in the bootup.
2012 bool "Support extended precision"
2013 depends on FPE_NWFPE
2015 Say Y to include 80-bit support in the kernel floating-point
2016 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2017 Note that gcc does not generate 80-bit operations by default,
2018 so in most cases this option only enlarges the size of the
2019 floating point emulator without any good reason.
2021 You almost surely want to say N here.
2024 bool "FastFPE math emulation (EXPERIMENTAL)"
2025 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2027 Say Y here to include the FAST floating point emulator in the kernel.
2028 This is an experimental much faster emulator which now also has full
2029 precision for the mantissa. It does not support any exceptions.
2030 It is very simple, and approximately 3-6 times faster than NWFPE.
2032 It should be sufficient for most programs. It may be not suitable
2033 for scientific calculations, but you have to check this for yourself.
2034 If you do not feel you need a faster FP emulation you should better
2038 bool "VFP-format floating point maths"
2039 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2041 Say Y to include VFP support code in the kernel. This is needed
2042 if your hardware includes a VFP unit.
2044 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2045 release notes and additional status information.
2047 Say N if your target does not have VFP hardware.
2055 bool "Advanced SIMD (NEON) Extension support"
2056 depends on VFPv3 && CPU_V7
2058 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2061 config KERNEL_MODE_NEON
2062 bool "Support for NEON in kernel mode"
2063 depends on NEON && AEABI
2065 Say Y to include support for NEON in kernel mode.
2069 menu "Power management options"
2071 source "kernel/power/Kconfig"
2073 config ARCH_SUSPEND_POSSIBLE
2074 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2075 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2078 config ARM_CPU_SUSPEND
2079 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2080 depends on ARCH_SUSPEND_POSSIBLE
2082 config ARCH_HIBERNATION_POSSIBLE
2085 default y if ARCH_SUSPEND_POSSIBLE
2089 source "drivers/firmware/Kconfig"
2092 source "arch/arm/crypto/Kconfig"
2095 source "arch/arm/kvm/Kconfig"