4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_HARDENED_USERCOPY
39 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
41 select HAVE_ARCH_MMAP_RND_BITS if MMU
42 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
43 select HAVE_ARCH_TRACEHOOK
44 select HAVE_ARM_SMCCC if CPU_V7
46 select HAVE_CC_STACKPROTECTOR
47 select HAVE_CONTEXT_TRACKING
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_DEBUG_KMEMLEAK
50 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_CONTIGUOUS if MMU
52 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
53 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
54 select HAVE_EXIT_THREAD
55 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
56 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
57 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
58 select HAVE_FUTEX_CMPXCHG if FUTEX
59 select HAVE_GCC_PLUGINS
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
62 select HAVE_IDE if PCI || ISA || PCMCIA
63 select HAVE_IRQ_TIME_ACCOUNTING
64 select HAVE_KERNEL_GZIP
65 select HAVE_KERNEL_LZ4
66 select HAVE_KERNEL_LZMA
67 select HAVE_KERNEL_LZO
69 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
70 select HAVE_KRETPROBES if (HAVE_KPROBES)
72 select HAVE_MOD_ARCH_SPECIFIC
74 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
75 select HAVE_OPTPROBES if !THUMB2_KERNEL
76 select HAVE_PERF_EVENTS
78 select HAVE_PERF_USER_STACK_DUMP
79 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
80 select HAVE_REGS_AND_STACK_ACCESS_API
81 select HAVE_SYSCALL_TRACEPOINTS
83 select HAVE_VIRT_CPU_ACCOUNTING_GEN
84 select IRQ_FORCED_THREADING
85 select MODULES_USE_ELF_REL
87 select OF_EARLY_FLATTREE if OF
88 select OF_RESERVED_MEM if OF
90 select OLD_SIGSUSPEND3
91 select PERF_USE_VMALLOC
93 select SYS_SUPPORTS_APM_EMULATION
94 # Above selects are sorted alphabetically; please add new ones
95 # according to that. Thanks.
97 The ARM series is a line of low-power-consumption RISC chip designs
98 licensed by ARM Ltd and targeted at embedded applications and
99 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
100 manufactured, but legacy ARM-based PC hardware remains popular in
101 Europe. There is an ARM Linux project with a web page at
102 <http://www.arm.linux.org.uk/>.
104 config ARM_HAS_SG_CHAIN
105 select ARCH_HAS_SG_CHAIN
108 config NEED_SG_DMA_LENGTH
111 config ARM_DMA_USE_IOMMU
113 select ARM_HAS_SG_CHAIN
114 select NEED_SG_DMA_LENGTH
118 config ARM_DMA_IOMMU_ALIGNMENT
119 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
123 DMA mapping framework by default aligns all buffers to the smallest
124 PAGE_SIZE order which is greater than or equal to the requested buffer
125 size. This works well for buffers up to a few hundreds kilobytes, but
126 for larger buffers it just a waste of address space. Drivers which has
127 relatively small addressing window (like 64Mib) might run out of
128 virtual space with just a few allocations.
130 With this parameter you can specify the maximum PAGE_SIZE order for
131 DMA IOMMU buffers. Larger buffers will be aligned only to this
132 specified order. The order is expressed as a power of two multiplied
137 config MIGHT_HAVE_PCI
140 config SYS_SUPPORTS_APM_EMULATION
145 select GENERIC_ALLOCATOR
156 The Extended Industry Standard Architecture (EISA) bus was
157 developed as an open alternative to the IBM MicroChannel bus.
159 The EISA bus provided some of the features of the IBM MicroChannel
160 bus while maintaining backward compatibility with cards made for
161 the older ISA bus. The EISA bus saw limited use between 1988 and
162 1995 when it was made obsolete by the PCI bus.
164 Say Y here if you are building a kernel for an EISA-based machine.
171 config STACKTRACE_SUPPORT
175 config LOCKDEP_SUPPORT
179 config TRACE_IRQFLAGS_SUPPORT
183 config RWSEM_XCHGADD_ALGORITHM
187 config ARCH_HAS_ILOG2_U32
190 config ARCH_HAS_ILOG2_U64
193 config ARCH_HAS_BANDGAP
196 config FIX_EARLYCON_MEM
199 config GENERIC_HWEIGHT
203 config GENERIC_CALIBRATE_DELAY
207 config ARCH_MAY_HAVE_PC_FDC
213 config NEED_DMA_MAP_STATE
216 config ARCH_SUPPORTS_UPROBES
219 config ARCH_HAS_DMA_SET_COHERENT_MASK
222 config GENERIC_ISA_DMA
228 config NEED_RET_TO_USER
236 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
237 default DRAM_BASE if REMAP_VECTORS_TO_RAM
240 The base address of exception vectors. This must be two pages
243 config ARM_PATCH_PHYS_VIRT
244 bool "Patch physical to virtual translations at runtime" if EMBEDDED
246 depends on !XIP_KERNEL && MMU
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0xc0000000 if ARCH_SA1100
287 Please provide the physical address corresponding to the
288 location of main memory in your system.
294 config PGTABLE_LEVELS
296 default 3 if ARM_LPAE
299 source "init/Kconfig"
301 source "kernel/Kconfig.freezer"
306 bool "MMU-based Paged Memory Management Support"
309 Select if you want MMU-based virtualised addressing space
310 support by paged memory management. If unsure, say 'Y'.
312 config ARCH_MMAP_RND_BITS_MIN
315 config ARCH_MMAP_RND_BITS_MAX
316 default 14 if PAGE_OFFSET=0x40000000
317 default 15 if PAGE_OFFSET=0x80000000
321 # The "ARM system type" choice list is ordered alphabetically by option
322 # text. Please add new entries in the option alphabetic order.
325 prompt "ARM system type"
326 default ARM_SINGLE_ARMV7M if !MMU
327 default ARCH_MULTIPLATFORM if MMU
329 config ARCH_MULTIPLATFORM
330 bool "Allow multiple platforms to be selected"
332 select ARM_HAS_SG_CHAIN
333 select ARM_PATCH_PHYS_VIRT
337 select GENERIC_CLOCKEVENTS
338 select MIGHT_HAVE_PCI
339 select MULTI_IRQ_HANDLER
340 select PCI_DOMAINS if PCI
344 config ARM_SINGLE_ARMV7M
345 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
352 select GENERIC_CLOCKEVENTS
358 bool "Cortina Systems Gemini"
361 select GENERIC_CLOCKEVENTS
364 Support for the Cortina Systems Gemini family SoCs
368 select ARCH_USES_GETTIMEOFFSET
371 select NEED_MACH_IO_H
372 select NEED_MACH_MEMORY_H
375 This is an evaluation board for the StrongARM processor available
376 from Digital. It has limited hardware on-board, including an
377 Ethernet interface, two PCMCIA sockets, two serial ports and a
382 select ARCH_HAS_HOLES_MEMORYMODEL
384 select ARM_PATCH_PHYS_VIRT
390 select GENERIC_CLOCKEVENTS
393 This enables support for the Cirrus EP93xx series of CPUs.
395 config ARCH_FOOTBRIDGE
399 select GENERIC_CLOCKEVENTS
401 select NEED_MACH_IO_H if !MMU
402 select NEED_MACH_MEMORY_H
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
408 bool "Hilscher NetX based"
412 select GENERIC_CLOCKEVENTS
414 This enables support for systems based on the Hilscher NetX Soc
420 select NEED_MACH_MEMORY_H
421 select NEED_RET_TO_USER
427 Support for Intel's IOP13XX (XScale) family of processors.
435 select NEED_RET_TO_USER
439 Support for Intel's 80219 and IOP32X (XScale) family of
448 select NEED_RET_TO_USER
452 Support for Intel's IOP33X (XScale) family of processors.
457 select ARCH_HAS_DMA_SET_COHERENT_MASK
458 select ARCH_SUPPORTS_BIG_ENDIAN
461 select DMABOUNCE if PCI
462 select GENERIC_CLOCKEVENTS
464 select MIGHT_HAVE_PCI
465 select NEED_MACH_IO_H
466 select USB_EHCI_BIG_ENDIAN_DESC
467 select USB_EHCI_BIG_ENDIAN_MMIO
469 Support for Intel's IXP4XX (XScale) family of processors.
474 select GENERIC_CLOCKEVENTS
476 select MIGHT_HAVE_PCI
477 select MULTI_IRQ_HANDLER
481 select PLAT_ORION_LEGACY
483 select PM_GENERIC_DOMAINS if PM
485 Support for the Marvell Dove SoC 88AP510
488 bool "Micrel/Kendin KS8695"
491 select GENERIC_CLOCKEVENTS
493 select NEED_MACH_MEMORY_H
495 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
496 System-on-Chip devices.
499 bool "Nuvoton W90X900 CPU"
503 select GENERIC_CLOCKEVENTS
506 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
507 At present, the w90x900 has been renamed nuc900, regarding
508 the ARM series product line, you can login the following
509 link address to know more.
511 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
512 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
518 select CLKSRC_LPC32XX
521 select GENERIC_CLOCKEVENTS
523 select MULTI_IRQ_HANDLER
527 Support for the NXP LPC32XX family of processors
530 bool "PXA2xx/PXA3xx-based"
533 select ARM_CPU_SUSPEND if PM
540 select CPU_XSCALE if !CPU_XSC3
541 select GENERIC_CLOCKEVENTS
546 select MULTI_IRQ_HANDLER
550 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
556 select ARCH_MAY_HAVE_PC_FDC
557 select ARCH_SPARSEMEM_ENABLE
558 select ARCH_USES_GETTIMEOFFSET
562 select HAVE_PATA_PLATFORM
564 select NEED_MACH_IO_H
565 select NEED_MACH_MEMORY_H
568 On the Acorn Risc-PC, Linux can support the internal IDE disk and
569 CD-ROM interface, serial and parallel port, and the floppy drive.
574 select ARCH_SPARSEMEM_ENABLE
578 select CLKSRC_OF if OF
581 select GENERIC_CLOCKEVENTS
586 select MULTI_IRQ_HANDLER
587 select NEED_MACH_MEMORY_H
590 Support for StrongARM 11x0 based boards.
593 bool "Samsung S3C24XX SoCs"
596 select CLKSRC_SAMSUNG_PWM
597 select GENERIC_CLOCKEVENTS
600 select HAVE_S3C2410_I2C if I2C
601 select HAVE_S3C2410_WATCHDOG if WATCHDOG
602 select HAVE_S3C_RTC if RTC_CLASS
603 select MULTI_IRQ_HANDLER
604 select NEED_MACH_IO_H
605 select S3C2410_WATCHDOG
609 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
610 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
611 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
612 Samsung SMDK2410 development board (and derivatives).
616 select ARCH_HAS_HOLES_MEMORYMODEL
619 select GENERIC_ALLOCATOR
620 select GENERIC_CLOCKEVENTS
621 select GENERIC_IRQ_CHIP
627 Support for TI's DaVinci platform.
632 select ARCH_HAS_HOLES_MEMORYMODEL
636 select GENERIC_CLOCKEVENTS
637 select GENERIC_IRQ_CHIP
641 select MULTI_IRQ_HANDLER
642 select NEED_MACH_IO_H if PCCARD
643 select NEED_MACH_MEMORY_H
646 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
650 menu "Multiple platform selection"
651 depends on ARCH_MULTIPLATFORM
653 comment "CPU Core family selection"
656 bool "ARMv4 based platforms (FA526)"
657 depends on !ARCH_MULTI_V6_V7
658 select ARCH_MULTI_V4_V5
661 config ARCH_MULTI_V4T
662 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
663 depends on !ARCH_MULTI_V6_V7
664 select ARCH_MULTI_V4_V5
665 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
666 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
667 CPU_ARM925T || CPU_ARM940T)
670 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
671 depends on !ARCH_MULTI_V6_V7
672 select ARCH_MULTI_V4_V5
673 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
674 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
675 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
677 config ARCH_MULTI_V4_V5
681 bool "ARMv6 based platforms (ARM11)"
682 select ARCH_MULTI_V6_V7
686 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
688 select ARCH_MULTI_V6_V7
692 config ARCH_MULTI_V6_V7
694 select MIGHT_HAVE_CACHE_L2X0
696 config ARCH_MULTI_CPU_AUTO
697 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
703 bool "Dummy Virtual Machine"
704 depends on ARCH_MULTI_V7
707 select ARM_GIC_V2M if PCI
710 select HAVE_ARM_ARCH_TIMER
713 # This is sorted alphabetically by mach-* pathname. However, plat-*
714 # Kconfigs may be included either alphabetically (according to the
715 # plat- suffix) or along side the corresponding mach-* source.
717 source "arch/arm/mach-mvebu/Kconfig"
719 source "arch/arm/mach-alpine/Kconfig"
721 source "arch/arm/mach-artpec/Kconfig"
723 source "arch/arm/mach-asm9260/Kconfig"
725 source "arch/arm/mach-at91/Kconfig"
727 source "arch/arm/mach-axxia/Kconfig"
729 source "arch/arm/mach-bcm/Kconfig"
731 source "arch/arm/mach-berlin/Kconfig"
733 source "arch/arm/mach-clps711x/Kconfig"
735 source "arch/arm/mach-cns3xxx/Kconfig"
737 source "arch/arm/mach-davinci/Kconfig"
739 source "arch/arm/mach-digicolor/Kconfig"
741 source "arch/arm/mach-dove/Kconfig"
743 source "arch/arm/mach-ep93xx/Kconfig"
745 source "arch/arm/mach-footbridge/Kconfig"
747 source "arch/arm/mach-gemini/Kconfig"
749 source "arch/arm/mach-highbank/Kconfig"
751 source "arch/arm/mach-hisi/Kconfig"
753 source "arch/arm/mach-integrator/Kconfig"
755 source "arch/arm/mach-iop32x/Kconfig"
757 source "arch/arm/mach-iop33x/Kconfig"
759 source "arch/arm/mach-iop13xx/Kconfig"
761 source "arch/arm/mach-ixp4xx/Kconfig"
763 source "arch/arm/mach-keystone/Kconfig"
765 source "arch/arm/mach-ks8695/Kconfig"
767 source "arch/arm/mach-meson/Kconfig"
769 source "arch/arm/mach-moxart/Kconfig"
771 source "arch/arm/mach-aspeed/Kconfig"
773 source "arch/arm/mach-mv78xx0/Kconfig"
775 source "arch/arm/mach-imx/Kconfig"
777 source "arch/arm/mach-mediatek/Kconfig"
779 source "arch/arm/mach-mxs/Kconfig"
781 source "arch/arm/mach-netx/Kconfig"
783 source "arch/arm/mach-nomadik/Kconfig"
785 source "arch/arm/mach-nspire/Kconfig"
787 source "arch/arm/plat-omap/Kconfig"
789 source "arch/arm/mach-omap1/Kconfig"
791 source "arch/arm/mach-omap2/Kconfig"
793 source "arch/arm/mach-orion5x/Kconfig"
795 source "arch/arm/mach-picoxcell/Kconfig"
797 source "arch/arm/mach-pxa/Kconfig"
798 source "arch/arm/plat-pxa/Kconfig"
800 source "arch/arm/mach-mmp/Kconfig"
802 source "arch/arm/mach-oxnas/Kconfig"
804 source "arch/arm/mach-qcom/Kconfig"
806 source "arch/arm/mach-realview/Kconfig"
808 source "arch/arm/mach-rockchip/Kconfig"
810 source "arch/arm/mach-sa1100/Kconfig"
812 source "arch/arm/mach-socfpga/Kconfig"
814 source "arch/arm/mach-spear/Kconfig"
816 source "arch/arm/mach-sti/Kconfig"
818 source "arch/arm/mach-s3c24xx/Kconfig"
820 source "arch/arm/mach-s3c64xx/Kconfig"
822 source "arch/arm/mach-s5pv210/Kconfig"
824 source "arch/arm/mach-exynos/Kconfig"
825 source "arch/arm/plat-samsung/Kconfig"
827 source "arch/arm/mach-shmobile/Kconfig"
829 source "arch/arm/mach-sunxi/Kconfig"
831 source "arch/arm/mach-prima2/Kconfig"
833 source "arch/arm/mach-tango/Kconfig"
835 source "arch/arm/mach-tegra/Kconfig"
837 source "arch/arm/mach-u300/Kconfig"
839 source "arch/arm/mach-uniphier/Kconfig"
841 source "arch/arm/mach-ux500/Kconfig"
843 source "arch/arm/mach-versatile/Kconfig"
845 source "arch/arm/mach-vexpress/Kconfig"
846 source "arch/arm/plat-versatile/Kconfig"
848 source "arch/arm/mach-vt8500/Kconfig"
850 source "arch/arm/mach-w90x900/Kconfig"
852 source "arch/arm/mach-zx/Kconfig"
854 source "arch/arm/mach-zynq/Kconfig"
856 # ARMv7-M architecture
858 bool "Energy Micro efm32"
859 depends on ARM_SINGLE_ARMV7M
862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
866 bool "NXP LPC18xx/LPC43xx"
867 depends on ARM_SINGLE_ARMV7M
868 select ARCH_HAS_RESET_CONTROLLER
870 select CLKSRC_LPC32XX
873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
874 high performance microcontrollers.
877 bool "STMicrolectronics STM32"
878 depends on ARM_SINGLE_ARMV7M
879 select ARCH_HAS_RESET_CONTROLLER
880 select ARMV7M_SYSTICK
883 select RESET_CONTROLLER
886 Support for STMicroelectronics STM32 processors.
888 config MACH_STM32F429
889 bool "STMicrolectronics STM32F429"
890 depends on ARCH_STM32
894 bool "ARM MPS2 platform"
895 depends on ARM_SINGLE_ARMV7M
899 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
900 with a range of available cores like Cortex-M3/M4/M7.
902 Please, note that depends which Application Note is used memory map
903 for the platform may vary, so adjustment of RAM base might be needed.
905 # Definitions to make life easier
911 select GENERIC_CLOCKEVENTS
917 select GENERIC_IRQ_CHIP
920 config PLAT_ORION_LEGACY
927 config PLAT_VERSATILE
930 source "arch/arm/firmware/Kconfig"
932 source arch/arm/mm/Kconfig
935 bool "Enable iWMMXt support"
936 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
937 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
939 Enable support for iWMMXt context switching at run time if
940 running on a CPU that supports it.
942 config MULTI_IRQ_HANDLER
945 Allow each machine to specify it's own IRQ handler at run time.
948 source "arch/arm/Kconfig-nommu"
951 config PJ4B_ERRATA_4742
952 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
953 depends on CPU_PJ4B && MACH_ARMADA_370
956 When coming out of either a Wait for Interrupt (WFI) or a Wait for
957 Event (WFE) IDLE states, a specific timing sensitivity exists between
958 the retiring WFI/WFE instructions and the newly issued subsequent
959 instructions. This sensitivity can result in a CPU hang scenario.
961 The software must insert either a Data Synchronization Barrier (DSB)
962 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
965 config ARM_ERRATA_326103
966 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
969 Executing a SWP instruction to read-only memory does not set bit 11
970 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
971 treat the access as a read, preventing a COW from occurring and
972 causing the faulting task to livelock.
974 config ARM_ERRATA_411920
975 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
976 depends on CPU_V6 || CPU_V6K
978 Invalidation of the Instruction Cache operation can
979 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
980 It does not affect the MPCore. This option enables the ARM Ltd.
981 recommended workaround.
983 config ARM_ERRATA_430973
984 bool "ARM errata: Stale prediction on replaced interworking branch"
987 This option enables the workaround for the 430973 Cortex-A8
988 r1p* erratum. If a code sequence containing an ARM/Thumb
989 interworking branch is replaced with another code sequence at the
990 same virtual address, whether due to self-modifying code or virtual
991 to physical address re-mapping, Cortex-A8 does not recover from the
992 stale interworking branch prediction. This results in Cortex-A8
993 executing the new code sequence in the incorrect ARM or Thumb state.
994 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
995 and also flushes the branch target cache at every context switch.
996 Note that setting specific bits in the ACTLR register may not be
997 available in non-secure mode.
999 config ARM_ERRATA_458693
1000 bool "ARM errata: Processor deadlock when a false hazard is created"
1002 depends on !ARCH_MULTIPLATFORM
1004 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1005 erratum. For very specific sequences of memory operations, it is
1006 possible for a hazard condition intended for a cache line to instead
1007 be incorrectly associated with a different cache line. This false
1008 hazard might then cause a processor deadlock. The workaround enables
1009 the L1 caching of the NEON accesses and disables the PLD instruction
1010 in the ACTLR register. Note that setting specific bits in the ACTLR
1011 register may not be available in non-secure mode.
1013 config ARM_ERRATA_460075
1014 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1016 depends on !ARCH_MULTIPLATFORM
1018 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1019 erratum. Any asynchronous access to the L2 cache may encounter a
1020 situation in which recent store transactions to the L2 cache are lost
1021 and overwritten with stale memory contents from external memory. The
1022 workaround disables the write-allocate mode for the L2 cache via the
1023 ACTLR register. Note that setting specific bits in the ACTLR register
1024 may not be available in non-secure mode.
1026 config ARM_ERRATA_742230
1027 bool "ARM errata: DMB operation may be faulty"
1028 depends on CPU_V7 && SMP
1029 depends on !ARCH_MULTIPLATFORM
1031 This option enables the workaround for the 742230 Cortex-A9
1032 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1033 between two write operations may not ensure the correct visibility
1034 ordering of the two writes. This workaround sets a specific bit in
1035 the diagnostic register of the Cortex-A9 which causes the DMB
1036 instruction to behave as a DSB, ensuring the correct behaviour of
1039 config ARM_ERRATA_742231
1040 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1041 depends on CPU_V7 && SMP
1042 depends on !ARCH_MULTIPLATFORM
1044 This option enables the workaround for the 742231 Cortex-A9
1045 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1046 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1047 accessing some data located in the same cache line, may get corrupted
1048 data due to bad handling of the address hazard when the line gets
1049 replaced from one of the CPUs at the same time as another CPU is
1050 accessing it. This workaround sets specific bits in the diagnostic
1051 register of the Cortex-A9 which reduces the linefill issuing
1052 capabilities of the processor.
1054 config ARM_ERRATA_643719
1055 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1056 depends on CPU_V7 && SMP
1059 This option enables the workaround for the 643719 Cortex-A9 (prior to
1060 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1061 register returns zero when it should return one. The workaround
1062 corrects this value, ensuring cache maintenance operations which use
1063 it behave as intended and avoiding data corruption.
1065 config ARM_ERRATA_720789
1066 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1069 This option enables the workaround for the 720789 Cortex-A9 (prior to
1070 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1071 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1072 As a consequence of this erratum, some TLB entries which should be
1073 invalidated are not, resulting in an incoherency in the system page
1074 tables. The workaround changes the TLB flushing routines to invalidate
1075 entries regardless of the ASID.
1077 config ARM_ERRATA_743622
1078 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1080 depends on !ARCH_MULTIPLATFORM
1082 This option enables the workaround for the 743622 Cortex-A9
1083 (r2p*) erratum. Under very rare conditions, a faulty
1084 optimisation in the Cortex-A9 Store Buffer may lead to data
1085 corruption. This workaround sets a specific bit in the diagnostic
1086 register of the Cortex-A9 which disables the Store Buffer
1087 optimisation, preventing the defect from occurring. This has no
1088 visible impact on the overall performance or power consumption of the
1091 config ARM_ERRATA_751472
1092 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1094 depends on !ARCH_MULTIPLATFORM
1096 This option enables the workaround for the 751472 Cortex-A9 (prior
1097 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1098 completion of a following broadcasted operation if the second
1099 operation is received by a CPU before the ICIALLUIS has completed,
1100 potentially leading to corrupted entries in the cache or TLB.
1102 config ARM_ERRATA_754322
1103 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1106 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1107 r3p*) erratum. A speculative memory access may cause a page table walk
1108 which starts prior to an ASID switch but completes afterwards. This
1109 can populate the micro-TLB with a stale entry which may be hit with
1110 the new ASID. This workaround places two dsb instructions in the mm
1111 switching code so that no page table walks can cross the ASID switch.
1113 config ARM_ERRATA_754327
1114 bool "ARM errata: no automatic Store Buffer drain"
1115 depends on CPU_V7 && SMP
1117 This option enables the workaround for the 754327 Cortex-A9 (prior to
1118 r2p0) erratum. The Store Buffer does not have any automatic draining
1119 mechanism and therefore a livelock may occur if an external agent
1120 continuously polls a memory location waiting to observe an update.
1121 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1122 written polling loops from denying visibility of updates to memory.
1124 config ARM_ERRATA_364296
1125 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1128 This options enables the workaround for the 364296 ARM1136
1129 r0p2 erratum (possible cache data corruption with
1130 hit-under-miss enabled). It sets the undocumented bit 31 in
1131 the auxiliary control register and the FI bit in the control
1132 register, thus disabling hit-under-miss without putting the
1133 processor into full low interrupt latency mode. ARM11MPCore
1136 config ARM_ERRATA_764369
1137 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1138 depends on CPU_V7 && SMP
1140 This option enables the workaround for erratum 764369
1141 affecting Cortex-A9 MPCore with two or more processors (all
1142 current revisions). Under certain timing circumstances, a data
1143 cache line maintenance operation by MVA targeting an Inner
1144 Shareable memory region may fail to proceed up to either the
1145 Point of Coherency or to the Point of Unification of the
1146 system. This workaround adds a DSB instruction before the
1147 relevant cache maintenance functions and sets a specific bit
1148 in the diagnostic control register of the SCU.
1150 config ARM_ERRATA_775420
1151 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1154 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1155 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1156 operation aborts with MMU exception, it might cause the processor
1157 to deadlock. This workaround puts DSB before executing ISB if
1158 an abort may occur on cache maintenance.
1160 config ARM_ERRATA_798181
1161 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1162 depends on CPU_V7 && SMP
1164 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1165 adequately shooting down all use of the old entries. This
1166 option enables the Linux kernel workaround for this erratum
1167 which sends an IPI to the CPUs that are running the same ASID
1168 as the one being invalidated.
1170 config ARM_ERRATA_773022
1171 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1174 This option enables the workaround for the 773022 Cortex-A15
1175 (up to r0p4) erratum. In certain rare sequences of code, the
1176 loop buffer may deliver incorrect instructions. This
1177 workaround disables the loop buffer to avoid the erratum.
1179 config ARM_ERRATA_818325_852422
1180 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1183 This option enables the workaround for:
1184 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1185 instruction might deadlock. Fixed in r0p1.
1186 - Cortex-A12 852422: Execution of a sequence of instructions might
1187 lead to either a data corruption or a CPU deadlock. Not fixed in
1188 any Cortex-A12 cores yet.
1189 This workaround for all both errata involves setting bit[12] of the
1190 Feature Register. This bit disables an optimisation applied to a
1191 sequence of 2 instructions that use opposing condition codes.
1193 config ARM_ERRATA_821420
1194 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1197 This option enables the workaround for the 821420 Cortex-A12
1198 (all revs) erratum. In very rare timing conditions, a sequence
1199 of VMOV to Core registers instructions, for which the second
1200 one is in the shadow of a branch or abort, can lead to a
1201 deadlock when the VMOV instructions are issued out-of-order.
1203 config ARM_ERRATA_825619
1204 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1207 This option enables the workaround for the 825619 Cortex-A12
1208 (all revs) erratum. Within rare timing constraints, executing a
1209 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1210 and Device/Strongly-Ordered loads and stores might cause deadlock
1212 config ARM_ERRATA_852421
1213 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1216 This option enables the workaround for the 852421 Cortex-A17
1217 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1218 execution of a DMB ST instruction might fail to properly order
1219 stores from GroupA and stores from GroupB.
1221 config ARM_ERRATA_852423
1222 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1225 This option enables the workaround for:
1226 - Cortex-A17 852423: Execution of a sequence of instructions might
1227 lead to either a data corruption or a CPU deadlock. Not fixed in
1228 any Cortex-A17 cores yet.
1229 This is identical to Cortex-A12 erratum 852422. It is a separate
1230 config option from the A12 erratum due to the way errata are checked
1235 source "arch/arm/common/Kconfig"
1242 Find out whether you have ISA slots on your motherboard. ISA is the
1243 name of a bus system, i.e. the way the CPU talks to the other stuff
1244 inside your box. Other bus systems are PCI, EISA, MicroChannel
1245 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1246 newer boards don't support it. If you have ISA, say Y, otherwise N.
1248 # Select ISA DMA controller support
1253 # Select ISA DMA interface
1258 bool "PCI support" if MIGHT_HAVE_PCI
1260 Find out whether you have a PCI motherboard. PCI is the name of a
1261 bus system, i.e. the way the CPU talks to the other stuff inside
1262 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1263 VESA. If you have PCI, say Y, otherwise N.
1269 config PCI_DOMAINS_GENERIC
1270 def_bool PCI_DOMAINS
1272 config PCI_NANOENGINE
1273 bool "BSE nanoEngine PCI support"
1274 depends on SA1100_NANOENGINE
1276 Enable PCI on the BSE nanoEngine board.
1281 config PCI_HOST_ITE8152
1283 depends on PCI && MACH_ARMCORE
1287 source "drivers/pci/Kconfig"
1289 source "drivers/pcmcia/Kconfig"
1293 menu "Kernel Features"
1298 This option should be selected by machines which have an SMP-
1301 The only effect of this option is to make the SMP-related
1302 options available to the user for configuration.
1305 bool "Symmetric Multi-Processing"
1306 depends on CPU_V6K || CPU_V7
1307 depends on GENERIC_CLOCKEVENTS
1309 depends on MMU || ARM_MPU
1312 This enables support for systems with more than one CPU. If you have
1313 a system with only one CPU, say N. If you have a system with more
1314 than one CPU, say Y.
1316 If you say N here, the kernel will run on uni- and multiprocessor
1317 machines, but will use only one CPU of a multiprocessor machine. If
1318 you say Y here, the kernel will run on many, but not all,
1319 uniprocessor machines. On a uniprocessor machine, the kernel
1320 will run faster if you say N here.
1322 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1323 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1324 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1326 If you don't know what to do here, say N.
1329 bool "Allow booting SMP kernel on uniprocessor systems"
1330 depends on SMP && !XIP_KERNEL && MMU
1333 SMP kernels contain instructions which fail on non-SMP processors.
1334 Enabling this option allows the kernel to modify itself to make
1335 these instructions safe. Disabling it allows about 1K of space
1338 If you don't know what to do here, say Y.
1340 config ARM_CPU_TOPOLOGY
1341 bool "Support cpu topology definition"
1342 depends on SMP && CPU_V7
1345 Support ARM cpu topology definition. The MPIDR register defines
1346 affinity between processors which is then used to describe the cpu
1347 topology of an ARM System.
1350 bool "Multi-core scheduler support"
1351 depends on ARM_CPU_TOPOLOGY
1353 Multi-core scheduler support improves the CPU scheduler's decision
1354 making when dealing with multi-core CPU chips at a cost of slightly
1355 increased overhead in some places. If unsure say N here.
1358 bool "SMT scheduler support"
1359 depends on ARM_CPU_TOPOLOGY
1361 Improves the CPU scheduler's decision making when dealing with
1362 MultiThreading at a cost of slightly increased overhead in some
1363 places. If unsure say N here.
1368 This option enables support for the ARM system coherency unit
1370 config HAVE_ARM_ARCH_TIMER
1371 bool "Architected timer support"
1373 select ARM_ARCH_TIMER
1374 select GENERIC_CLOCKEVENTS
1376 This option enables support for the ARM architected timer
1380 select CLKSRC_OF if OF
1382 This options enables support for the ARM timer and watchdog unit
1385 bool "Multi-Cluster Power Management"
1386 depends on CPU_V7 && SMP
1388 This option provides the common power management infrastructure
1389 for (multi-)cluster based systems, such as big.LITTLE based
1392 config MCPM_QUAD_CLUSTER
1396 To avoid wasting resources unnecessarily, MCPM only supports up
1397 to 2 clusters by default.
1398 Platforms with 3 or 4 clusters that use MCPM must select this
1399 option to allow the additional clusters to be managed.
1402 bool "big.LITTLE support (Experimental)"
1403 depends on CPU_V7 && SMP
1406 This option enables support selections for the big.LITTLE
1407 system architecture.
1410 bool "big.LITTLE switcher support"
1411 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1414 The big.LITTLE "switcher" provides the core functionality to
1415 transparently handle transition between a cluster of A15's
1416 and a cluster of A7's in a big.LITTLE system.
1418 config BL_SWITCHER_DUMMY_IF
1419 tristate "Simple big.LITTLE switcher user interface"
1420 depends on BL_SWITCHER && DEBUG_KERNEL
1422 This is a simple and dummy char dev interface to control
1423 the big.LITTLE switcher core code. It is meant for
1424 debugging purposes only.
1427 prompt "Memory split"
1431 Select the desired split between kernel and user memory.
1433 If you are not absolutely sure what you are doing, leave this
1437 bool "3G/1G user/kernel split"
1438 config VMSPLIT_3G_OPT
1439 bool "3G/1G user/kernel split (for full 1G low memory)"
1441 bool "2G/2G user/kernel split"
1443 bool "1G/3G user/kernel split"
1448 default PHYS_OFFSET if !MMU
1449 default 0x40000000 if VMSPLIT_1G
1450 default 0x80000000 if VMSPLIT_2G
1451 default 0xB0000000 if VMSPLIT_3G_OPT
1455 int "Maximum number of CPUs (2-32)"
1461 bool "Support for hot-pluggable CPUs"
1463 select GENERIC_IRQ_MIGRATION
1465 Say Y here to experiment with turning CPUs off and on. CPUs
1466 can be controlled through /sys/devices/system/cpu.
1469 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1470 depends on HAVE_ARM_SMCCC
1473 Say Y here if you want Linux to communicate with system firmware
1474 implementing the PSCI specification for CPU-centric power
1475 management operations described in ARM document number ARM DEN
1476 0022A ("Power State Coordination Interface System Software on
1479 # The GPIO number here must be sorted by descending number. In case of
1480 # a multiplatform kernel, we just want the highest value required by the
1481 # selected platforms.
1484 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1486 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1487 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1488 default 416 if ARCH_SUNXI
1489 default 392 if ARCH_U8500
1490 default 352 if ARCH_VT8500
1491 default 288 if ARCH_ROCKCHIP
1492 default 264 if MACH_H4700
1495 Maximum number of GPIOs in the system.
1497 If unsure, leave the default value.
1499 source kernel/Kconfig.preempt
1503 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1504 ARCH_S5PV210 || ARCH_EXYNOS4
1505 default 128 if SOC_AT91RM9200
1509 depends on HZ_FIXED = 0
1510 prompt "Timer frequency"
1534 default HZ_FIXED if HZ_FIXED != 0
1535 default 100 if HZ_100
1536 default 200 if HZ_200
1537 default 250 if HZ_250
1538 default 300 if HZ_300
1539 default 500 if HZ_500
1543 def_bool HIGH_RES_TIMERS
1545 config THUMB2_KERNEL
1546 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1547 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1548 default y if CPU_THUMBONLY
1552 By enabling this option, the kernel will be compiled in
1557 config THUMB2_AVOID_R_ARM_THM_JUMP11
1558 bool "Work around buggy Thumb-2 short branch relocations in gas"
1559 depends on THUMB2_KERNEL && MODULES
1562 Various binutils versions can resolve Thumb-2 branches to
1563 locally-defined, preemptible global symbols as short-range "b.n"
1564 branch instructions.
1566 This is a problem, because there's no guarantee the final
1567 destination of the symbol, or any candidate locations for a
1568 trampoline, are within range of the branch. For this reason, the
1569 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1570 relocation in modules at all, and it makes little sense to add
1573 The symptom is that the kernel fails with an "unsupported
1574 relocation" error when loading some modules.
1576 Until fixed tools are available, passing
1577 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1578 code which hits this problem, at the cost of a bit of extra runtime
1579 stack usage in some cases.
1581 The problem is described in more detail at:
1582 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1584 Only Thumb-2 kernels are affected.
1586 Unless you are sure your tools don't have this problem, say Y.
1588 config ARM_PATCH_IDIV
1589 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1590 depends on CPU_32v7 && !XIP_KERNEL
1593 The ARM compiler inserts calls to __aeabi_idiv() and
1594 __aeabi_uidiv() when it needs to perform division on signed
1595 and unsigned integers. Some v7 CPUs have support for the sdiv
1596 and udiv instructions that can be used to implement those
1599 Enabling this option allows the kernel to modify itself to
1600 replace the first two instructions of these library functions
1601 with the sdiv or udiv plus "bx lr" instructions when the CPU
1602 it is running on supports them. Typically this will be faster
1603 and less power intensive than running the original library
1604 code to do integer division.
1607 bool "Use the ARM EABI to compile the kernel"
1609 This option allows for the kernel to be compiled using the latest
1610 ARM ABI (aka EABI). This is only useful if you are using a user
1611 space environment that is also compiled with EABI.
1613 Since there are major incompatibilities between the legacy ABI and
1614 EABI, especially with regard to structure member alignment, this
1615 option also changes the kernel syscall calling convention to
1616 disambiguate both ABIs and allow for backward compatibility support
1617 (selected with CONFIG_OABI_COMPAT).
1619 To use this you need GCC version 4.0.0 or later.
1622 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1623 depends on AEABI && !THUMB2_KERNEL
1625 This option preserves the old syscall interface along with the
1626 new (ARM EABI) one. It also provides a compatibility layer to
1627 intercept syscalls that have structure arguments which layout
1628 in memory differs between the legacy ABI and the new ARM EABI
1629 (only for non "thumb" binaries). This option adds a tiny
1630 overhead to all syscalls and produces a slightly larger kernel.
1632 The seccomp filter system will not be available when this is
1633 selected, since there is no way yet to sensibly distinguish
1634 between calling conventions during filtering.
1636 If you know you'll be using only pure EABI user space then you
1637 can say N here. If this option is not selected and you attempt
1638 to execute a legacy ABI binary then the result will be
1639 UNPREDICTABLE (in fact it can be predicted that it won't work
1640 at all). If in doubt say N.
1642 config ARCH_HAS_HOLES_MEMORYMODEL
1645 config ARCH_SPARSEMEM_ENABLE
1648 config ARCH_SPARSEMEM_DEFAULT
1649 def_bool ARCH_SPARSEMEM_ENABLE
1651 config ARCH_SELECT_MEMORY_MODEL
1652 def_bool ARCH_SPARSEMEM_ENABLE
1654 config HAVE_ARCH_PFN_VALID
1655 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1657 config HAVE_GENERIC_RCU_GUP
1662 bool "High Memory Support"
1665 The address space of ARM processors is only 4 Gigabytes large
1666 and it has to accommodate user address space, kernel address
1667 space as well as some memory mapped IO. That means that, if you
1668 have a large amount of physical memory and/or IO, not all of the
1669 memory can be "permanently mapped" by the kernel. The physical
1670 memory that is not permanently mapped is called "high memory".
1672 Depending on the selected kernel/user memory split, minimum
1673 vmalloc space and actual amount of RAM, you may not need this
1674 option which should result in a slightly faster kernel.
1679 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1683 The VM uses one page of physical memory for each page table.
1684 For systems with a lot of processes, this can use a lot of
1685 precious low memory, eventually leading to low memory being
1686 consumed by page tables. Setting this option will allow
1687 user-space 2nd level page tables to reside in high memory.
1689 config CPU_SW_DOMAIN_PAN
1690 bool "Enable use of CPU domains to implement privileged no-access"
1691 depends on MMU && !ARM_LPAE
1694 Increase kernel security by ensuring that normal kernel accesses
1695 are unable to access userspace addresses. This can help prevent
1696 use-after-free bugs becoming an exploitable privilege escalation
1697 by ensuring that magic values (such as LIST_POISON) will always
1698 fault when dereferenced.
1700 CPUs with low-vector mappings use a best-efforts implementation.
1701 Their lower 1MB needs to remain accessible for the vectors, but
1702 the remainder of userspace will become appropriately inaccessible.
1704 config HW_PERF_EVENTS
1708 config SYS_SUPPORTS_HUGETLBFS
1712 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1716 config ARCH_WANT_GENERAL_HUGETLB
1719 config ARM_MODULE_PLTS
1720 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1723 Allocate PLTs when loading modules so that jumps and calls whose
1724 targets are too far away for their relative offsets to be encoded
1725 in the instructions themselves can be bounced via veneers in the
1726 module's PLT. This allows modules to be allocated in the generic
1727 vmalloc area after the dedicated module memory area has been
1728 exhausted. The modules will use slightly more memory, but after
1729 rounding up to page size, the actual memory footprint is usually
1732 Say y if you are getting out of memory errors while loading modules
1736 config FORCE_MAX_ZONEORDER
1737 int "Maximum zone order"
1738 default "12" if SOC_AM33XX
1739 default "9" if SA1111 || ARCH_EFM32
1742 The kernel memory allocator divides physically contiguous memory
1743 blocks into "zones", where each zone is a power of two number of
1744 pages. This option selects the largest power of two that the kernel
1745 keeps in the memory allocator. If you need to allocate very large
1746 blocks of physically contiguous memory, then you may need to
1747 increase this value.
1749 This config option is actually maximum order plus one. For example,
1750 a value of 11 means that the largest free memory block is 2^10 pages.
1752 config ALIGNMENT_TRAP
1754 depends on CPU_CP15_MMU
1755 default y if !ARCH_EBSA110
1756 select HAVE_PROC_CPU if PROC_FS
1758 ARM processors cannot fetch/store information which is not
1759 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1760 address divisible by 4. On 32-bit ARM processors, these non-aligned
1761 fetch/store instructions will be emulated in software if you say
1762 here, which has a severe performance impact. This is necessary for
1763 correct operation of some network protocols. With an IP-only
1764 configuration it is safe to say N, otherwise say Y.
1766 config UACCESS_WITH_MEMCPY
1767 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1769 default y if CPU_FEROCEON
1771 Implement faster copy_to_user and clear_user methods for CPU
1772 cores where a 8-word STM instruction give significantly higher
1773 memory write throughput than a sequence of individual 32bit stores.
1775 A possible side effect is a slight increase in scheduling latency
1776 between threads sharing the same address space if they invoke
1777 such copy operations with large buffers.
1779 However, if the CPU data cache is using a write-allocate mode,
1780 this option is unlikely to provide any performance gain.
1784 prompt "Enable seccomp to safely compute untrusted bytecode"
1786 This kernel feature is useful for number crunching applications
1787 that may need to compute untrusted bytecode during their
1788 execution. By using pipes or other transports made available to
1789 the process as file descriptors supporting the read/write
1790 syscalls, it's possible to isolate those applications in
1791 their own address space using seccomp. Once seccomp is
1792 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1793 and the task is only allowed to execute a few safe syscalls
1794 defined by each seccomp mode.
1803 bool "Enable paravirtualization code"
1805 This changes the kernel so it can modify itself when it is run
1806 under a hypervisor, potentially improving performance significantly
1807 over full virtualization.
1809 config PARAVIRT_TIME_ACCOUNTING
1810 bool "Paravirtual steal time accounting"
1814 Select this option to enable fine granularity task steal time
1815 accounting. Time spent executing other tasks in parallel with
1816 the current vCPU is discounted from the vCPU power. To account for
1817 that, there can be a small performance impact.
1819 If in doubt, say N here.
1826 bool "Xen guest support on ARM"
1827 depends on ARM && AEABI && OF
1828 depends on CPU_V7 && !CPU_V6
1829 depends on !GENERIC_ATOMIC64
1831 select ARCH_DMA_ADDR_T_64BIT
1836 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1843 bool "Flattened Device Tree support"
1847 Include support for flattened device tree machine descriptions.
1850 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1853 This is the traditional way of passing data to the kernel at boot
1854 time. If you are solely relying on the flattened device tree (or
1855 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1856 to remove ATAGS support from your kernel binary. If unsure,
1859 config DEPRECATED_PARAM_STRUCT
1860 bool "Provide old way to pass kernel parameters"
1863 This was deprecated in 2001 and announced to live on for 5 years.
1864 Some old boot loaders still use this way.
1866 # Compressed boot loader in ROM. Yes, we really want to ask about
1867 # TEXT and BSS so we preserve their values in the config files.
1868 config ZBOOT_ROM_TEXT
1869 hex "Compressed ROM boot loader base address"
1872 The physical address at which the ROM-able zImage is to be
1873 placed in the target. Platforms which normally make use of
1874 ROM-able zImage formats normally set this to a suitable
1875 value in their defconfig file.
1877 If ZBOOT_ROM is not enabled, this has no effect.
1879 config ZBOOT_ROM_BSS
1880 hex "Compressed ROM boot loader BSS address"
1883 The base address of an area of read/write memory in the target
1884 for the ROM-able zImage which must be available while the
1885 decompressor is running. It must be large enough to hold the
1886 entire decompressed kernel plus an additional 128 KiB.
1887 Platforms which normally make use of ROM-able zImage formats
1888 normally set this to a suitable value in their defconfig file.
1890 If ZBOOT_ROM is not enabled, this has no effect.
1893 bool "Compressed boot loader in ROM/flash"
1894 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1895 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1897 Say Y here if you intend to execute your compressed kernel image
1898 (zImage) directly from ROM or flash. If unsure, say N.
1900 config ARM_APPENDED_DTB
1901 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1904 With this option, the boot code will look for a device tree binary
1905 (DTB) appended to zImage
1906 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1908 This is meant as a backward compatibility convenience for those
1909 systems with a bootloader that can't be upgraded to accommodate
1910 the documented boot protocol using a device tree.
1912 Beware that there is very little in terms of protection against
1913 this option being confused by leftover garbage in memory that might
1914 look like a DTB header after a reboot if no actual DTB is appended
1915 to zImage. Do not leave this option active in a production kernel
1916 if you don't intend to always append a DTB. Proper passing of the
1917 location into r2 of a bootloader provided DTB is always preferable
1920 config ARM_ATAG_DTB_COMPAT
1921 bool "Supplement the appended DTB with traditional ATAG information"
1922 depends on ARM_APPENDED_DTB
1924 Some old bootloaders can't be updated to a DTB capable one, yet
1925 they provide ATAGs with memory configuration, the ramdisk address,
1926 the kernel cmdline string, etc. Such information is dynamically
1927 provided by the bootloader and can't always be stored in a static
1928 DTB. To allow a device tree enabled kernel to be used with such
1929 bootloaders, this option allows zImage to extract the information
1930 from the ATAG list and store it at run time into the appended DTB.
1933 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1934 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1936 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937 bool "Use bootloader kernel arguments if available"
1939 Uses the command-line options passed by the boot loader instead of
1940 the device tree bootargs property. If the boot loader doesn't provide
1941 any, the device tree bootargs property will be used.
1943 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1944 bool "Extend with bootloader kernel arguments"
1946 The command-line arguments provided by the boot loader will be
1947 appended to the the device tree bootargs property.
1952 string "Default kernel command string"
1955 On some architectures (EBSA110 and CATS), there is currently no way
1956 for the boot loader to pass arguments to the kernel. For these
1957 architectures, you should supply some command-line options at build
1958 time by entering them here. As a minimum, you should specify the
1959 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1962 prompt "Kernel command line type" if CMDLINE != ""
1963 default CMDLINE_FROM_BOOTLOADER
1966 config CMDLINE_FROM_BOOTLOADER
1967 bool "Use bootloader kernel arguments if available"
1969 Uses the command-line options passed by the boot loader. If
1970 the boot loader doesn't provide any, the default kernel command
1971 string provided in CMDLINE will be used.
1973 config CMDLINE_EXTEND
1974 bool "Extend bootloader kernel arguments"
1976 The command-line arguments provided by the boot loader will be
1977 appended to the default kernel command string.
1979 config CMDLINE_FORCE
1980 bool "Always use the default kernel command string"
1982 Always use the default kernel command string, even if the boot
1983 loader passes other arguments to the kernel.
1984 This is useful if you cannot or don't want to change the
1985 command-line options your boot loader passes to the kernel.
1989 bool "Kernel Execute-In-Place from ROM"
1990 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1992 Execute-In-Place allows the kernel to run from non-volatile storage
1993 directly addressable by the CPU, such as NOR flash. This saves RAM
1994 space since the text section of the kernel is not loaded from flash
1995 to RAM. Read-write sections, such as the data section and stack,
1996 are still copied to RAM. The XIP kernel is not compressed since
1997 it has to run directly from flash, so it will take more space to
1998 store it. The flash address used to link the kernel object files,
1999 and for storing it, is configuration dependent. Therefore, if you
2000 say Y here, you must know the proper physical address where to
2001 store the kernel image depending on your own flash memory usage.
2003 Also note that the make target becomes "make xipImage" rather than
2004 "make zImage" or "make Image". The final kernel binary to put in
2005 ROM memory will be arch/arm/boot/xipImage.
2009 config XIP_PHYS_ADDR
2010 hex "XIP Kernel Physical Location"
2011 depends on XIP_KERNEL
2012 default "0x00080000"
2014 This is the physical address in your flash memory the kernel will
2015 be linked for and stored to. This address is dependent on your
2019 bool "Kexec system call (EXPERIMENTAL)"
2020 depends on (!SMP || PM_SLEEP_SMP)
2024 kexec is a system call that implements the ability to shutdown your
2025 current kernel, and to start another kernel. It is like a reboot
2026 but it is independent of the system firmware. And like a reboot
2027 you can start any kernel with it, not just Linux.
2029 It is an ongoing process to be certain the hardware in a machine
2030 is properly shutdown, so do not be surprised if this code does not
2031 initially work for you.
2034 bool "Export atags in procfs"
2035 depends on ATAGS && KEXEC
2038 Should the atags used to boot the kernel be exported in an "atags"
2039 file in procfs. Useful with kexec.
2042 bool "Build kdump crash kernel (EXPERIMENTAL)"
2044 Generate crash dump after being started by kexec. This should
2045 be normally only set in special crash dump kernels which are
2046 loaded in the main kernel with kexec-tools into a specially
2047 reserved region and then later executed after a crash by
2048 kdump/kexec. The crash dump kernel must be compiled to a
2049 memory address not used by the main kernel
2051 For more details see Documentation/kdump/kdump.txt
2053 config AUTO_ZRELADDR
2054 bool "Auto calculation of the decompressed kernel image address"
2056 ZRELADDR is the physical address where the decompressed kernel
2057 image will be placed. If AUTO_ZRELADDR is selected, the address
2058 will be determined at run-time by masking the current IP with
2059 0xf8000000. This assumes the zImage being placed in the first 128MB
2060 from start of memory.
2066 bool "UEFI runtime support"
2067 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2069 select EFI_PARAMS_FROM_FDT
2072 select EFI_RUNTIME_WRAPPERS
2074 This option provides support for runtime services provided
2075 by UEFI firmware (such as non-volatile variables, realtime
2076 clock, and platform reset). A UEFI stub is also provided to
2077 allow the kernel to be booted as an EFI application. This
2078 is only useful for kernels that may run on systems that have
2083 menu "CPU Power Management"
2085 source "drivers/cpufreq/Kconfig"
2087 source "drivers/cpuidle/Kconfig"
2091 menu "Floating point emulation"
2093 comment "At least one emulation must be selected"
2096 bool "NWFPE math emulation"
2097 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2099 Say Y to include the NWFPE floating point emulator in the kernel.
2100 This is necessary to run most binaries. Linux does not currently
2101 support floating point hardware so you need to say Y here even if
2102 your machine has an FPA or floating point co-processor podule.
2104 You may say N here if you are going to load the Acorn FPEmulator
2105 early in the bootup.
2108 bool "Support extended precision"
2109 depends on FPE_NWFPE
2111 Say Y to include 80-bit support in the kernel floating-point
2112 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2113 Note that gcc does not generate 80-bit operations by default,
2114 so in most cases this option only enlarges the size of the
2115 floating point emulator without any good reason.
2117 You almost surely want to say N here.
2120 bool "FastFPE math emulation (EXPERIMENTAL)"
2121 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2123 Say Y here to include the FAST floating point emulator in the kernel.
2124 This is an experimental much faster emulator which now also has full
2125 precision for the mantissa. It does not support any exceptions.
2126 It is very simple, and approximately 3-6 times faster than NWFPE.
2128 It should be sufficient for most programs. It may be not suitable
2129 for scientific calculations, but you have to check this for yourself.
2130 If you do not feel you need a faster FP emulation you should better
2134 bool "VFP-format floating point maths"
2135 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2137 Say Y to include VFP support code in the kernel. This is needed
2138 if your hardware includes a VFP unit.
2140 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2141 release notes and additional status information.
2143 Say N if your target does not have VFP hardware.
2151 bool "Advanced SIMD (NEON) Extension support"
2152 depends on VFPv3 && CPU_V7
2154 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2157 config KERNEL_MODE_NEON
2158 bool "Support for NEON in kernel mode"
2159 depends on NEON && AEABI
2161 Say Y to include support for NEON in kernel mode.
2165 menu "Userspace binary formats"
2167 source "fs/Kconfig.binfmt"
2171 menu "Power management options"
2173 source "kernel/power/Kconfig"
2175 config ARCH_SUSPEND_POSSIBLE
2176 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2177 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2180 config ARM_CPU_SUSPEND
2181 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2182 depends on ARCH_SUSPEND_POSSIBLE
2184 config ARCH_HIBERNATION_POSSIBLE
2187 default y if ARCH_SUSPEND_POSSIBLE
2191 source "net/Kconfig"
2193 source "drivers/Kconfig"
2195 source "drivers/firmware/Kconfig"
2199 source "arch/arm/Kconfig.debug"
2201 source "security/Kconfig"
2203 source "crypto/Kconfig"
2205 source "arch/arm/crypto/Kconfig"
2208 source "lib/Kconfig"
2210 source "arch/arm/kvm/Kconfig"