1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Check if we are running on Simulator or on real hardware
9 * to skip certain things during boot on simulator
12 #include <linux/linkage.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/entry.h>
15 #include <asm/arcregs.h>
16 #include <asm/cache.h>
17 #include <asm/irqflags.h>
19 .macro CPU_EARLY_SETUP
21 ; Setting up Vectror Table (in case exception happens in early boot
22 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
24 ; Disable I-cache/D-cache if kernel so configured
25 lr r5, [ARC_REG_IC_BCR]
26 breq r5, 0, 1f ; I$ doesn't exist
27 lr r5, [ARC_REG_IC_CTRL]
28 #ifdef CONFIG_ARC_HAS_ICACHE
29 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
31 bset r5, r5, 0 ; I$ exists, but is not used
33 sr r5, [ARC_REG_IC_CTRL]
36 lr r5, [ARC_REG_DC_BCR]
37 breq r5, 0, 1f ; D$ doesn't exist
38 lr r5, [ARC_REG_DC_CTRL]
39 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
40 #ifdef CONFIG_ARC_HAS_DCACHE
41 bclr r5, r5, 0 ; Enable (+Inv)
43 bset r5, r5, 0 ; Disable (+Inv)
45 sr r5, [ARC_REG_DC_CTRL]
49 #ifdef CONFIG_ISA_ARCV2
50 ; Unaligned access is disabled at reset, so re-enable early as
51 ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
54 #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
55 bset r5, r5, STATUS_AD_BIT
57 ; Although disabled at reset, bootloader might have enabled it
58 bclr r5, r5, STATUS_AD_BIT
64 .section .init.text, "ax",@progbits
66 ;----------------------------------------------------------------
67 ; Default Reset Handler (jumped into from Reset vector)
68 ; - Don't clobber r0,r1,r2 as they might have u-boot provided args
69 ; - Platforms can override this weak version if needed
70 ;----------------------------------------------------------------
75 ;----------------------------------------------------------------
77 ;----------------------------------------------------------------
88 ; Non-Masters wait for Master to boot enough and bring them up
89 ; when they resume, tail-call to entry point
90 mov blink, @first_lines_of_secondary
91 j arc_platform_smp_wait_to_boot
96 ; Clear BSS before updating any globals
99 sub r6, __bss_stop, r5
100 lsr.f lp_count, r6, 2
106 ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
107 ; r1 = magic number (always zero as of now)
108 ; r2 = pointer to uboot provided cmdline or external DTB in mem
109 ; These are handled later in handle_uboot_args()
111 st r1, [@uboot_magic]
114 ; setup "current" tsk and optionally cache it in dedicated r25
116 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
118 ; setup stack (fp, sp)
121 ; tsk->thread_info is really a PAGE, whose bottom hoists stack
122 GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
124 j start_kernel ; "C" entry point
128 ;----------------------------------------------------------------
129 ; First lines of code run by secondary before jumping to 'C'
130 ;----------------------------------------------------------------
131 .section .text, "ax",@progbits
132 ENTRY(first_lines_of_secondary)
134 ; setup per-cpu idle task as "current" on this CPU
135 ld r0, [@secondary_idle_tsk]
136 SET_CURR_TASK_ON_CPU r0, r1
138 ; setup stack (fp, sp)
141 ; set it's stack base to tsk->thread_info bottom
142 GET_TSK_STACK_BASE r0, sp
144 j start_kernel_secondary
145 END(first_lines_of_secondary)