1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __ASM_ARC_ENTRY_ARCV2_H
4 #define __ASM_ARC_ENTRY_ARCV2_H
6 #include <asm/asm-offsets.h>
7 #include <asm/irqflags-arcv2.h>
8 #include <asm/thread_info.h> /* For THREAD_SIZE */
10 /*------------------------------------------------------------------------*/
11 .macro INTERRUPT_PROLOGUE called_from
13 ; Before jumping to Interrupt Vector, hardware micro-ops did following:
14 ; 1. SP auto-switched to kernel mode stack
15 ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0)
16 ; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32
18 ; Now manually save: r12, sp, fp, gp, r25
20 #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
21 .ifnc \called_from, exception
22 st.as r9, [sp, -10] ; save r9 in it's final stack slot
23 sub sp, sp, 12 ; skip JLI, LDI, EI
33 sub sp, sp, 4 ; skip r9
47 #ifdef CONFIG_ARC_HAS_ACCL_REGS
55 ; Saving pt_regs->sp correctly requires some extra work due to the way
56 ; Auto stack switch works
57 ; - U mode: retrieve it from AUX_USER_SP
58 ; - K mode: add the offset from current SP where H/w starts auto push
60 ; Utilize the fact that Z bit is set if Intr taken in U mode
62 add.nz r9, r9, SZ_PT_REGS - PT_sp - 4
72 #ifdef CONFIG_ARC_CURR_IN_REG
74 GET_CURR_TASK_ON_CPU r25
79 .ifnc \called_from, exception
80 sub sp, sp, 12 ; BTA/ECR/orig_r0 placeholder per pt_regs
85 /*------------------------------------------------------------------------*/
86 .macro INTERRUPT_EPILOGUE called_from
88 .ifnc \called_from, exception
89 add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss
92 #ifdef CONFIG_ARC_CURR_IN_REG
101 ; Don't touch AUX_USER_SP if returning to K mode (Z bit set)
102 ; (Z bit set on K mode is inverse of INTERRUPT_PROLOGUE)
111 #ifdef CONFIG_ARC_HAS_ACCL_REGS
116 #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
117 .ifnc \called_from, exception
138 add sp, sp, 12 ; skip JLI, LDI, EI
139 ld.as r9, [sp, -10] ; reload r9 which got clobbered
145 /*------------------------------------------------------------------------*/
146 .macro EXCEPTION_PROLOGUE
148 ; Before jumping to Exception Vector, hardware micro-ops did following:
149 ; 1. SP auto-switched to kernel mode stack
150 ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1,K:0)
152 ; Now manually save the complete reg file
154 PUSH r9 ; freeup a register: slot of erstatus
157 sub sp, sp, 12 ; skip JLI, LDI, EI
166 ld.as r9, [sp, 10] ; load stashed r9 (status32 stack slot)
168 st.as r10, [sp, 10] ; save status32 at it's right stack slot
181 ; -- for interrupts, regs above are auto-saved by h/w in that order --
182 ; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25)
184 ; Set Z flag if this was from U mode (expected by INTERRUPT_PROLOGUE)
185 ; Although H/w exception micro-ops do set Z flag for U mode (just like
186 ; for interrupts), it could get clobbered in case we soft land here from
187 ; a TLB Miss exception handler (tlbex.S)
189 and r10, r10, STATUS_U_MASK
190 xor.f 0, r10, STATUS_U_MASK
192 INTERRUPT_PROLOGUE exception
195 PUSHAX ecr ; r9 contains ECR, expected by EV_Trap
200 /*------------------------------------------------------------------------*/
201 .macro EXCEPTION_EPILOGUE
203 ; Assumes r0 has PT_status32
204 btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE
206 add sp, sp, 8 ; orig_r0/ECR don't need restoring
209 INTERRUPT_EPILOGUE exception
231 add sp, sp, 12 ; skip JLI, LDI, EI
235 ld.as r9, [sp, -12] ; reload r9 which got clobbered
238 .macro FAKE_RET_FROM_EXCPN
240 bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)
241 or r9, r9, STATUS_IE_MASK
245 /* Get thread_info of "current" tsk */
246 .macro GET_CURR_THR_INFO_FROM_SP reg
247 bmskn \reg, sp, THREAD_SHIFT - 1
250 /* Get CPU-ID of this core */
251 .macro GET_CPU_ID reg
253 xbfu \reg, \reg, 0xE8 /* 00111 01000 */