1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
5 * - The address HAS to be 64-bit aligned
8 #ifndef _ASM_ARC_ATOMIC64_ARCV2_H
9 #define _ASM_ARC_ATOMIC64_ARCV2_H
12 s64 __aligned(8) counter;
15 #define ATOMIC64_INIT(a) { (a) }
17 static inline s64 arch_atomic64_read(const atomic64_t *v)
29 static inline void arch_atomic64_set(atomic64_t *v, s64 a)
32 * This could have been a simple assignment in "C" but would need
33 * explicit volatile. Otherwise gcc optimizers could elide the store
34 * which borked atomic64 self-test
35 * In the inline asm version, memory clobber needed for exact same
36 * reason, to tell gcc about the store.
38 * This however is not needed for sibling atomic64_add() etc since both
39 * load/store are explicitly done in inline asm. As long as API is used
40 * for each access, gcc has no way to optimize away any load/store
45 : "r"(a), "r"(&v->counter)
49 #define ATOMIC64_OP(op, op1, op2) \
50 static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \
54 __asm__ __volatile__( \
56 " llockd %0, [%1] \n" \
57 " " #op1 " %L0, %L0, %L2 \n" \
58 " " #op2 " %H0, %H0, %H2 \n" \
59 " scondd %0, [%1] \n" \
62 : "r"(&v->counter), "ir"(a) \
66 #define ATOMIC64_OP_RETURN(op, op1, op2) \
67 static inline s64 arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
71 __asm__ __volatile__( \
73 " llockd %0, [%1] \n" \
74 " " #op1 " %L0, %L0, %L2 \n" \
75 " " #op2 " %H0, %H0, %H2 \n" \
76 " scondd %0, [%1] \n" \
79 : "r"(&v->counter), "ir"(a) \
85 #define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
86 #define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
88 #define ATOMIC64_FETCH_OP(op, op1, op2) \
89 static inline s64 arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
93 __asm__ __volatile__( \
95 " llockd %0, [%2] \n" \
96 " " #op1 " %L1, %L0, %L3 \n" \
97 " " #op2 " %H1, %H0, %H3 \n" \
98 " scondd %1, [%2] \n" \
100 : "=&r"(orig), "=&r"(val) \
101 : "r"(&v->counter), "ir"(a) \
107 #define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
108 #define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
110 #define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
111 #define arch_atomic64_fetch_andnot_relaxed arch_atomic64_fetch_andnot_relaxed
112 #define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
113 #define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
115 #define ATOMIC64_OPS(op, op1, op2) \
116 ATOMIC64_OP(op, op1, op2) \
117 ATOMIC64_OP_RETURN(op, op1, op2) \
118 ATOMIC64_FETCH_OP(op, op1, op2)
120 ATOMIC64_OPS(add, add.f, adc)
121 ATOMIC64_OPS(sub, sub.f, sbc)
124 #define ATOMIC64_OPS(op, op1, op2) \
125 ATOMIC64_OP(op, op1, op2) \
126 ATOMIC64_FETCH_OP(op, op1, op2)
128 ATOMIC64_OPS(and, and, and)
129 ATOMIC64_OPS(andnot, bic, bic)
130 ATOMIC64_OPS(or, or, or)
131 ATOMIC64_OPS(xor, xor, xor)
133 #define arch_atomic64_andnot arch_atomic64_andnot
136 #undef ATOMIC64_FETCH_OP
137 #undef ATOMIC64_OP_RETURN
141 arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new)
147 __asm__ __volatile__(
148 "1: llockd %0, [%1] \n"
149 " brne %L0, %L2, 2f \n"
150 " brne %H0, %H2, 2f \n"
151 " scondd %3, [%1] \n"
155 : "r"(ptr), "ir"(expected), "r"(new)
156 : "cc"); /* memory clobber comes from smp_mb() */
162 #define arch_atomic64_cmpxchg arch_atomic64_cmpxchg
164 static inline s64 arch_atomic64_xchg(atomic64_t *ptr, s64 new)
170 __asm__ __volatile__(
171 "1: llockd %0, [%1] \n"
172 " scondd %2, [%1] \n"
177 : "cc"); /* memory clobber comes from smp_mb() */
183 #define arch_atomic64_xchg arch_atomic64_xchg
185 static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
191 __asm__ __volatile__(
192 "1: llockd %0, [%1] \n"
193 " sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
194 " sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
195 " brlt %H0, 0, 2f \n"
196 " scondd %0, [%1] \n"
201 : "cc"); /* memory clobber comes from smp_mb() */
207 #define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
209 static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
215 __asm__ __volatile__(
216 "1: llockd %0, [%2] \n"
217 " brne %L0, %L4, 2f # continue to add since v != u \n"
218 " breq.d %H0, %H4, 3f # return since v == u \n"
220 " add.f %L1, %L0, %L3 \n"
221 " adc %H1, %H0, %H3 \n"
222 " scondd %1, [%2] \n"
225 : "=&r"(old), "=&r" (temp)
226 : "r"(&v->counter), "r"(a), "r"(u)
227 : "cc"); /* memory clobber comes from smp_mb() */
233 #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless