2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device Tree for ARC HS Development Kit
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
19 compatible = "snps,hsdk";
25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
38 compatible = "snps,archs38";
45 compatible = "snps,archs38";
52 compatible = "snps,archs38";
59 compatible = "snps,archs38";
65 input_clk: input-clk {
67 compatible = "fixed-clock";
68 clock-frequency = <33333333>;
71 cpu_intc: cpu-interrupt-controller {
72 compatible = "snps,archs-intc";
74 #interrupt-cells = <1>;
77 idu_intc: idu-interrupt-controller {
78 compatible = "snps,archs-idu-intc";
80 #interrupt-cells = <1>;
81 interrupt-parent = <&cpu_intc>;
85 compatible = "snps,archs-pct";
86 interrupt-parent = <&cpu_intc>;
90 /* TIMER0 with interrupt for clockevent */
92 compatible = "snps,arc-timer";
94 interrupt-parent = <&cpu_intc>;
98 /* 64-bit Global Free Running Counter */
100 compatible = "snps,archs-timer-gfrc";
101 clocks = <&core_clk>;
105 compatible = "simple-bus";
106 #address-cells = <1>;
108 interrupt-parent = <&idu_intc>;
110 ranges = <0x00000000 0xf0000000 0x10000000>;
112 cgu_rst: reset-controller@8a0 {
113 compatible = "snps,hsdk-reset";
115 reg = <0x8A0 0x4>, <0xFF0 0x4>;
118 core_clk: core-clk@0 {
119 compatible = "snps,hsdk-core-pll-clock";
120 reg = <0x00 0x10>, <0x14B8 0x4>;
122 clocks = <&input_clk>;
125 * Set initial core pll output frequency to 1GHz.
126 * It will be applied at the core pll driver probing
129 assigned-clocks = <&core_clk>;
130 assigned-clock-rates = <1000000000>;
133 serial: serial@5000 {
134 compatible = "snps,dw-apb-uart";
135 reg = <0x5000 0x100>;
136 clock-frequency = <33330000>;
144 compatible = "fixed-clock";
145 clock-frequency = <400000000>;
149 mmcclk_ciu: mmcclk-ciu {
150 compatible = "fixed-clock";
152 * DW sdio controller has external ciu clock divider
153 * controlled via register in SDIO IP. Due to its
154 * unexpected default value (it should divide by 1
155 * but it divides by 8) SDIO IP uses wrong clock and
156 * works unstable (see STAR 9001204800)
157 * We switched to the minimum possible value of the
158 * divisor (div-by-2) in HSDK platform code.
159 * So add temporary fix and change clock frequency
160 * to 50000000 Hz until we fix dw sdio driver itself.
162 clock-frequency = <50000000>;
166 mmcclk_biu: mmcclk-biu {
167 compatible = "fixed-clock";
168 clock-frequency = <400000000>;
172 gmac: ethernet@8000 {
173 #interrupt-cells = <1>;
174 compatible = "snps,dwmac";
175 reg = <0x8000 0x2000>;
177 interrupt-names = "macirq";
178 phy-mode = "rgmii-id";
180 snps,multicast-filter-bins = <256>;
182 clock-names = "stmmaceth";
183 phy-handle = <&phy0>;
184 resets = <&cgu_rst HSDK_ETH_RESET>;
185 reset-names = "stmmaceth";
186 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
189 tx-fifo-depth = <4096>;
190 rx-fifo-depth = <4096>;
193 #address-cells = <1>;
195 compatible = "snps,dwmac-mdio";
196 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
198 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
199 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
200 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
206 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
207 reg = <0x60000 0x100>;
213 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
214 reg = <0x40000 0x100>;
220 compatible = "altr,socfpga-dw-mshc";
221 reg = <0xa000 0x400>;
224 card-detect-delay = <200>;
225 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
226 clock-names = "biu", "ciu";
234 #address-cells = <1>;
236 device_type = "memory";
237 reg = <0x80000000 0x40000000>; /* 1 GiB */