2 * Support for peripherals on the AXS10x mainboard
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
17 compatible = "simple-bus";
20 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
21 interrupt-parent = <&mb_intc>;
23 creg_rst: reset-controller@11220 {
24 compatible = "snps,axs10x-reset";
29 i2sclk: i2sclk@100a0 {
30 compatible = "snps,axs10x-i2s-pll-clock";
32 clocks = <&i2spll_clk>;
37 i2spll_clk: i2spll_clk {
38 compatible = "fixed-clock";
39 clock-frequency = <27000000>;
44 compatible = "fixed-clock";
45 clock-frequency = <50000000>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "fixed-clock";
58 * DW sdio controller has external ciu clock divider
59 * controlled via register in SDIO IP. It divides
60 * sdio_ref_clk (which comes from CGU) by 16 for
61 * default. So default mmcclk clock (which comes
62 * to sdk_in) is 25000000 Hz.
64 clock-frequency = <25000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <74250000>;
75 gmac: ethernet@0x18000 {
76 #interrupt-cells = <1>;
77 compatible = "snps,dwmac";
78 reg = < 0x18000 0x2000 >;
80 interrupt-names = "macirq";
83 snps,multicast-filter-bins = <256>;
85 clock-names = "stmmaceth";
87 resets = <&creg_rst 5>;
88 reset-names = "stmmaceth";
89 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
93 compatible = "generic-ehci";
94 reg = < 0x40000 0x100 >;
99 compatible = "generic-ohci";
100 reg = < 0x60000 0x100 >;
105 * According to DW Mobile Storage databook it is required
106 * to use "Hold Register" if card is enumerated in SDR12 or
109 * Utilization of "Hold Register" is already implemented via
110 * dw_mci_pltfm_prepare_command() which in its turn gets
111 * used through dw_mci_drv_data->prepare_command call-back.
112 * This call-back is used in Altera Socfpga platform and so
113 * we may reuse it saying that we're compatible with their
114 * "altr,socfpga-dw-mshc".
116 * Most probably "Hold Register" utilization is platform-
117 * independent requirement which means that single unified
118 * "snps,dw-mshc" should be enough for all users of DW MMC once
119 * dw_mci_pltfm_prepare_command() is used in generic platform
123 compatible = "altr,socfpga-dw-mshc";
124 reg = < 0x15000 0x400 >;
126 card-detect-delay = < 200 >;
127 clocks = <&apbclk>, <&mmcclk>;
128 clock-names = "biu", "ciu";
134 compatible = "snps,dw-apb-uart";
135 reg = <0x20000 0x100>;
136 clock-frequency = <33333333>;
144 compatible = "snps,dw-apb-uart";
145 reg = <0x21000 0x100>;
146 clock-frequency = <33333333>;
153 /* UART muxed with USB data port (ttyS3) */
155 compatible = "snps,dw-apb-uart";
156 reg = <0x22000 0x100>;
157 clock-frequency = <33333333>;
165 compatible = "snps,designware-i2c";
166 reg = <0x1d000 0x100>;
167 clock-frequency = <400000>;
173 compatible = "snps,designware-i2s";
174 reg = <0x1e000 0x100>;
175 clocks = <&i2sclk 0>;
176 clock-names = "i2sclk";
178 #sound-dai-cells = <0>;
182 compatible = "snps,designware-i2c";
183 #address-cells = <1>;
185 reg = <0x1f000 0x100>;
186 clock-frequency = <400000>;
191 compatible="adi,adv7511";
194 adi,input-depth = <8>;
195 adi,input-colorspace = "rgb";
196 adi,input-clock = "1x";
197 adi,clock-delay = <0x03>;
198 #sound-dai-cells = <0>;
201 #address-cells = <1>;
207 adv7511_input:endpoint {
208 remote-endpoint = <&pgu_output>;
215 adv7511_output: endpoint {
216 remote-endpoint = <&hdmi_connector_in>;
223 compatible = "atmel,24c01";
229 compatible = "atmel,24c04";
236 compatible = "hdmi-connector";
239 hdmi_connector_in: endpoint {
240 remote-endpoint = <&adv7511_output>;
246 compatible = "snps,dw-apb-gpio";
247 reg = <0x13000 0x1000>;
248 #address-cells = <1>;
251 gpio0_banka: gpio-controller@0 {
252 compatible = "snps,dw-apb-gpio-port";
255 snps,nr-gpios = <32>;
259 gpio0_bankb: gpio-controller@1 {
260 compatible = "snps,dw-apb-gpio-port";
267 gpio0_bankc: gpio-controller@2 {
268 compatible = "snps,dw-apb-gpio-port";
277 compatible = "snps,dw-apb-gpio";
278 reg = <0x14000 0x1000>;
279 #address-cells = <1>;
282 gpio1_banka: gpio-controller@0 {
283 compatible = "snps,dw-apb-gpio-port";
286 snps,nr-gpios = <30>;
290 gpio1_bankb: gpio-controller@1 {
291 compatible = "snps,dw-apb-gpio-port";
294 snps,nr-gpios = <10>;
298 gpio1_bankc: gpio-controller@2 {
299 compatible = "snps,dw-apb-gpio-port";
308 compatible = "snps,arcpgu";
309 reg = <0x17000 0x400>;
310 encoder-slave = <&adv7511>;
312 clock-names = "pxlclk";
313 memory-region = <&frame_buffer>;
315 pgu_output: endpoint {
316 remote-endpoint = <&adv7511_input>;
322 compatible = "simple-audio-card";
323 simple-audio-card,name = "AXS10x HDMI Audio";
324 simple-audio-card,format = "i2s";
325 simple-audio-card,cpu {
328 simple-audio-card,codec {
329 sound-dai = <&adv7511>;