arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 i2sclk: i2sclk@100a0 {
  20                         compatible = "snps,axs10x-i2s-pll-clock";
  21                         reg = <0x100a0 0x10>;
  22                         clocks = <&i2spll_clk>;
  23                         #clock-cells = <0>;
  24                 };
  25
  26                 clocks {
  27                         i2spll_clk: i2spll_clk {
  28                                 compatible = "fixed-clock";
  29                                 clock-frequency = <27000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         i2cclk: i2cclk {
  34                                 compatible = "fixed-clock";
  35                                 clock-frequency = <50000000>;
  36                                 #clock-cells = <0>;
  37                         };
  38
  39                         apbclk: apbclk {
  40                                 compatible = "fixed-clock";
  41                                 clock-frequency = <50000000>;
  42                                 #clock-cells = <0>;
  43                         };
  44
  45                         mmcclk: mmcclk {
  46                                 compatible = "fixed-clock";
  47                                 /*
  48                                  * DW sdio controller has external ciu clock divider
  49                                  * controlled via register in SDIO IP. It divides
  50                                  * sdio_ref_clk (which comes from CGU) by 16 for
  51                                  * default. So default mmcclk clock (which comes
  52                                  * to sdk_in) is 25000000 Hz.
  53                                  */
  54                                 clock-frequency = <25000000>;
  55                                 #clock-cells = <0>;
  56                         };
  57
  58                         pguclk: pguclk {
  59                                 #clock-cells = <0>;
  60                                 compatible = "fixed-clock";
  61                                 clock-frequency = <74250000>;
  62                         };
  63                 };
  64
  65                 ethernet@0x18000 {
  66                         #interrupt-cells = <1>;
  67                         compatible = "snps,dwmac";
  68                         reg = < 0x18000 0x2000 >;
  69                         interrupts = < 4 >;
  70                         interrupt-names = "macirq";
  71                         phy-mode = "rgmii";
  72                         snps,pbl = < 32 >;
  73                         snps,multicast-filter-bins = <256>;
  74                         clocks = <&apbclk>;
  75                         clock-names = "stmmaceth";
  76                         max-speed = <100>;
  77                 };
  78
  79                 ehci@0x40000 {
  80                         compatible = "generic-ehci";
  81                         reg = < 0x40000 0x100 >;
  82                         interrupts = < 8 >;
  83                 };
  84
  85                 ohci@0x60000 {
  86                         compatible = "generic-ohci";
  87                         reg = < 0x60000 0x100 >;
  88                         interrupts = < 8 >;
  89                 };
  90
  91                 /*
  92                  * According to DW Mobile Storage databook it is required
  93                  * to use  "Hold Register" if card is enumerated in SDR12 or
  94                  * SDR25 modes.
  95                  *
  96                  * Utilization of "Hold Register" is already implemented via
  97                  * dw_mci_pltfm_prepare_command() which in its turn gets
  98                  * used through dw_mci_drv_data->prepare_command call-back.
  99                  * This call-back is used in Altera Socfpga platform and so
 100                  * we may reuse it saying that we're compatible with their
 101                  * "altr,socfpga-dw-mshc".
 102                  *
 103                  * Most probably "Hold Register" utilization is platform-
 104                  * independent requirement which means that single unified
 105                  * "snps,dw-mshc" should be enough for all users of DW MMC once
 106                  * dw_mci_pltfm_prepare_command() is used in generic platform
 107                  * code.
 108                  */
 109                 mmc@0x15000 {
 110                         compatible = "altr,socfpga-dw-mshc";
 111                         reg = < 0x15000 0x400 >;
 112                         fifo-depth = < 16 >;
 113                         card-detect-delay = < 200 >;
 114                         clocks = <&apbclk>, <&mmcclk>;
 115                         clock-names = "biu", "ciu";
 116                         interrupts = < 7 >;
 117                         bus-width = < 4 >;
 118                 };
 119
 120                 uart@0x20000 {
 121                         compatible = "snps,dw-apb-uart";
 122                         reg = <0x20000 0x100>;
 123                         clock-frequency = <33333333>;
 124                         interrupts = <17>;
 125                         baud = <115200>;
 126                         reg-shift = <2>;
 127                         reg-io-width = <4>;
 128                 };
 129
 130                 uart@0x21000 {
 131                         compatible = "snps,dw-apb-uart";
 132                         reg = <0x21000 0x100>;
 133                         clock-frequency = <33333333>;
 134                         interrupts = <18>;
 135                         baud = <115200>;
 136                         reg-shift = <2>;
 137                         reg-io-width = <4>;
 138                 };
 139
 140                 /* UART muxed with USB data port (ttyS3) */
 141                 uart@0x22000 {
 142                         compatible = "snps,dw-apb-uart";
 143                         reg = <0x22000 0x100>;
 144                         clock-frequency = <33333333>;
 145                         interrupts = <19>;
 146                         baud = <115200>;
 147                         reg-shift = <2>;
 148                         reg-io-width = <4>;
 149                 };
 150
 151                 i2c@0x1d000 {
 152                         compatible = "snps,designware-i2c";
 153                         reg = <0x1d000 0x100>;
 154                         clock-frequency = <400000>;
 155                         clocks = <&i2cclk>;
 156                         interrupts = <14>;
 157                 };
 158
 159                 i2s: i2s@1e000 {
 160                         compatible = "snps,designware-i2s";
 161                         reg = <0x1e000 0x100>;
 162                         clocks = <&i2sclk 0>;
 163                         clock-names = "i2sclk";
 164                         interrupts = <15>;
 165                         #sound-dai-cells = <0>;
 166                 };
 167
 168                 i2c@0x1f000 {
 169                         compatible = "snps,designware-i2c";
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         reg = <0x1f000 0x100>;
 173                         clock-frequency = <400000>;
 174                         clocks = <&i2cclk>;
 175                         interrupts = <16>;
 176
 177                         adv7511:adv7511@39{
 178                                 compatible="adi,adv7511";
 179                                 reg = <0x39>;
 180                                 interrupts = <23>;
 181                                 adi,input-depth = <8>;
 182                                 adi,input-colorspace = "rgb";
 183                                 adi,input-clock = "1x";
 184                                 adi,clock-delay = <0x03>;
 185                                 #sound-dai-cells = <0>;
 186
 187                                 ports {
 188                                         #address-cells = <1>;
 189                                         #size-cells = <0>;
 190
 191                                         /* RGB/YUV input */
 192                                         port@0 {
 193                                                 reg = <0>;
 194                                                 adv7511_input:endpoint {
 195                                                 remote-endpoint = <&pgu_output>;
 196                                                 };
 197                                         };
 198
 199                                         /* HDMI output */
 200                                         port@1 {
 201                                                 reg = <1>;
 202                                                 adv7511_output: endpoint {
 203                                                         remote-endpoint = <&hdmi_connector_in>;
 204                                                 };
 205                                         };
 206                                 };
 207                         };
 208
 209                         eeprom@0x54{
 210                                 compatible = "24c01";
 211                                 reg = <0x54>;
 212                                 pagesize = <0x8>;
 213                         };
 214
 215                         eeprom@0x57{
 216                                 compatible = "24c04";
 217                                 reg = <0x57>;
 218                                 pagesize = <0x8>;
 219                         };
 220                 };
 221
 222                 hdmi0: connector {
 223                         compatible = "hdmi-connector";
 224                         type = "a";
 225                         port {
 226                                 hdmi_connector_in: endpoint {
 227                                         remote-endpoint = <&adv7511_output>;
 228                                 };
 229                         };
 230                 };
 231
 232                 gpio0:gpio@13000 {
 233                         compatible = "snps,dw-apb-gpio";
 234                         reg = <0x13000 0x1000>;
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237
 238                         gpio0_banka: gpio-controller@0 {
 239                                 compatible = "snps,dw-apb-gpio-port";
 240                                 gpio-controller;
 241                                 #gpio-cells = <2>;
 242                                 snps,nr-gpios = <32>;
 243                                 reg = <0>;
 244                         };
 245
 246                         gpio0_bankb: gpio-controller@1 {
 247                                 compatible = "snps,dw-apb-gpio-port";
 248                                 gpio-controller;
 249                                 #gpio-cells = <2>;
 250                                 snps,nr-gpios = <8>;
 251                                 reg = <1>;
 252                         };
 253
 254                         gpio0_bankc: gpio-controller@2 {
 255                                 compatible = "snps,dw-apb-gpio-port";
 256                                 gpio-controller;
 257                                 #gpio-cells = <2>;
 258                                 snps,nr-gpios = <8>;
 259                                 reg = <2>;
 260                         };
 261                 };
 262
 263                 gpio1:gpio@14000 {
 264                         compatible = "snps,dw-apb-gpio";
 265                         reg = <0x14000 0x1000>;
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268
 269                         gpio1_banka: gpio-controller@0 {
 270                                 compatible = "snps,dw-apb-gpio-port";
 271                                 gpio-controller;
 272                                 #gpio-cells = <2>;
 273                                 snps,nr-gpios = <30>;
 274                                 reg = <0>;
 275                         };
 276
 277                         gpio1_bankb: gpio-controller@1 {
 278                                 compatible = "snps,dw-apb-gpio-port";
 279                                 gpio-controller;
 280                                 #gpio-cells = <2>;
 281                                 snps,nr-gpios = <10>;
 282                                 reg = <1>;
 283                         };
 284
 285                         gpio1_bankc: gpio-controller@2 {
 286                                 compatible = "snps,dw-apb-gpio-port";
 287                                 gpio-controller;
 288                                 #gpio-cells = <2>;
 289                                 snps,nr-gpios = <8>;
 290                                 reg = <2>;
 291                         };
 292                 };
 293
 294                 pgu@17000 {
 295                         compatible = "snps,arcpgu";
 296                         reg = <0x17000 0x400>;
 297                         encoder-slave = <&adv7511>;
 298                         clocks = <&pguclk>;
 299                         clock-names = "pxlclk";
 300                         memory-region = <&frame_buffer>;
 301                         port {
 302                                 pgu_output: endpoint {
 303                                         remote-endpoint = <&adv7511_input>;
 304                                 };
 305                         };
 306                 };
 307
 308                 sound_playback {
 309                         compatible = "simple-audio-card";
 310                         simple-audio-card,name = "AXS10x HDMI Audio";
 311                         simple-audio-card,format = "i2s";
 312                         simple-audio-card,cpu {
 313                                 sound-dai = <&i2s>;
 314                         };
 315                         simple-audio-card,codec {
 316                                 sound-dai = <&adv7511>;
 317                         };
 318                 };
 319         };
 320 };