1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
29 select GENERIC_IOREMAP
30 select GENERIC_STRNCPY_FROM_USER if MMU
31 select GENERIC_STRNLEN_USER if MMU
33 select HAVE_ARCH_TRACEHOOK
34 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
35 select HAVE_DEBUG_STACKOVERFLOW
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_IOREMAP_PROT
38 select HAVE_KERNEL_GZIP
39 select HAVE_KERNEL_LZMA
41 select HAVE_KRETPROBES
42 select HAVE_REGS_AND_STACK_ACCESS_API
43 select HAVE_MOD_ARCH_SPECIFIC
44 select HAVE_PERF_EVENTS
45 select HAVE_SYSCALL_TRACEPOINTS
47 select LOCK_MM_AND_FIND_VMA
48 select MODULES_USE_ELF_RELA
50 select OF_EARLY_FLATTREE
51 select PCI_SYSCALL if PCI
52 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
53 select TRACE_IRQFLAGS_SUPPORT
55 config LOCKDEP_SUPPORT
58 config SCHED_OMIT_FRAME_POINTER
64 config ARCH_FLATMEM_ENABLE
73 config GENERIC_CALIBRATE_DELAY
76 config GENERIC_HWEIGHT
79 config STACKTRACE_SUPPORT
83 menu "ARC Architecture Configuration"
85 menu "ARC Platform/SoC/Board"
87 source "arch/arc/plat-tb10x/Kconfig"
88 source "arch/arc/plat-axs10x/Kconfig"
89 source "arch/arc/plat-hsdk/Kconfig"
94 prompt "ARC Instruction Set"
99 select CPU_NO_EFFICIENT_FFS
101 The original ARC ISA of ARC600/700 cores
105 select ARC_TIMERS_64BIT
107 ISA for the Next Generation ARC-HS cores
111 menu "ARC CPU Configuration"
115 default ARC_CPU_770 if ISA_ARCOMPACT
116 default ARC_CPU_HS if ISA_ARCV2
120 depends on ISA_ARCOMPACT
123 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
124 This core has a bunch of cool new features:
125 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
126 Shared Address Spaces (for sharing TLB entries in MMU)
127 -Caches: New Prog Model, Region Flush
128 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
134 Support for ARC HS38x Cores based on ARCv2 ISA
135 The notable features are:
136 - SMP configurations of up to 4 cores with coherency
137 - Optional L2 Cache and IO-Coherency
138 - Revised Interrupt Architecture (multiple priorites, reg banks,
139 auto stack switch, auto regfile save/restore)
140 - MMUv4 (PIPT dcache, Huge Pages)
142 * 64bit load/store: LDD, STD
143 * Hardware assisted divide/remainder: DIV, REM
144 * Function prologue/epilogue: ENTER_S, LEAVE_S
145 * IRQ enable/disable: CLRI, SETI
146 * pop count: FFS, FLS
147 * SETcc, BMSKN, XBFU...
152 string "Override default -mcpu compiler flag"
155 Override default -mcpu=xxx compiler flag (which is set depending on
156 the ISA version) with the specified value.
157 NOTE: If specified flag isn't supported by current compiler the
158 ISA default value will be used as a fallback.
160 config CPU_BIG_ENDIAN
161 bool "Enable Big Endian Mode"
163 Build kernel for Big Endian Mode of ARC CPU
166 bool "Symmetric Multi-Processing"
167 select ARC_MCIP if ISA_ARCV2
169 This enables support for systems with more than one CPU.
174 int "Maximum number of CPUs (2-4096)"
178 config ARC_SMP_HALT_ON_RESET
179 bool "Enable Halt-on-reset boot mode"
181 In SMP configuration cores can be configured as Halt-on-reset
182 or they could all start at same time. For Halt-on-reset, non
183 masters are parked until Master kicks them so they can start off
184 at designated entry point. For other case, all jump to common
185 entry point and spin wait for Master's signal.
190 bool "ARConnect Multicore IP (MCIP) Support "
194 This IP block enables SMP in ARC-HS38 cores.
195 It provides for cross-core interrupts, multi-core debug
196 hardware semaphores, shared memory,....
199 bool "Enable Cache Support"
204 config ARC_CACHE_LINE_SHIFT
205 int "Cache Line Length (as power of 2)"
209 Starting with ARC700 4.9, Cache line length is configurable,
210 This option specifies "N", with Line-len = 2 power N
211 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
212 Linux only supports same line lengths for I and D caches.
214 config ARC_HAS_ICACHE
215 bool "Use Instruction Cache"
218 config ARC_HAS_DCACHE
219 bool "Use Data Cache"
222 config ARC_CACHE_PAGES
223 bool "Per Page Cache Control"
225 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
227 This can be used to over-ride the global I/D Cache Enable on a
228 per-page basis (but only for pages accessed via MMU such as
229 Kernel Virtual address or User Virtual Address)
230 TLB entries have a per-page Cache Enable Bit.
231 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
232 Global DISABLE + Per Page ENABLE won't work
239 Single Cycle RAMS to store Fast Path Code
242 int "ICCM Size in KB"
244 depends on ARC_HAS_ICCM
249 Single Cycle RAMS to store Fast Path Data
252 int "DCCM Size in KB"
254 depends on ARC_HAS_DCCM
257 hex "DCCM map address"
259 depends on ARC_HAS_DCCM
263 default ARC_MMU_V3 if ISA_ARCOMPACT
264 default ARC_MMU_V4 if ISA_ARCV2
268 depends on ISA_ARCOMPACT
270 Introduced with ARC700 4.10: New Features
271 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
272 Shared Address Spaces (SASID)
282 prompt "MMU Page Size"
283 default ARC_PAGE_SIZE_8K
285 config ARC_PAGE_SIZE_8K
287 select HAVE_PAGE_SIZE_8KB
289 Choose between 8k vs 16k
291 config ARC_PAGE_SIZE_16K
292 select HAVE_PAGE_SIZE_16KB
295 config ARC_PAGE_SIZE_4K
297 select HAVE_PAGE_SIZE_4KB
298 depends on ARC_MMU_V3 || ARC_MMU_V4
303 prompt "MMU Super Page Size"
304 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
305 default ARC_HUGEPAGE_2M
307 config ARC_HUGEPAGE_2M
310 config ARC_HUGEPAGE_16M
315 config PGTABLE_LEVELS
316 int "Number of Page table levels"
319 config ARC_COMPACT_IRQ_LEVELS
320 depends on ISA_ARCOMPACT
321 bool "Setup Timer IRQ as high Priority"
322 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
325 config ARC_FPU_SAVE_RESTORE
326 bool "Enable FPU state persistence across context switch"
328 ARCompact FPU has internal registers to assist with Double precision
329 Floating Point operations. There are control and stauts registers
330 for floating point exceptions and rounding modes. These are
331 preserved across task context switch when enabled.
337 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
339 depends on !ARC_CANT_LLSC
342 bool "Insn: SWAPE (endian-swap)"
347 config ARC_USE_UNALIGNED_MEM_ACCESS
348 bool "Enable unaligned access in HW"
350 select HAVE_EFFICIENT_UNALIGNED_ACCESS
352 The ARC HS architecture supports unaligned memory access
353 which is disabled by default. Enable unaligned access in
354 hardware and use software to use it
357 bool "Insn: 64bit LDD/STD"
359 Enable gcc to generate 64-bit load/store instructions
360 ISA mandates even/odd registers to allow encoding of two
361 dest operands with 2 possible source operands.
364 config ARC_HAS_DIV_REM
365 bool "Insn: div, divu, rem, remu"
368 config ARC_HAS_ACCL_REGS
369 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
372 Depending on the configuration, CPU can contain accumulator reg-pair
373 (also referred to as r58:r59). These can also be used by gcc as GPR so
374 kernel needs to save/restore per process
376 config ARC_DSP_HANDLED
379 config ARC_DSP_SAVE_RESTORE_REGS
386 Depending on the configuration, CPU can contain DSP registers
387 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
388 Below are options describing how to handle these registers in
389 interrupt entry / exit and in context switch.
392 bool "No DSP extension presence in HW"
394 No DSP extension presence in HW
396 config ARC_DSP_KERNEL
397 bool "DSP extension in HW, no support for userspace"
398 select ARC_HAS_ACCL_REGS
399 select ARC_DSP_HANDLED
401 DSP extension presence in HW, no support for DSP-enabled userspace
402 applications. We don't save / restore DSP registers and only do
403 some minimal preparations so userspace won't be able to break kernel
405 config ARC_DSP_USERSPACE
406 bool "Support DSP for userspace apps"
407 select ARC_HAS_ACCL_REGS
408 select ARC_DSP_HANDLED
409 select ARC_DSP_SAVE_RESTORE_REGS
411 DSP extension presence in HW, support save / restore DSP registers to
412 run DSP-enabled userspace applications
414 config ARC_DSP_AGU_USERSPACE
415 bool "Support DSP with AGU for userspace apps"
416 select ARC_HAS_ACCL_REGS
417 select ARC_DSP_HANDLED
418 select ARC_DSP_SAVE_RESTORE_REGS
420 DSP and AGU extensions presence in HW, support save / restore DSP
421 and AGU registers to run DSP-enabled userspace applications
424 config ARC_IRQ_NO_AUTOSAVE
425 bool "Disable hardware autosave regfile on interrupts"
428 On HS cores, taken interrupt auto saves the regfile on stack.
429 This is programmable and can be optionally disabled in which case
430 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
432 config ARC_LPB_DISABLE
433 bool "Disable loop buffer (LPB)"
435 On HS cores, loop buffer (LPB) is programmable in runtime and can
436 be optionally disabled.
440 endmenu # "ARC CPU Configuration"
442 config LINUX_LINK_BASE
443 hex "Kernel link address"
446 ARC700 divides the 32 bit phy address space into two equal halves
447 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
448 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
449 Typically Linux kernel is linked at the start of untransalted addr,
450 hence the default value of 0x8zs.
451 However some customers have peripherals mapped at this addr, so
452 Linux needs to be scooted a bit.
453 If you don't know what the above means, leave this setting alone.
454 This needs to match memory start address specified in Device Tree
456 config LINUX_RAM_BASE
457 hex "RAM base address"
458 default LINUX_LINK_BASE
460 By default Linux is linked at base of RAM. However in some special
461 cases (such as HSDK), Linux can't be linked at start of DDR, hence
465 bool "High Memory Support"
466 select HAVE_ARCH_PFN_VALID
469 With ARC 2G:2G address split, only upper 2G is directly addressable by
470 kernel. Enable this to potentially allow access to rest of 2G and PAE
474 bool "Support for the 40-bit Physical Address Extension"
477 select PHYS_ADDR_T_64BIT
479 Enable access to physical memory beyond 4G, only supported on
480 ARC cores with 40 bit Physical Addressing support
482 config ARC_KVADDR_SIZE
483 int "Kernel Virtual Address Space size (MB)"
487 The kernel address space is carved out of 256MB of translated address
488 space for catering to vmalloc, modules, pkmap, fixmap. This however may
489 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
490 this to be stretched to 512 MB (by extending into the reserved
493 config ARC_CURR_IN_REG
494 bool "cache current task pointer in gp"
497 This reserves gp register to point to Current Task in
498 kernel mode eliding memory access for each access
501 config ARC_EMUL_UNALIGNED
502 bool "Emulate unaligned memory access (userspace only)"
503 select SYSCTL_ARCH_UNALIGN_NO_WARN
504 select SYSCTL_ARCH_UNALIGN_ALLOW
505 depends on ISA_ARCOMPACT
507 This enables misaligned 16 & 32 bit memory access from user space.
508 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
509 potential bugs in code
512 int "Timer Frequency"
515 config ARC_METAWARE_HLINK
516 bool "Support for Metaware debugger assisted Host access"
518 This options allows a Linux userland apps to directly access
519 host file system (open/creat/read/write etc) with help from
520 Metaware Debugger. This can come in handy for Linux-host communication
521 when there is no real usable peripheral such as EMAC.
529 config ARC_DW2_UNWIND
530 bool "Enable DWARF specific kernel stack unwind"
534 Compiles the kernel with DWARF unwind information and can be used
535 to get stack backtraces.
537 If you say Y here the resulting kernel image will be slightly larger
538 but not slower, and it will give very useful debugging information.
539 If you don't debug the kernel, you can say N, but we may not be able
540 to solve problems without frame unwind information
542 config ARC_DBG_JUMP_LABEL
543 bool "Paranoid checks in Static Keys (jump labels) code"
544 depends on JUMP_LABEL
545 default y if STATIC_KEYS_SELFTEST
547 Enable paranoid checks and self-test of both ARC-specific and generic
548 part of static keys (jump labels) related code.
551 config ARC_BUILTIN_DTB_NAME
552 string "Built in DTB"
554 Set the name of the DTB to embed in the vmlinux binary
555 Leaving it blank selects the minimal "skeleton" dtb
557 endmenu # "ARC Architecture Configuration"
559 config ARCH_FORCE_MAX_ORDER
560 int "Maximum zone order"
561 default "11" if ARC_HUGEPAGE_16M
564 source "kernel/power/Kconfig"