2 * arch/alpha/kernel/traps.c
4 * (C) Copyright 1994 Linus Torvalds
8 * This file initializes the trap entry points
11 #include <linux/jiffies.h>
13 #include <linux/sched.h>
14 #include <linux/tty.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/kallsyms.h>
18 #include <linux/ratelimit.h>
20 #include <asm/gentrap.h>
21 #include <asm/uaccess.h>
22 #include <asm/unaligned.h>
23 #include <asm/sysinfo.h>
24 #include <asm/hwrpb.h>
25 #include <asm/mmu_context.h>
26 #include <asm/special_insns.h>
30 /* Work-around for some SRMs which mishandle opDEC faults. */
37 __asm__ __volatile__ (
38 /* Load the address of... */
40 /* A stub instruction fault handler. Just add 4 to the
46 /* Install the instruction fault handler. */
48 " call_pal %[wrent]\n"
49 /* With that in place, the fault from the round-to-minf fp
50 insn will arrive either at the "lda 4" insn (bad) or one
51 past that (good). This places the correct fixup in %0. */
53 " cvttq/svm $f31,$f31\n"
55 : [fix] "=r" (opDEC_fix)
56 : [rti] "n" (PAL_rti), [wrent] "n" (PAL_wrent)
57 : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25");
60 printk("opDEC fixup enabled.\n");
64 dik_show_regs(struct pt_regs *regs, unsigned long *r9_15)
66 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n",
67 regs->pc, regs->r26, regs->ps, print_tainted());
68 printk("pc is at %pSR\n", (void *)regs->pc);
69 printk("ra is at %pSR\n", (void *)regs->r26);
70 printk("v0 = %016lx t0 = %016lx t1 = %016lx\n",
71 regs->r0, regs->r1, regs->r2);
72 printk("t2 = %016lx t3 = %016lx t4 = %016lx\n",
73 regs->r3, regs->r4, regs->r5);
74 printk("t5 = %016lx t6 = %016lx t7 = %016lx\n",
75 regs->r6, regs->r7, regs->r8);
78 printk("s0 = %016lx s1 = %016lx s2 = %016lx\n",
79 r9_15[9], r9_15[10], r9_15[11]);
80 printk("s3 = %016lx s4 = %016lx s5 = %016lx\n",
81 r9_15[12], r9_15[13], r9_15[14]);
82 printk("s6 = %016lx\n", r9_15[15]);
85 printk("a0 = %016lx a1 = %016lx a2 = %016lx\n",
86 regs->r16, regs->r17, regs->r18);
87 printk("a3 = %016lx a4 = %016lx a5 = %016lx\n",
88 regs->r19, regs->r20, regs->r21);
89 printk("t8 = %016lx t9 = %016lx t10= %016lx\n",
90 regs->r22, regs->r23, regs->r24);
91 printk("t11= %016lx pv = %016lx at = %016lx\n",
92 regs->r25, regs->r27, regs->r28);
93 printk("gp = %016lx sp = %p\n", regs->gp, regs+1);
100 static char * ireg_name[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
101 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6",
102 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
103 "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"};
107 dik_show_code(unsigned int *pc)
112 for (i = -6; i < 2; i++) {
114 if (__get_user(insn, (unsigned int __user *)pc + i))
116 printk("%c%08x%c", i ? ' ' : '<', insn, i ? ' ' : '>');
122 dik_show_trace(unsigned long *sp)
126 while (0x1ff8 & (unsigned long) sp) {
127 extern char _stext[], _etext[];
128 unsigned long tmp = *sp;
130 if (tmp < (unsigned long) &_stext)
132 if (tmp >= (unsigned long) &_etext)
134 printk("[<%lx>] %pSR\n", tmp, (void *)tmp);
143 static int kstack_depth_to_print = 24;
145 void show_stack(struct task_struct *task, unsigned long *sp)
147 unsigned long *stack;
151 * debugging aid: "show_stack(NULL);" prints the
152 * back trace for this cpu.
155 sp=(unsigned long*)&sp;
158 for(i=0; i < kstack_depth_to_print; i++) {
159 if (((long) stack & (THREAD_SIZE-1)) == 0)
168 pr_cont("%016lx", *stack++);
175 die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15)
180 printk("CPU %d ", hard_smp_processor_id());
182 printk("%s(%d): %s %ld\n", current->comm, task_pid_nr(current), str, err);
183 dik_show_regs(regs, r9_15);
184 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
185 dik_show_trace((unsigned long *)(regs+1));
186 dik_show_code((unsigned int *)regs->pc);
188 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
189 printk("die_if_kernel recursion detected.\n");
196 #ifndef CONFIG_MATHEMU
197 static long dummy_emul(void) { return 0; }
198 long (*alpha_fp_emul_imprecise)(struct pt_regs *regs, unsigned long writemask)
199 = (void *)dummy_emul;
200 long (*alpha_fp_emul) (unsigned long pc)
201 = (void *)dummy_emul;
203 long alpha_fp_emul_imprecise(struct pt_regs *regs, unsigned long writemask);
204 long alpha_fp_emul (unsigned long pc);
208 do_entArith(unsigned long summary, unsigned long write_mask,
209 struct pt_regs *regs)
211 long si_code = FPE_FLTINV;
215 /* Software-completion summary bit is set, so try to
216 emulate the instruction. If the processor supports
217 precise exceptions, we don't have to search. */
218 if (!amask(AMASK_PRECISE_TRAP))
219 si_code = alpha_fp_emul(regs->pc - 4);
221 si_code = alpha_fp_emul_imprecise(regs, write_mask);
225 die_if_kernel("Arithmetic fault", regs, 0, NULL);
227 info.si_signo = SIGFPE;
229 info.si_code = si_code;
230 info.si_addr = (void __user *) regs->pc;
231 send_sig_info(SIGFPE, &info, current);
235 do_entIF(unsigned long type, struct pt_regs *regs)
240 if ((regs->ps & ~IPL_MAX) == 0) {
242 const unsigned int *data
243 = (const unsigned int *) regs->pc;
244 printk("Kernel bug at %s:%d\n",
245 (const char *)(data[1] | (long)data[2] << 32),
248 #ifdef CONFIG_ALPHA_WTINT
250 /* If CALL_PAL WTINT is totally unsupported by the
251 PALcode, e.g. MILO, "emulate" it by overwriting
254 = (unsigned int *) regs->pc - 1;
255 if (*pinsn == PAL_wtint) {
256 *pinsn = 0x47e01400; /* mov 0,$0 */
262 #endif /* ALPHA_WTINT */
263 die_if_kernel((type == 1 ? "Kernel Bug" : "Instruction fault"),
268 case 0: /* breakpoint */
269 info.si_signo = SIGTRAP;
271 info.si_code = TRAP_BRKPT;
273 info.si_addr = (void __user *) regs->pc;
275 if (ptrace_cancel_bpt(current)) {
276 regs->pc -= 4; /* make pc point to former bpt */
279 send_sig_info(SIGTRAP, &info, current);
282 case 1: /* bugcheck */
283 info.si_signo = SIGTRAP;
285 info.si_code = __SI_FAULT;
286 info.si_addr = (void __user *) regs->pc;
288 send_sig_info(SIGTRAP, &info, current);
291 case 2: /* gentrap */
292 info.si_addr = (void __user *) regs->pc;
293 info.si_trapno = regs->r16;
294 switch ((long) regs->r16) {
351 info.si_signo = signo;
354 info.si_addr = (void __user *) regs->pc;
355 send_sig_info(signo, &info, current);
359 if (implver() == IMPLVER_EV4) {
362 /* The some versions of SRM do not handle
363 the opDEC properly - they return the PC of the
364 opDEC fault, not the instruction after as the
365 Alpha architecture requires. Here we fix it up.
366 We do this by intentionally causing an opDEC
367 fault during the boot sequence and testing if
368 we get the correct PC. If not, we set a flag
369 to correct it every time through. */
370 regs->pc += opDEC_fix;
372 /* EV4 does not implement anything except normal
373 rounding. Everything else will come here as
374 an illegal instruction. Emulate them. */
375 si_code = alpha_fp_emul(regs->pc - 4);
379 info.si_signo = SIGFPE;
381 info.si_code = si_code;
382 info.si_addr = (void __user *) regs->pc;
383 send_sig_info(SIGFPE, &info, current);
389 case 3: /* FEN fault */
390 /* Irritating users can call PAL_clrfen to disable the
391 FPU for the process. The kernel will then trap in
392 do_switch_stack and undo_switch_stack when we try
393 to save and restore the FP registers.
395 Given that GCC by default generates code that uses the
396 FP registers, PAL_clrfen is not useful except for DoS
397 attacks. So turn the bleeding FPU back on and be done
399 current_thread_info()->pcb.flags |= 1;
400 __reload_thread(¤t_thread_info()->pcb);
404 default: /* unexpected instruction-fault type */
408 info.si_signo = SIGILL;
410 info.si_code = ILL_ILLOPC;
411 info.si_addr = (void __user *) regs->pc;
412 send_sig_info(SIGILL, &info, current);
415 /* There is an ifdef in the PALcode in MILO that enables a
416 "kernel debugging entry point" as an unprivileged call_pal.
418 We don't want to have anything to do with it, but unfortunately
419 several versions of MILO included in distributions have it enabled,
420 and if we don't put something on the entry point we'll oops. */
423 do_entDbg(struct pt_regs *regs)
427 die_if_kernel("Instruction fault", regs, 0, NULL);
429 info.si_signo = SIGILL;
431 info.si_code = ILL_ILLOPC;
432 info.si_addr = (void __user *) regs->pc;
433 force_sig_info(SIGILL, &info, current);
438 * entUna has a different register layout to be reasonably simple. It
439 * needs access to all the integer registers (the kernel doesn't use
440 * fp-regs), and it needs to have them in order for simpler access.
442 * Due to the non-standard register layout (and because we don't want
443 * to handle floating-point regs), user-mode unaligned accesses are
444 * handled separately by do_entUnaUser below.
446 * Oh, btw, we don't handle the "gp" register correctly, but if we fault
447 * on a gp-register unaligned load/store, something is _very_ wrong
448 * in the kernel anyway..
451 unsigned long regs[32];
452 unsigned long ps, pc, gp, a0, a1, a2;
455 struct unaligned_stat {
456 unsigned long count, va, pc;
460 /* Macro for exception fixup code to access integer registers. */
461 #define una_reg(r) (_regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
465 do_entUna(void * va, unsigned long opcode, unsigned long reg,
466 struct allregs *regs)
468 long error, tmp1, tmp2, tmp3, tmp4;
469 unsigned long pc = regs->pc - 4;
470 unsigned long *_regs = regs->regs;
471 const struct exception_table_entry *fixup;
473 unaligned[0].count++;
474 unaligned[0].va = (unsigned long) va;
475 unaligned[0].pc = pc;
477 /* We don't want to use the generic get/put unaligned macros as
478 we want to trap exceptions. Only if we actually get an
479 exception will we decide whether we should have caught it. */
482 case 0x0c: /* ldwu */
483 __asm__ __volatile__(
484 "1: ldq_u %1,0(%3)\n"
485 "2: ldq_u %2,1(%3)\n"
489 ".section __ex_table,\"a\"\n"
491 " lda %1,3b-1b(%0)\n"
493 " lda %2,3b-2b(%0)\n"
495 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
499 una_reg(reg) = tmp1|tmp2;
503 __asm__ __volatile__(
504 "1: ldq_u %1,0(%3)\n"
505 "2: ldq_u %2,3(%3)\n"
509 ".section __ex_table,\"a\"\n"
511 " lda %1,3b-1b(%0)\n"
513 " lda %2,3b-2b(%0)\n"
515 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
519 una_reg(reg) = (int)(tmp1|tmp2);
523 __asm__ __volatile__(
524 "1: ldq_u %1,0(%3)\n"
525 "2: ldq_u %2,7(%3)\n"
529 ".section __ex_table,\"a\"\n"
531 " lda %1,3b-1b(%0)\n"
533 " lda %2,3b-2b(%0)\n"
535 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
539 una_reg(reg) = tmp1|tmp2;
542 /* Note that the store sequences do not indicate that they change
543 memory because it _should_ be affecting nothing in this context.
544 (Otherwise we have other, much larger, problems.) */
546 __asm__ __volatile__(
547 "1: ldq_u %2,1(%5)\n"
548 "2: ldq_u %1,0(%5)\n"
555 "3: stq_u %2,1(%5)\n"
556 "4: stq_u %1,0(%5)\n"
558 ".section __ex_table,\"a\"\n"
560 " lda %2,5b-1b(%0)\n"
562 " lda %1,5b-2b(%0)\n"
564 " lda $31,5b-3b(%0)\n"
566 " lda $31,5b-4b(%0)\n"
568 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
569 "=&r"(tmp3), "=&r"(tmp4)
570 : "r"(va), "r"(una_reg(reg)), "0"(0));
576 __asm__ __volatile__(
577 "1: ldq_u %2,3(%5)\n"
578 "2: ldq_u %1,0(%5)\n"
585 "3: stq_u %2,3(%5)\n"
586 "4: stq_u %1,0(%5)\n"
588 ".section __ex_table,\"a\"\n"
590 " lda %2,5b-1b(%0)\n"
592 " lda %1,5b-2b(%0)\n"
594 " lda $31,5b-3b(%0)\n"
596 " lda $31,5b-4b(%0)\n"
598 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
599 "=&r"(tmp3), "=&r"(tmp4)
600 : "r"(va), "r"(una_reg(reg)), "0"(0));
606 __asm__ __volatile__(
607 "1: ldq_u %2,7(%5)\n"
608 "2: ldq_u %1,0(%5)\n"
615 "3: stq_u %2,7(%5)\n"
616 "4: stq_u %1,0(%5)\n"
618 ".section __ex_table,\"a\"\n\t"
620 " lda %2,5b-1b(%0)\n"
622 " lda %1,5b-2b(%0)\n"
624 " lda $31,5b-3b(%0)\n"
626 " lda $31,5b-4b(%0)\n"
628 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
629 "=&r"(tmp3), "=&r"(tmp4)
630 : "r"(va), "r"(una_reg(reg)), "0"(0));
636 printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n",
637 pc, va, opcode, reg);
641 /* Ok, we caught the exception, but we don't want it. Is there
642 someone to pass it along to? */
643 if ((fixup = search_exception_tables(pc)) != 0) {
645 newpc = fixup_exception(una_reg, fixup, pc);
647 printk("Forwarding unaligned exception at %lx (%lx)\n",
655 * Yikes! No one to forward the exception to.
656 * Since the registers are in a weird format, dump them ourselves.
659 printk("%s(%d): unhandled unaligned exception\n",
660 current->comm, task_pid_nr(current));
662 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx\n",
663 pc, una_reg(26), regs->ps);
664 printk("r0 = %016lx r1 = %016lx r2 = %016lx\n",
665 una_reg(0), una_reg(1), una_reg(2));
666 printk("r3 = %016lx r4 = %016lx r5 = %016lx\n",
667 una_reg(3), una_reg(4), una_reg(5));
668 printk("r6 = %016lx r7 = %016lx r8 = %016lx\n",
669 una_reg(6), una_reg(7), una_reg(8));
670 printk("r9 = %016lx r10= %016lx r11= %016lx\n",
671 una_reg(9), una_reg(10), una_reg(11));
672 printk("r12= %016lx r13= %016lx r14= %016lx\n",
673 una_reg(12), una_reg(13), una_reg(14));
674 printk("r15= %016lx\n", una_reg(15));
675 printk("r16= %016lx r17= %016lx r18= %016lx\n",
676 una_reg(16), una_reg(17), una_reg(18));
677 printk("r19= %016lx r20= %016lx r21= %016lx\n",
678 una_reg(19), una_reg(20), una_reg(21));
679 printk("r22= %016lx r23= %016lx r24= %016lx\n",
680 una_reg(22), una_reg(23), una_reg(24));
681 printk("r25= %016lx r27= %016lx r28= %016lx\n",
682 una_reg(25), una_reg(27), una_reg(28));
683 printk("gp = %016lx sp = %p\n", regs->gp, regs+1);
685 dik_show_code((unsigned int *)pc);
686 dik_show_trace((unsigned long *)(regs+1));
688 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
689 printk("die_if_kernel recursion detected.\n");
697 * Convert an s-floating point value in memory format to the
698 * corresponding value in register format. The exponent
699 * needs to be remapped to preserve non-finite values
700 * (infinities, not-a-numbers, denormals).
702 static inline unsigned long
703 s_mem_to_reg (unsigned long s_mem)
705 unsigned long frac = (s_mem >> 0) & 0x7fffff;
706 unsigned long sign = (s_mem >> 31) & 0x1;
707 unsigned long exp_msb = (s_mem >> 30) & 0x1;
708 unsigned long exp_low = (s_mem >> 23) & 0x7f;
711 exp = (exp_msb << 10) | exp_low; /* common case */
713 if (exp_low == 0x7f) {
717 if (exp_low == 0x00) {
723 return (sign << 63) | (exp << 52) | (frac << 29);
727 * Convert an s-floating point value in register format to the
728 * corresponding value in memory format.
730 static inline unsigned long
731 s_reg_to_mem (unsigned long s_reg)
733 return ((s_reg >> 62) << 30) | ((s_reg << 5) >> 34);
737 * Handle user-level unaligned fault. Handling user-level unaligned
738 * faults is *extremely* slow and produces nasty messages. A user
739 * program *should* fix unaligned faults ASAP.
741 * Notice that we have (almost) the regular kernel stack layout here,
742 * so finding the appropriate registers is a little more difficult
743 * than in the kernel case.
745 * Finally, we handle regular integer load/stores only. In
746 * particular, load-linked/store-conditionally and floating point
747 * load/stores are not supported. The former make no sense with
748 * unaligned faults (they are guaranteed to fail) and I don't think
749 * the latter will occur in any decent program.
751 * Sigh. We *do* have to handle some FP operations, because GCC will
752 * uses them as temporary storage for integer memory to memory copies.
753 * However, we need to deal with stt/ldt and sts/lds only.
756 #define OP_INT_MASK ( 1L << 0x28 | 1L << 0x2c /* ldl stl */ \
757 | 1L << 0x29 | 1L << 0x2d /* ldq stq */ \
758 | 1L << 0x0c | 1L << 0x0d /* ldwu stw */ \
759 | 1L << 0x0a | 1L << 0x0e ) /* ldbu stb */
761 #define OP_WRITE_MASK ( 1L << 0x26 | 1L << 0x27 /* sts stt */ \
762 | 1L << 0x2c | 1L << 0x2d /* stl stq */ \
763 | 1L << 0x0d | 1L << 0x0e ) /* stw stb */
765 #define R(x) ((size_t) &((struct pt_regs *)0)->x)
767 static int unauser_reg_offsets[32] = {
768 R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), R(r8),
769 /* r9 ... r15 are stored in front of regs. */
770 -56, -48, -40, -32, -24, -16, -8,
771 R(r16), R(r17), R(r18),
772 R(r19), R(r20), R(r21), R(r22), R(r23), R(r24), R(r25), R(r26),
773 R(r27), R(r28), R(gp),
780 do_entUnaUser(void __user * va, unsigned long opcode,
781 unsigned long reg, struct pt_regs *regs)
783 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
785 unsigned long tmp1, tmp2, tmp3, tmp4;
786 unsigned long fake_reg, *reg_addr = &fake_reg;
790 /* Check the UAC bits to decide what the user wants us to do
791 with the unaliged access. */
793 if (!(current_thread_info()->status & TS_UAC_NOPRINT)) {
794 if (__ratelimit(&ratelimit)) {
795 printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n",
796 current->comm, task_pid_nr(current),
797 regs->pc - 4, va, opcode, reg);
800 if ((current_thread_info()->status & TS_UAC_SIGBUS))
802 /* Not sure why you'd want to use this, but... */
803 if ((current_thread_info()->status & TS_UAC_NOFIX))
806 /* Don't bother reading ds in the access check since we already
807 know that this came from the user. Also rely on the fact that
808 the page at TASK_SIZE is unmapped and so can't be touched anyway. */
809 if (!__access_ok((unsigned long)va, 0, USER_DS))
812 ++unaligned[1].count;
813 unaligned[1].va = (unsigned long)va;
814 unaligned[1].pc = regs->pc - 4;
816 if ((1L << opcode) & OP_INT_MASK) {
817 /* it's an integer load/store */
819 reg_addr = (unsigned long *)
820 ((char *)regs + unauser_reg_offsets[reg]);
821 } else if (reg == 30) {
822 /* usp in PAL regs */
825 /* zero "register" */
830 /* We don't want to use the generic get/put unaligned macros as
831 we want to trap exceptions. Only if we actually get an
832 exception will we decide whether we should have caught it. */
835 case 0x0c: /* ldwu */
836 __asm__ __volatile__(
837 "1: ldq_u %1,0(%3)\n"
838 "2: ldq_u %2,1(%3)\n"
842 ".section __ex_table,\"a\"\n"
844 " lda %1,3b-1b(%0)\n"
846 " lda %2,3b-2b(%0)\n"
848 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
852 *reg_addr = tmp1|tmp2;
856 __asm__ __volatile__(
857 "1: ldq_u %1,0(%3)\n"
858 "2: ldq_u %2,3(%3)\n"
862 ".section __ex_table,\"a\"\n"
864 " lda %1,3b-1b(%0)\n"
866 " lda %2,3b-2b(%0)\n"
868 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
872 alpha_write_fp_reg(reg, s_mem_to_reg((int)(tmp1|tmp2)));
876 __asm__ __volatile__(
877 "1: ldq_u %1,0(%3)\n"
878 "2: ldq_u %2,7(%3)\n"
882 ".section __ex_table,\"a\"\n"
884 " lda %1,3b-1b(%0)\n"
886 " lda %2,3b-2b(%0)\n"
888 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
892 alpha_write_fp_reg(reg, tmp1|tmp2);
896 __asm__ __volatile__(
897 "1: ldq_u %1,0(%3)\n"
898 "2: ldq_u %2,3(%3)\n"
902 ".section __ex_table,\"a\"\n"
904 " lda %1,3b-1b(%0)\n"
906 " lda %2,3b-2b(%0)\n"
908 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
912 *reg_addr = (int)(tmp1|tmp2);
916 __asm__ __volatile__(
917 "1: ldq_u %1,0(%3)\n"
918 "2: ldq_u %2,7(%3)\n"
922 ".section __ex_table,\"a\"\n"
924 " lda %1,3b-1b(%0)\n"
926 " lda %2,3b-2b(%0)\n"
928 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
932 *reg_addr = tmp1|tmp2;
935 /* Note that the store sequences do not indicate that they change
936 memory because it _should_ be affecting nothing in this context.
937 (Otherwise we have other, much larger, problems.) */
939 __asm__ __volatile__(
940 "1: ldq_u %2,1(%5)\n"
941 "2: ldq_u %1,0(%5)\n"
948 "3: stq_u %2,1(%5)\n"
949 "4: stq_u %1,0(%5)\n"
951 ".section __ex_table,\"a\"\n"
953 " lda %2,5b-1b(%0)\n"
955 " lda %1,5b-2b(%0)\n"
957 " lda $31,5b-3b(%0)\n"
959 " lda $31,5b-4b(%0)\n"
961 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
962 "=&r"(tmp3), "=&r"(tmp4)
963 : "r"(va), "r"(*reg_addr), "0"(0));
969 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
973 __asm__ __volatile__(
974 "1: ldq_u %2,3(%5)\n"
975 "2: ldq_u %1,0(%5)\n"
982 "3: stq_u %2,3(%5)\n"
983 "4: stq_u %1,0(%5)\n"
985 ".section __ex_table,\"a\"\n"
987 " lda %2,5b-1b(%0)\n"
989 " lda %1,5b-2b(%0)\n"
991 " lda $31,5b-3b(%0)\n"
993 " lda $31,5b-4b(%0)\n"
995 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
996 "=&r"(tmp3), "=&r"(tmp4)
997 : "r"(va), "r"(*reg_addr), "0"(0));
1002 case 0x27: /* stt */
1003 fake_reg = alpha_read_fp_reg(reg);
1006 case 0x2d: /* stq */
1007 __asm__ __volatile__(
1008 "1: ldq_u %2,7(%5)\n"
1009 "2: ldq_u %1,0(%5)\n"
1016 "3: stq_u %2,7(%5)\n"
1017 "4: stq_u %1,0(%5)\n"
1019 ".section __ex_table,\"a\"\n\t"
1021 " lda %2,5b-1b(%0)\n"
1023 " lda %1,5b-2b(%0)\n"
1025 " lda $31,5b-3b(%0)\n"
1027 " lda $31,5b-4b(%0)\n"
1029 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
1030 "=&r"(tmp3), "=&r"(tmp4)
1031 : "r"(va), "r"(*reg_addr), "0"(0));
1037 /* What instruction were you trying to use, exactly? */
1041 /* Only integer loads should get here; everyone else returns early. */
1047 regs->pc -= 4; /* make pc point to faulting insn */
1048 info.si_signo = SIGSEGV;
1051 /* We need to replicate some of the logic in mm/fault.c,
1052 since we don't have access to the fault code in the
1053 exception handling return path. */
1054 if (!__access_ok((unsigned long)va, 0, USER_DS))
1055 info.si_code = SEGV_ACCERR;
1057 struct mm_struct *mm = current->mm;
1058 down_read(&mm->mmap_sem);
1059 if (find_vma(mm, (unsigned long)va))
1060 info.si_code = SEGV_ACCERR;
1062 info.si_code = SEGV_MAPERR;
1063 up_read(&mm->mmap_sem);
1066 send_sig_info(SIGSEGV, &info, current);
1071 info.si_signo = SIGBUS;
1073 info.si_code = BUS_ADRALN;
1075 send_sig_info(SIGBUS, &info, current);
1082 /* Tell PAL-code what global pointer we want in the kernel. */
1083 register unsigned long gptr __asm__("$29");
1086 /* Hack for Multia (UDB) and JENSEN: some of their SRMs have
1087 a bug in the handling of the opDEC fault. Fix it up if so. */
1088 if (implver() == IMPLVER_EV4)