1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_ALPHA_FPU_H
3 #define __ASM_ALPHA_FPU_H
5 #include <asm/special_insns.h>
6 #include <uapi/asm/fpu.h>
8 /* The following two functions don't need trapb/excb instructions
9 around the mf_fpcr/mt_fpcr instructions because (a) the kernel
10 never generates arithmetic faults and (b) call_pal instructions
11 are implied trap barriers. */
13 static inline unsigned long
16 unsigned long tmp, ret;
19 if (current_thread_info()->status & TS_SAVED_FP) {
20 ret = current_thread_info()->fp[31];
22 #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
23 __asm__ __volatile__ (
28 : "=r"(tmp), "=r"(ret));
30 __asm__ __volatile__ (
35 : "=m"(tmp), "=m"(ret));
44 wrfpcr(unsigned long val)
49 if (current_thread_info()->status & TS_SAVED_FP) {
50 current_thread_info()->status |= TS_RESTORE_FP;
51 current_thread_info()->fp[31] = val;
53 #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
54 __asm__ __volatile__ (
59 : "=&r"(tmp) : "r"(val));
61 __asm__ __volatile__ (
66 : "=m"(tmp) : "m"(val));
72 static inline unsigned long
73 swcr_update_status(unsigned long swcr, unsigned long fpcr)
75 /* EV6 implements most of the bits in hardware. Collect
76 the acrued exception bits from the real fpcr. */
77 if (implver() == IMPLVER_EV6) {
78 swcr &= ~IEEE_STATUS_MASK;
79 swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
84 extern unsigned long alpha_read_fp_reg (unsigned long reg);
85 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
86 extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
87 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
89 #endif /* __ASM_ALPHA_FPU_H */