2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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14 * documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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36 #ifndef _ATH_AR5416_DESC_H_
37 #define _ATH_AR5416_DESC_H_
39 #define ds_ctl8 u.tx.ctl8
40 #define ds_ctl9 u.tx.ctl9
41 #define ds_ctl10 u.tx.ctl10
42 #define ds_ctl11 u.tx.ctl11
44 struct ar5416_desc_20 {
45 a_uint32_t ds_link; /* link pointer */
46 a_uint32_t ds_data; /* data buffer pointer */
47 a_uint32_t ds_ctl0; /* DMA control 0 */
48 a_uint32_t ds_ctl1; /* DMA control 1 */
72 struct { /* rx desc has 2 control words + 9 status words */
86 #define AR5416DESC_20(_ds) ((struct ar5416_desc_20 *)(_ds))
87 #define AR5416DESC_CONST_20(_ds) ((const struct ar5416_desc_20 *)(_ds))
89 #define ds_ctl2 u.tx.ctl2
90 #define ds_ctl3 u.tx.ctl3
91 #define ds_ctl4 u.tx.ctl4
92 #define ds_ctl5 u.tx.ctl5
93 #define ds_ctl6 u.tx.ctl6
94 #define ds_ctl7 u.tx.ctl7
96 #define ds_txstatus0 u.tx.status0
97 #define ds_txstatus1 u.tx.status1
98 #define ds_txstatus2 u.tx.status2
99 #define ds_txstatus3 u.tx.status3
100 #define ds_txstatus4 u.tx.status4
101 #define ds_txstatus5 u.tx.status5
102 #define ds_txstatus6 u.tx.status6
103 #define ds_txstatus7 u.tx.status7
104 #define ds_txstatus8 u.tx.status8
105 #define ds_txstatus9 u.tx.status9
107 #define ds_rxstatus0 u.rx.status0
108 #define ds_rxstatus1 u.rx.status1
109 #define ds_rxstatus2 u.rx.status2
110 #define ds_rxstatus3 u.rx.status3
111 #define ds_rxstatus4 u.rx.status4
112 #define ds_rxstatus5 u.rx.status5
113 #define ds_rxstatus6 u.rx.status6
114 #define ds_rxstatus7 u.rx.status7
115 #define ds_rxstatus8 u.rx.status8
122 #define AR_FrameLen 0x00000fff
123 #define AR_VirtMoreFrag 0x00001000
124 #define AR_TxCtlRsvd00 0x0000e000
126 #define AR_XmitPower 0x003f0000
127 #define AR_XmitPower_S 16
129 #define AR_RTSEnable 0x00400000
130 #define AR_VEOL 0x00800000
131 #define AR_ClrDestMask 0x01000000
132 #define AR_TxCtlRsvd01 0x1e000000
133 #define AR_TxIntrReq 0x20000000
134 #define AR_DestIdxValid 0x40000000
135 #define AR_CTSEnable 0x80000000
138 #define AR_BufLen 0x00000fff
139 #define AR_TxMore 0x00001000
140 #define AR_DestIdx 0x000fe000
141 #define AR_DestIdx_S 13
142 #define AR_FrameType 0x00f00000
143 #define AR_FrameType_S 20
144 #define AR_NoAck 0x01000000
145 #define AR_InsertTS 0x02000000
146 #define AR_CorruptFCS 0x04000000
147 #define AR_ExtOnly 0x08000000
148 #define AR_ExtAndCtl 0x10000000
149 #define AR_MoreAggr 0x20000000
150 #define AR_IsAggr 0x40000000
151 #define AR_MoreRifs 0x80000000
154 #define AR_BurstDur 0x00007fff
155 #define AR_BurstDur_S 0
156 #define AR_DurUpdateEn 0x00008000
157 #define AR_XmitDataTries0 0x000f0000
158 #define AR_XmitDataTries0_S 16
159 #define AR_XmitDataTries1 0x00f00000
160 #define AR_XmitDataTries1_S 20
161 #define AR_XmitDataTries2 0x0f000000
162 #define AR_XmitDataTries2_S 24
163 #define AR_XmitDataTries3 0xf0000000
164 #define AR_XmitDataTries3_S 28
167 #define AR_XmitRate0 0x000000ff
168 #define AR_XmitRate0_S 0
169 #define AR_XmitRate1 0x0000ff00
170 #define AR_XmitRate1_S 8
171 #define AR_XmitRate2 0x00ff0000
172 #define AR_XmitRate2_S 16
173 #define AR_XmitRate3 0xff000000
174 #define AR_XmitRate3_S 24
177 #define AR_PacketDur0 0x00007fff
178 #define AR_PacketDur0_S 0
179 #define AR_RTSCTSQual0 0x00008000
180 #define AR_PacketDur1 0x7fff0000
181 #define AR_PacketDur1_S 16
182 #define AR_RTSCTSQual1 0x80000000
185 #define AR_PacketDur2 0x00007fff
186 #define AR_PacketDur2_S 0
187 #define AR_RTSCTSQual2 0x00008000
188 #define AR_PacketDur3 0x7fff0000
189 #define AR_PacketDur3_S 16
190 #define AR_RTSCTSQual3 0x80000000
193 #define AR_AggrLen 0x0000ffff
194 #define AR_AggrLen_S 0
195 #define AR_TxCtlRsvd60 0x00030000
196 #define AR_PadDelim 0x03fc0000
197 #define AR_PadDelim_S 18
198 #define AR_EncrType 0x1c000000
199 #define AR_EncrType_S 26
200 #define AR_TxCtlRsvd61 0xf0000000
203 #define AR_2040_0 0x00000001
204 #define AR_GI0 0x00000002
205 #define AR_ChainSel0 0x0000001c
206 #define AR_ChainSel0_S 2
207 #define AR_2040_1 0x00000020
208 #define AR_GI1 0x00000040
209 #define AR_ChainSel1 0x00000380
210 #define AR_ChainSel1_S 7
211 #define AR_2040_2 0x00000400
212 #define AR_GI2 0x00000800
213 #define AR_ChainSel2 0x00007000
214 #define AR_ChainSel2_S 12
215 #define AR_2040_3 0x00008000
216 #define AR_GI3 0x00010000
217 #define AR_ChainSel3 0x000e0000
218 #define AR_ChainSel3_S 17
219 #define AR_RTSCTSRate 0x0ff00000
220 #define AR_RTSCTSRate_S 20
221 #define AR_TxCtlRsvd70 0xf0000000
222 #define AR_STBC0 0x10000000
223 #define AR_STBC1 0x20000000
224 #define AR_STBC2 0x40000000
225 #define AR_STBC3 0x80000000
229 #define AR_TxCtlRsvd80 0xffffffff
232 #define AR_TxCtlRsvd90 0x00ffffff
233 #define AR_XmitPower1 0x3f000000
234 #define AR_XmitPower1_S 24
235 #define AR_TxCtlRsvd91 0xc0000000
238 #define AR_TxCtlRsvd100 0x00ffffff
239 #define AR_XmitPower2 0x3f000000
240 #define AR_XmitPower2_S 24
241 #define AR_TxCtlRsvd101 0xc0000000
244 #define AR_TxCtlRsvd110 0x00ffffff
245 #define AR_XmitPower3 0x3f000000
246 #define AR_XmitPower3_S 24
247 #define AR_TxCtlRsvd111 0xc0000000
255 #define AR_TxRSSIAnt00 0x000000ff
256 #define AR_TxRSSIAnt00_S 0
257 #define AR_TxRSSIAnt01 0x0000ff00
258 #define AR_TxRSSIAnt01_S 8
259 #define AR_TxRSSIAnt02 0x00ff0000
260 #define AR_TxRSSIAnt02_S 16
261 #define AR_TxStatusRsvd00 0x3f000000
262 #define AR_TxBaStatus 0x40000000
263 #define AR_TxStatusRsvd01 0x80000000
266 #define AR_FrmXmitOK 0x00000001
267 #define AR_ExcessiveRetries 0x00000002
268 #define AR_FIFOUnderrun 0x00000004
269 #define AR_Filtered 0x00000008
270 #define AR_RTSFailCnt 0x000000f0
271 #define AR_RTSFailCnt_S 4
272 #define AR_DataFailCnt 0x00000f00
273 #define AR_DataFailCnt_S 8
274 #define AR_VirtRetryCnt 0x0000f000
275 #define AR_VirtRetryCnt_S 12
276 #define AR_TxDelimUnderrun 0x00010000
277 #define AR_TxDataUnderrun 0x00020000
278 #define AR_DescCfgErr 0x00040000
279 #define AR_TxTimerExpired 0x00080000
280 #define AR_TxStatusRsvd10 0xfff00000
283 #define AR_SendTimestamp ds_txstatus2
286 #define AR_BaBitmapLow ds_txstatus3
289 #define AR_BaBitmapHigh ds_txstatus4
292 #define AR_TxRSSIAnt10 0x000000ff
293 #define AR_TxRSSIAnt10_S 0
294 #define AR_TxRSSIAnt11 0x0000ff00
295 #define AR_TxRSSIAnt11_S 8
296 #define AR_TxRSSIAnt12 0x00ff0000
297 #define AR_TxRSSIAnt12_S 16
298 #define AR_TxRSSICombined 0xff000000
299 #define AR_TxRSSICombined_S 24
302 #define AR_TxEVM0 ds_txstatus5
305 #define AR_TxEVM1 ds_txstatus6
308 #define AR_TxEVM2 ds_txstatus7
311 #define AR_TxDone 0x00000001
312 #define AR_SeqNum 0x00001ffe
313 #define AR_SeqNum_S 1
314 #define AR_TxStatusRsvd80 0x0001e000
315 #define AR_TxOpExceeded 0x00020000
316 #define AR_TxStatusRsvd81 0x001c0000
317 #define AR_FinalTxIdx 0x00600000
318 #define AR_FinalTxIdx_S 21
319 #define AR_TxStatusRsvd82 0x01800000
320 #define AR_PowerMgmt 0x02000000
321 #define AR_TxStatusRsvd83 0xfc000000
328 #define AR_RxCTLRsvd00 0xffffffff
331 #define AR_BufLen 0x00000fff
332 #define AR_RxCtlRsvd00 0x00001000
333 #define AR_RxIntrReq 0x00002000
334 #define AR_RxCtlRsvd01 0xffffc000
341 #define AR_RxRSSIAnt00 0x000000ff
342 #define AR_RxRSSIAnt00_S 0
343 #define AR_RxRSSIAnt01 0x0000ff00
344 #define AR_RxRSSIAnt01_S 8
345 #define AR_RxRSSIAnt02 0x00ff0000
346 #define AR_RxRSSIAnt02_S 16
347 #define AR_RxRate 0xff000000
348 #define AR_RxRate_S 24
349 #define AR_RxStatusRsvd00 0xff000000
352 #define AR_DataLen 0x00000fff
353 #define AR_RxMore 0x00001000
354 #define AR_NumDelim 0x003fc000
355 #define AR_NumDelim_S 14
356 #define AR_RxStatusRsvd10 0xff800000
359 #define AR_RcvTimestamp ds_rxstatus2
362 #define AR_GI 0x00000001
363 #define AR_2040 0x00000002
364 #define AR_Parallel40 0x00000004
365 #define AR_Parallel40_S 2
366 #define AR_RxStatusRsvd30 0x000000f8
367 #define AR_RxAntenna 0xffffff00
368 #define AR_RxAntenna_S 8
371 #define AR_RxRSSIAnt10 0x000000ff
372 #define AR_RxRSSIAnt10_S 0
373 #define AR_RxRSSIAnt11 0x0000ff00
374 #define AR_RxRSSIAnt11_S 8
375 #define AR_RxRSSIAnt12 0x00ff0000
376 #define AR_RxRSSIAnt12_S 16
377 #define AR_RxRSSICombined 0xff000000
378 #define AR_RxRSSICombined_S 24
381 #define AR_RxEVM0 ds_rxstatus4
384 #define AR_RxEVM1 ds_rxstatus5
387 #define AR_RxEVM2 ds_rxstatus6
390 #define AR_RxDone 0x00000001
391 #define AR_RxFrameOK 0x00000002
392 #define AR_CRCErr 0x00000004
393 #define AR_DecryptCRCErr 0x00000008
394 #define AR_PHYErr 0x00000010
395 #define AR_MichaelErr 0x00000020
396 #define AR_PreDelimCRCErr 0x00000040
397 #define AR_RxStatusRsvd70 0x00000080
398 #define AR_RxKeyIdxValid 0x00000100
399 #define AR_KeyIdx 0x0000fe00
400 #define AR_KeyIdx_S 9
401 #define AR_PHYErrCode 0x0000ff00
402 #define AR_PHYErrCode_S 8
403 #define AR_RxMoreAggr 0x00010000
404 #define AR_RxAggr 0x00020000
405 #define AR_PostDelimCRCErr 0x00040000
406 #define AR_RxStatusRsvd71 0x3ff80000
407 #define AR_DecryptBusyErr 0x40000000
408 #define AR_KeyMiss 0x80000000
410 #define RXSTATUS_RATE(ah, ads) (MS(ads->ds_rxstatus0, AR_RxRate))
411 #define VALID_TX_RATES \
412 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)| \
413 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)| \
414 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
415 #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
417 #define set11nTries(_series, _index) \
418 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
420 #define set11nRate(_series, _index) \
421 (SM((_series)[_index].Rate, AR_XmitRate##_index))
423 #define set11nPktDurRTSCTS(_series, _index) \
424 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
425 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\
426 AR_RTSCTSQual##_index : 0))
428 #define set11nRateFlags(_series, _index) \
429 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
430 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
431 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \
432 |SM((_series)[_index].ChSel, AR_ChainSel##_index)
434 #define set11nTxPower(_index, _txpower) \
435 SM(_txpower, AR_XmitPower##_index)
437 extern HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *,
438 HAL_BOOL IncTrigLevel);
439 extern a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q);
440 extern HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp);
441 extern HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q);
442 extern a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q);
443 extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, a_uint32_t q);
444 extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah);
445 extern void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *);
446 extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *, a_uint32_t);
447 extern a_uint32_t ar5416GetGlobalTxTimeout(struct ath_hal *);
448 extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah);
449 extern a_uint32_t ar5416GetRxDP(struct ath_hal *ath);
450 extern void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp);
451 extern void ar5416EnableReceive(struct ath_hal *ah);
452 extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah);
453 extern void ar5416StartPcuReceive(struct ath_hal *ah);
454 extern void ar5416StopPcuReceive(struct ath_hal *ah);
455 extern void ar5416AbortPcuReceive(struct ath_hal *ah);
456 extern a_uint32_t ar5416GetRxFilter(struct ath_hal *ah);
457 extern void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits);
458 extern HAL_BOOL ar5416UpdateCTSForBursting_20(struct ath_hal *, struct ath_desc *,
459 struct ath_desc *,struct ath_desc *, struct ath_desc *,
460 a_uint32_t, a_uint32_t);
461 extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
462 a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower,
463 a_uint32_t txRate0, a_uint32_t txTries0,
464 a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
465 a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
466 a_uint32_t compicvLen, a_uint32_t compivLen, a_uint32_t comp);
467 extern HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
468 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
469 const struct ath_tx_desc *ds0);
470 extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *,HAL_KEY_TYPE);
471 extern HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *);
473 extern void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
474 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
475 a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags);
476 extern void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
477 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[],
478 a_uint32_t nseries, a_uint32_t flags);
479 extern void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds,
480 a_uint32_t aggrLen, a_uint32_t numDelims);
481 extern void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds,
482 a_uint32_t numDelims);
483 extern void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds);
484 extern void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds);
485 extern void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
486 a_uint32_t burstDuration);
487 extern void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
489 extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *,
490 struct ath_rx_desc *, a_uint32_t size, a_uint32_t flags);
491 extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah,
492 struct ath_rx_desc *, a_uint32_t,
494 struct ath_rx_status *);