2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_getInterrupts = ar5416GetInterrupts,
81 .ah_setInterrupts = ar5416SetInterrupts,
85 void ar5416Detach(struct ath_hal *ah)
87 HALASSERT(ah != AH_NULL);
92 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
93 a_uint32_t flags, HAL_STATUS *status)
95 struct ath_hal_5416 *ahp;
98 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
100 *status = HAL_ENOMEM;
103 ah = &ahp->ah_priv.h;
105 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
110 /* If its a Owl 2.0 chip then change the hal structure to
111 point to the Owl 2.0 ar5416_hal_20 structure */
113 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
114 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
115 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
116 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
117 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
118 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
119 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
120 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
121 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
122 ah->ah_updateCTSForBursting = NULL;
123 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
124 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
125 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
126 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
127 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
128 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
134 /**********************/
135 /* Interrupt Handling */
136 /**********************/
138 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
140 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
142 * Some platforms trigger our ISR before applying power to
143 * the card, so make sure.
145 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
148 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
152 HAL_BOOL fatal_int = AH_FALSE;
153 a_uint32_t sync_cause;
155 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
156 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
165 isr = OS_REG_READ(ah, AR_ISR_RAC);
166 if (isr == 0xffffffff) {
171 *masked = isr & HAL_INT_COMMON;
173 #ifdef AR5416_INT_MITIGATION
174 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
175 *masked |= HAL_INT_RX;
177 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
178 *masked |= HAL_INT_TX;
182 if (isr & AR_ISR_BCNMISC) {
185 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
187 if (s2_s & AR_ISR_S2_GTT) {
188 *masked |= HAL_INT_GTT;
191 if (s2_s & AR_ISR_S2_CST) {
192 *masked |= HAL_INT_CST;
196 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
197 *masked |= HAL_INT_RX;
198 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
199 struct ath_hal_5416 *ahp = AH5416(ah);
200 a_uint32_t s0_s, s1_s;
202 *masked |= HAL_INT_TX;
203 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
204 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
205 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
206 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
207 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
208 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
212 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
213 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
214 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
217 if (AH_TRUE == fatal_int) {
218 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
219 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
225 HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
227 return AH5416(ah)->ah_maskReg;
231 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
233 struct ath_hal_5416 *ahp = AH5416(ah);
234 a_uint32_t omask = ahp->ah_maskReg;
237 if (omask & HAL_INT_GLOBAL) {
238 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
239 (void) OS_REG_READ(ah, AR_IER);
242 mask = ints & HAL_INT_COMMON;
243 if (ints & HAL_INT_TX) {
244 #ifdef AR5416_INT_MITIGATION
245 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
248 mask |= AR_IMR_TXDESC;
250 mask |= AR_IMR_TXERR;
251 mask |= AR_IMR_TXEOL;
253 if (ints & HAL_INT_RX) {
254 mask |= AR_IMR_RXERR;
255 #ifdef AR5416_INT_MITIGATION
256 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
258 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
262 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
263 mask |= AR_IMR_BCNMISC;
266 OS_REG_WRITE(ah, AR_IMR, mask);
267 (void) OS_REG_READ(ah, AR_IMR);
268 ahp->ah_maskReg = ints;
270 /* Re-enable interrupts if they were enabled before. */
271 if (ints & HAL_INT_GLOBAL) {
272 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
273 /* See explanation above... */
274 (void) OS_REG_READ(ah, AR_IER);
277 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
278 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
279 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
288 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
292 tsf = OS_REG_READ(ah, AR_TSF_U32);
293 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
301 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
303 OS_REG_WRITE(ah, AR_RXDP, rxdp);
304 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
307 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
309 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
310 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
313 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
320 val = OS_REG_READ(ah, AR_MCAST_FIL1);
321 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
323 val = OS_REG_READ(ah, AR_MCAST_FIL0);
324 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
329 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
331 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
332 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
339 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
346 val = OS_REG_READ(ah, AR_MCAST_FIL1);
347 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
349 val = OS_REG_READ(ah, AR_MCAST_FIL0);
350 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
355 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
359 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
361 if (bits & HAL_RX_FILTER_PHYRADAR)
362 phybits |= AR_PHY_ERR_RADAR;
363 if (bits & HAL_RX_FILTER_PHYERR)
364 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
365 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
367 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
369 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
373 void ar5416EnableReceive(struct ath_hal *ah)
375 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
378 void ar5416StopPcuReceive(struct ath_hal *ah)
380 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
383 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
384 a_uint32_t size, a_uint32_t flags)
386 struct ar5416_desc *ads = AR5416DESC(ds);
388 HALASSERT((size &~ AR_BufLen) == 0);
390 ads->ds_ctl1 = size & AR_BufLen;
391 if (flags & HAL_RXDESC_INTREQ)
392 ads->ds_ctl1 |= AR_RxIntrReq;
394 /* this should be enough */
395 ads->ds_rxstatus8 &= ~AR_RxDone;
400 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
401 a_uint32_t pa, struct ath_desc *nds,
402 struct ath_rx_status *rx_stats)
404 struct ar5416_desc ads;
405 struct ar5416_desc *adsp = AR5416DESC(ds);
406 struct ar5416_desc *ands = AR5416DESC(nds);
408 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
409 return HAL_EINPROGRESS;
411 * Given the use of a self-linked tail be very sure that the hw is
412 * done with this descriptor; the hw may have done this descriptor
413 * once and picked it up again...make sure the hw has moved on.
415 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
416 && OS_REG_READ(ah, AR_RXDP) == pa)
417 return HAL_EINPROGRESS;
420 * Now we need to get the stats from the descriptor. Since desc are
421 * uncached, lets make a copy of the stats first. Note that, since we
422 * touch most of the rx stats, a memcpy would always be more efficient
424 * Next we fill in all values in a caller passed stack variable.
425 * This reduces the number of uncached accesses.
426 * Do this copy here, after the check so that when the checks fail, we
427 * dont end up copying the entire stats uselessly.
429 ads.u.rx = adsp->u.rx;
431 rx_stats->rs_status = 0;
432 rx_stats->rs_flags = 0;
434 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
435 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
437 /* XXX what about KeyCacheMiss? */
438 rx_stats->rs_rssi_combined =
439 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
440 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
441 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
442 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
443 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
444 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
445 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
446 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
447 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
449 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
450 /* NB: caller expected to do rate table mapping */
451 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
452 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
454 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
455 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
456 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
457 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
459 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
460 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
461 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
462 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
463 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
464 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
466 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
468 * These four bits should not be set together. The
469 * 5416 spec states a Michael error can only occur if
470 * DecryptCRCErr not set (and TKIP is used). Experience
471 * indicates however that you can also get Michael errors
472 * when a CRC error is detected, but these are specious.
473 * Consequently we filter them out here so we don't
474 * confuse and/or complicate drivers.
476 if (ads.ds_rxstatus8 & AR_CRCErr)
477 rx_stats->rs_status |= HAL_RXERR_CRC;
478 else if (ads.ds_rxstatus8 & AR_PHYErr) {
481 rx_stats->rs_status |= HAL_RXERR_PHY;
482 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
483 rx_stats->rs_phyerr = phyerr;
484 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
485 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
486 else if (ads.ds_rxstatus8 & AR_MichaelErr)
487 rx_stats->rs_status |= HAL_RXERR_MIC;
489 rx_stats->evm0=ads.AR_RxEVM0;
490 rx_stats->evm1=ads.AR_RxEVM1;
491 rx_stats->evm2=ads.AR_RxEVM2;
500 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
502 struct ath_hal_5416 *ahp = AH5416(ah);
503 a_uint32_t txcfg, curLevel, newLevel;
507 * Disable interrupts while futzing with the fifo level.
509 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
511 txcfg = OS_REG_READ(ah, AR_TXCFG);
512 curLevel = MS(txcfg, AR_FTRIG);
516 if (curLevel < MAX_TX_FIFO_THRESHOLD)
518 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
520 if (newLevel != curLevel)
521 OS_REG_WRITE(ah, AR_TXCFG,
522 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
524 /* re-enable chip interrupts */
525 ar5416SetInterrupts(ah, omask);
527 return (newLevel != curLevel);
530 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
532 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
533 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
536 * Make sure that TXE is deasserted before setting the TXDP. If TXE
537 * is still asserted, setting TXDP will have no effect.
539 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
541 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
546 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
548 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
549 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
551 /* Check to be sure we're not enabling a q that has its TXD bit set. */
552 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
554 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
559 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
563 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
564 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
566 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
569 * Pending frame count (PFC) can momentarily go to zero
570 * while TXE remains asserted. In other words a PFC of
571 * zero is not sufficient to say that the queue has stopped.
573 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
577 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
578 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
579 isrPrintf("RTSD on CAB queue\n");
580 /* Clear the ReadyTime shutdown status bits */
581 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
588 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
593 * set txd on all queues
595 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
600 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
601 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
602 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
605 * wait on all tx queues
607 for (q = 0; q < AR_NUM_QCU; q++) {
608 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
609 if (!ar5416NumTxPending(ah, q))
612 OS_DELAY(AR5416_ABORT_WAIT);
614 if (i == AR5416_ABORT_LOOPS) {
620 * clear tx abort bits
622 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
623 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
624 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
629 OS_REG_WRITE(ah, AR_Q_TXD, 0);
634 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
638 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
640 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
642 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
643 for (i = 1000; i != 0; i--) {
644 if (ar5416NumTxPending(ah, q) == 0)
646 OS_DELAY(100); /* XXX get actual value */
649 OS_REG_WRITE(ah, AR_Q_TXD, 0);
653 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
655 struct ar5416_desc *ads = AR5416DESC(ds);
656 ads->ds_ctl0 |= AR_TxIntrReq;
659 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
664 a_uint32_t txRate0, a_uint32_t txTries0,
668 a_uint32_t rtsctsRate,
669 a_uint32_t rtsctsDuration,
670 a_uint32_t compicvLen,
671 a_uint32_t compivLen,
674 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
676 struct ar5416_desc *ads = AR5416DESC(ds);
680 ads->ds_txstatus9 &= ~AR_TxDone;
682 HALASSERT(txTries0 != 0);
683 HALASSERT(isValidPktType(type));
684 HALASSERT(isValidTxRate(txRate0));
685 HALASSERT((flags & RTSCTS) != RTSCTS);
690 ads->ds_ctl0 = (pktLen & AR_FrameLen)
691 | (txPower << AR_XmitPower_S)
692 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
693 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
694 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
696 ads->ds_ctl1 = (type << AR_FrameType_S)
697 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
698 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
699 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
701 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
702 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
703 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
704 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
706 if (keyIx != HAL_TXKEYIX_INVALID) {
707 /* XXX validate key index */
708 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
709 ads->ds_ctl0 |= AR_DestIdxValid;
712 if (flags & RTSCTS) {
713 if (!isValidTxRate(rtsctsRate)) {
716 /* XXX validate rtsctsDuration */
717 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
718 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
719 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
720 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
727 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
728 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
729 const struct ath_tx_desc *ds0)
731 struct ar5416_desc *ads = AR5416DESC(ds);
733 HALASSERT((segLen &~ AR_BufLen) == 0);
737 * First descriptor, don't clobber xmit control data
738 * setup by ar5416SetupTxDesc.
740 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
741 } else if (lastSeg) {
743 * Last descriptor in a multi-descriptor frame,
744 * copy the multi-rate transmit parameters from
745 * the first frame for processing on completion.
748 ads->ds_ctl1 = segLen;
749 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
750 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
753 * Intermediate descriptor in a multi-descriptor frame.
756 ads->ds_ctl1 = segLen | AR_TxMore;
760 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
765 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
766 HAL_KEY_TYPE keyType)
768 struct ar5416_desc *ads = AR5416DESC(ds);
770 ads->ds_ctl6 = SM(keyType, AR_EncrType);
774 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
776 struct ar5416_desc *ads = AR5416DESC(gds);
777 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
779 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
780 return HAL_EINPROGRESS;
782 ads->ds_txstatus9 &= ~AR_TxDone;
784 /* Update software copies of the HW status */
785 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
786 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
787 ds->ds_txstat.ts_status = 0;
788 ds->ds_txstat.ts_flags = 0;
790 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
791 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
792 if (ads->ds_txstatus1 & AR_Filtered)
793 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
794 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
795 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
796 if (ads->ds_txstatus9 & AR_TxOpExceeded)
797 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
798 if (ads->ds_txstatus1 & AR_TxTimerExpired)
799 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
801 if (ads->ds_txstatus1 & AR_DescCfgErr)
802 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
803 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
804 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
805 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
807 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
808 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
809 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
811 if (ads->ds_txstatus0 & AR_TxBaStatus) {
812 ds->ds_txstat.ts_flags |= HAL_TX_BA;
813 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
814 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
818 * Extract the transmit rate used and mark the rate as
819 * ``alternate'' if it wasn't the series 0 rate.
821 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
822 ds->ds_txstat.ts_rssi_combined =
823 MS(ads->ds_txstatus5, AR_TxRSSICombined);
824 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
825 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
826 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
827 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
828 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
829 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
830 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
831 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
832 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
833 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
834 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
835 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
836 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
841 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
842 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
843 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
846 struct ar5416_desc *ads = AR5416DESC(ds);
848 HALASSERT(isValidPktType(type));
849 HALASSERT(isValidKeyType(keyType));
854 ads->ds_ctl0 = (pktLen & AR_FrameLen)
855 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
856 | SM(txPower, AR_XmitPower)
857 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
858 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
859 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
860 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
861 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
862 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
864 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
865 | SM(type, AR_FrameType)
866 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
867 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
868 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
870 ads->ds_ctl6 = SM(keyType, AR_EncrType);
875 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
876 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
877 a_uint32_t rtsctsDuration,
878 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
881 struct ar5416_desc *ads = AR5416DESC(ds);
884 HALASSERT(nseries == 4);
888 * Rate control settings override
890 ds_ctl0 = ads->ds_ctl0;
892 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
893 if (flags & HAL_TXDESC_RTSENA) {
894 ds_ctl0 &= ~AR_CTSEnable;
895 ds_ctl0 |= AR_RTSEnable;
897 ds_ctl0 &= ~AR_RTSEnable;
898 ds_ctl0 |= AR_CTSEnable;
901 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
904 ads->ds_ctl0 = ds_ctl0;
906 ads->ds_ctl2 = set11nTries(series, 0)
907 | set11nTries(series, 1)
908 | set11nTries(series, 2)
909 | set11nTries(series, 3)
910 | (durUpdateEn ? AR_DurUpdateEn : 0);
912 ads->ds_ctl3 = set11nRate(series, 0)
913 | set11nRate(series, 1)
914 | set11nRate(series, 2)
915 | set11nRate(series, 3);
917 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
918 | set11nPktDurRTSCTS(series, 1);
920 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
921 | set11nPktDurRTSCTS(series, 3);
923 ads->ds_ctl7 = set11nRateFlags(series, 0)
924 | set11nRateFlags(series, 1)
925 | set11nRateFlags(series, 2)
926 | set11nRateFlags(series, 3)
927 | SM(rtsctsRate, AR_RTSCTSRate);
932 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
933 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
934 a_uint32_t rtsctsDuration,
935 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
938 struct ar5416_desc *ads = AR5416DESC(ds);
941 HALASSERT(nseries == 4);
945 * Rate control settings override
947 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
948 ds_ctl0 = ads->ds_ctl0;
950 if (flags & HAL_TXDESC_RTSENA) {
951 ds_ctl0 &= ~AR_CTSEnable;
952 ds_ctl0 |= AR_RTSEnable;
954 ds_ctl0 &= ~AR_RTSEnable;
955 ds_ctl0 |= AR_CTSEnable;
958 ads->ds_ctl0 = ds_ctl0;
961 ads->ds_ctl2 = set11nTries(series, 0)
962 | set11nTries(series, 1)
963 | set11nTries(series, 2)
964 | set11nTries(series, 3)
965 | (durUpdateEn ? AR_DurUpdateEn : 0);
967 ads->ds_ctl3 = set11nRate(series, 0)
968 | set11nRate(series, 1)
969 | set11nRate(series, 2)
970 | set11nRate(series, 3);
972 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
973 | set11nPktDurRTSCTS(series, 1);
975 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
976 | set11nPktDurRTSCTS(series, 3);
978 ads->ds_ctl7 = set11nRateFlags(series, 0)
979 | set11nRateFlags(series, 1)
980 | set11nRateFlags(series, 2)
981 | set11nRateFlags(series, 3)
982 | SM(rtsctsRate, AR_RTSCTSRate);
987 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
988 a_uint32_t numDelims)
990 struct ar5416_desc *ads = AR5416DESC(ds);
992 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
994 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
995 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
996 SM(numDelims, AR_PadDelim);
999 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
1001 struct ar5416_desc *ads = AR5416DESC(ds);
1004 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1007 * We use a stack variable to manipulate ctl6 to reduce uncached
1008 * read modify, modfiy, write.
1010 ctl6 = ads->ds_ctl6;
1011 ctl6 &= ~AR_PadDelim;
1012 ctl6 |= SM(numDelims, AR_PadDelim);
1013 ads->ds_ctl6 = ctl6;
1016 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1018 struct ar5416_desc *ads = AR5416DESC(ds);
1020 ads->ds_ctl1 |= AR_IsAggr;
1021 ads->ds_ctl1 &= ~AR_MoreAggr;
1022 ads->ds_ctl6 &= ~AR_PadDelim;
1025 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1027 struct ar5416_desc *ads = AR5416DESC(ds);
1029 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1032 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1033 a_uint32_t burstDuration)
1035 struct ar5416_desc *ads = AR5416DESC(ds);
1037 ads->ds_ctl2 &= ~AR_BurstDur;
1038 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1041 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1044 struct ar5416_desc *ads = AR5416DESC(ds);
1047 ads->ds_ctl0 |= AR_VirtMoreFrag;
1049 ads->ds_ctl0 &= ~AR_VirtMoreFrag;