2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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38 #include "ah_internal.h"
40 #include "ar5416reg.h"
41 #include "ar5416phy.h"
42 #include "ar5416desc.h"
44 #define N(a) (sizeof(a)/sizeof(a[0]))
45 #define AR_INTR_SPURIOUS 0xffffffff
46 #define ar5416_desc ar5416_desc_20
47 #define AR5416_ABORT_LOOPS 1000
48 #define AR5416_ABORT_WAIT 5
49 #define AR5416DESC AR5416DESC_20
50 #define AR5416DESC_CONST AR5416DESC_CONST_20
56 static const struct ath_hal_private ar5416hal_10 = {{
57 .ah_getRateTable = ar5416GetRateTable,
58 .ah_detach = ar5416Detach,
60 /* Transmit functions */
61 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
62 .ah_getTxDP = ar5416GetTxDP,
63 .ah_setTxDP = ar5416SetTxDP,
64 .ah_numTxPending = ar5416NumTxPending,
65 .ah_startTxDma = ar5416StartTxDma,
66 .ah_stopTxDma = ar5416StopTxDma,
68 .ah_getTxIntrQueue = ar5416GetTxIntrQueue,
69 .ah_abortTxDma = ar5416AbortTxDma,
72 .ah_getCapability = ar5416GetCapability,
73 .ah_getTsf32 = ar5416GetTsf32,
74 .ah_getTsf64 = ar5416GetTsf64,
75 .ah_resetTsf = ar5416ResetTsf,
76 .ah_setRxFilter = ar5416SetRxFilter,
79 .ah_getRxDP = ar5416GetRxDP,
80 .ah_setRxDP = ar5416SetRxDP,
81 .ah_stopDmaReceive = ar5416StopDmaReceive,
82 .ah_enableReceive = ar5416EnableReceive,
83 .ah_startPcuReceive = ar5416StartPcuReceive,
84 .ah_stopPcuReceive = ar5416StopPcuReceive,
86 /* Interrupt Functions */
87 .ah_isInterruptPending = ar5416IsInterruptPending,
88 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
89 .ah_getInterrupts = ar5416GetInterrupts,
90 .ah_setInterrupts = ar5416SetInterrupts,
94 void ar5416Detach(struct ath_hal *ah)
96 HALASSERT(ah != AH_NULL);
101 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
102 a_uint32_t flags, HAL_STATUS *status)
104 struct ath_hal_5416 *ahp;
107 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
108 if (ahp == AH_NULL) {
109 *status = HAL_ENOMEM;
112 ah = &ahp->ah_priv.h;
114 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
119 /* If its a Owl 2.0 chip then change the hal structure to
120 point to the Owl 2.0 ar5416_hal_20 structure */
122 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
123 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
124 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
125 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
126 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
127 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
128 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
129 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
130 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
131 ah->ah_updateCTSForBursting = NULL;
132 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
133 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
134 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
135 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
136 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
137 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
143 /**********************/
144 /* Interrupt Handling */
145 /**********************/
147 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
149 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
151 * Some platforms trigger our ISR before applying power to
152 * the card, so make sure.
154 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
157 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
161 HAL_BOOL fatal_int = AH_FALSE;
162 a_uint32_t sync_cause;
164 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
165 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
174 isr = OS_REG_READ(ah, AR_ISR_RAC);
175 if (isr == 0xffffffff) {
180 *masked = isr & HAL_INT_COMMON;
182 #ifdef AR5416_INT_MITIGATION
183 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
184 *masked |= HAL_INT_RX;
186 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
187 *masked |= HAL_INT_TX;
191 if (isr & AR_ISR_BCNMISC) {
194 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
196 if (s2_s & AR_ISR_S2_GTT) {
197 *masked |= HAL_INT_GTT;
200 if (s2_s & AR_ISR_S2_CST) {
201 *masked |= HAL_INT_CST;
205 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
206 *masked |= HAL_INT_RX;
207 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
208 struct ath_hal_5416 *ahp = AH5416(ah);
209 a_uint32_t s0_s, s1_s;
211 *masked |= HAL_INT_TX;
212 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
213 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
214 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
215 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
216 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
217 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
221 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
222 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
223 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
226 if (AH_TRUE == fatal_int) {
227 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
228 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
234 HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
236 return AH5416(ah)->ah_maskReg;
240 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
242 struct ath_hal_5416 *ahp = AH5416(ah);
243 a_uint32_t omask = ahp->ah_maskReg;
246 if (omask & HAL_INT_GLOBAL) {
247 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
248 (void) OS_REG_READ(ah, AR_IER);
251 mask = ints & HAL_INT_COMMON;
252 if (ints & HAL_INT_TX) {
253 #ifdef AR5416_INT_MITIGATION
254 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
257 mask |= AR_IMR_TXDESC;
259 mask |= AR_IMR_TXERR;
260 mask |= AR_IMR_TXEOL;
262 if (ints & HAL_INT_RX) {
263 mask |= AR_IMR_RXERR;
264 #ifdef AR5416_INT_MITIGATION
265 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
267 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
271 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
272 mask |= AR_IMR_BCNMISC;
275 OS_REG_WRITE(ah, AR_IMR, mask);
276 (void) OS_REG_READ(ah, AR_IMR);
277 ahp->ah_maskReg = ints;
279 /* Re-enable interrupts if they were enabled before. */
280 if (ints & HAL_INT_GLOBAL) {
281 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
282 /* See explanation above... */
283 (void) OS_REG_READ(ah, AR_IER);
286 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
287 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
288 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
297 HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
298 a_uint32_t capability, a_uint32_t *result)
301 return ath_hal_getcapability(ah, type, capability, result);
308 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
312 tsf = OS_REG_READ(ah, AR_TSF_U32);
313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
318 a_uint32_t ar5416GetTsf32(struct ath_hal *ah)
320 return OS_REG_READ(ah, AR_TSF_L32);
323 void ar5416ResetTsf(struct ath_hal *ah)
329 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
336 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
343 a_uint32_t ar5416GetRxDP(struct ath_hal *ath)
345 return OS_REG_READ(ath, AR_RXDP);
349 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
351 OS_REG_WRITE(ah, AR_RXDP, rxdp);
352 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
355 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
357 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
358 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
361 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
368 val = OS_REG_READ(ah, AR_MCAST_FIL1);
369 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
371 val = OS_REG_READ(ah, AR_MCAST_FIL0);
372 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
377 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
379 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
380 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
387 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
394 val = OS_REG_READ(ah, AR_MCAST_FIL1);
395 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
397 val = OS_REG_READ(ah, AR_MCAST_FIL0);
398 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
403 void ar5416StartPcuReceive(struct ath_hal *ah)
405 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
406 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
409 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
413 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
415 if (bits & HAL_RX_FILTER_PHYRADAR)
416 phybits |= AR_PHY_ERR_RADAR;
417 if (bits & HAL_RX_FILTER_PHYERR)
418 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
419 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
421 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
423 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
427 void ar5416EnableReceive(struct ath_hal *ah)
429 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
432 void ar5416StopPcuReceive(struct ath_hal *ah)
434 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
437 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
438 a_uint32_t size, a_uint32_t flags)
440 struct ar5416_desc *ads = AR5416DESC(ds);
442 HALASSERT((size &~ AR_BufLen) == 0);
444 ads->ds_ctl1 = size & AR_BufLen;
445 if (flags & HAL_RXDESC_INTREQ)
446 ads->ds_ctl1 |= AR_RxIntrReq;
448 /* this should be enough */
449 ads->ds_rxstatus8 &= ~AR_RxDone;
454 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
455 a_uint32_t pa, struct ath_desc *nds,
456 struct ath_rx_status *rx_stats)
458 struct ar5416_desc ads;
459 struct ar5416_desc *adsp = AR5416DESC(ds);
460 struct ar5416_desc *ands = AR5416DESC(nds);
462 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
463 return HAL_EINPROGRESS;
465 * Given the use of a self-linked tail be very sure that the hw is
466 * done with this descriptor; the hw may have done this descriptor
467 * once and picked it up again...make sure the hw has moved on.
469 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
470 && OS_REG_READ(ah, AR_RXDP) == pa)
471 return HAL_EINPROGRESS;
474 * Now we need to get the stats from the descriptor. Since desc are
475 * uncached, lets make a copy of the stats first. Note that, since we
476 * touch most of the rx stats, a memcpy would always be more efficient
478 * Next we fill in all values in a caller passed stack variable.
479 * This reduces the number of uncached accesses.
480 * Do this copy here, after the check so that when the checks fail, we
481 * dont end up copying the entire stats uselessly.
483 ads.u.rx = adsp->u.rx;
485 rx_stats->rs_status = 0;
486 rx_stats->rs_flags = 0;
488 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
489 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
491 /* XXX what about KeyCacheMiss? */
492 rx_stats->rs_rssi_combined =
493 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
494 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
495 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
496 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
497 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
498 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
499 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
500 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
501 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
503 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
504 /* NB: caller expected to do rate table mapping */
505 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
506 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
508 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
509 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
510 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
511 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
513 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
514 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
515 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
516 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
517 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
518 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
520 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
522 * These four bits should not be set together. The
523 * 5416 spec states a Michael error can only occur if
524 * DecryptCRCErr not set (and TKIP is used). Experience
525 * indicates however that you can also get Michael errors
526 * when a CRC error is detected, but these are specious.
527 * Consequently we filter them out here so we don't
528 * confuse and/or complicate drivers.
530 if (ads.ds_rxstatus8 & AR_CRCErr)
531 rx_stats->rs_status |= HAL_RXERR_CRC;
532 else if (ads.ds_rxstatus8 & AR_PHYErr) {
535 rx_stats->rs_status |= HAL_RXERR_PHY;
536 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
537 rx_stats->rs_phyerr = phyerr;
538 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
539 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
540 else if (ads.ds_rxstatus8 & AR_MichaelErr)
541 rx_stats->rs_status |= HAL_RXERR_MIC;
543 rx_stats->evm0=ads.AR_RxEVM0;
544 rx_stats->evm1=ads.AR_RxEVM1;
545 rx_stats->evm2=ads.AR_RxEVM2;
554 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
556 struct ath_hal_5416 *ahp = AH5416(ah);
557 a_uint32_t txcfg, curLevel, newLevel;
561 * Disable interrupts while futzing with the fifo level.
563 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
565 txcfg = OS_REG_READ(ah, AR_TXCFG);
566 curLevel = MS(txcfg, AR_FTRIG);
570 if (curLevel < MAX_TX_FIFO_THRESHOLD)
572 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
574 if (newLevel != curLevel)
575 OS_REG_WRITE(ah, AR_TXCFG,
576 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
578 /* re-enable chip interrupts */
579 ar5416SetInterrupts(ah, omask);
581 return (newLevel != curLevel);
584 a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q)
586 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
587 return OS_REG_READ(ah, AR_QTXDP(q));
590 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
592 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
593 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
596 * Make sure that TXE is deasserted before setting the TXDP. If TXE
597 * is still asserted, setting TXDP will have no effect.
599 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
601 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
606 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
608 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
609 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
611 /* Check to be sure we're not enabling a q that has its TXD bit set. */
612 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
614 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
619 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
623 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
624 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
626 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
629 * Pending frame count (PFC) can momentarily go to zero
630 * while TXE remains asserted. In other words a PFC of
631 * zero is not sufficient to say that the queue has stopped.
633 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
637 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
638 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
639 isrPrintf("RTSD on CAB queue\n");
640 /* Clear the ReadyTime shutdown status bits */
641 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
648 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
653 * set txd on all queues
655 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
660 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
661 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
662 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
665 * wait on all tx queues
667 for (q = 0; q < AR_NUM_QCU; q++) {
668 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
669 if (!ar5416NumTxPending(ah, q))
672 OS_DELAY(AR5416_ABORT_WAIT);
674 if (i == AR5416_ABORT_LOOPS) {
680 * clear tx abort bits
682 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
683 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
684 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
689 OS_REG_WRITE(ah, AR_Q_TXD, 0);
694 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
698 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
700 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
702 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
703 for (i = 1000; i != 0; i--) {
704 if (ar5416NumTxPending(ah, q) == 0)
706 OS_DELAY(100); /* XXX get actual value */
709 OS_REG_WRITE(ah, AR_Q_TXD, 0);
713 void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs)
715 struct ath_hal_5416 *ahp = AH5416(ah);
716 *txqs &= ahp->ah_intrTxqs;
717 ahp->ah_intrTxqs &= ~(*txqs);
720 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
722 struct ar5416_desc *ads = AR5416DESC(ds);
723 ads->ds_ctl0 |= AR_TxIntrReq;
726 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
731 a_uint32_t txRate0, a_uint32_t txTries0,
735 a_uint32_t rtsctsRate,
736 a_uint32_t rtsctsDuration,
737 a_uint32_t compicvLen,
738 a_uint32_t compivLen,
741 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
743 struct ar5416_desc *ads = AR5416DESC(ds);
747 ads->ds_txstatus9 &= ~AR_TxDone;
749 HALASSERT(txTries0 != 0);
750 HALASSERT(isValidPktType(type));
751 HALASSERT(isValidTxRate(txRate0));
752 HALASSERT((flags & RTSCTS) != RTSCTS);
757 ads->ds_ctl0 = (pktLen & AR_FrameLen)
758 | (txPower << AR_XmitPower_S)
759 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
760 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
761 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
763 ads->ds_ctl1 = (type << AR_FrameType_S)
764 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
765 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
766 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
768 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
769 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
770 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
771 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
773 if (keyIx != HAL_TXKEYIX_INVALID) {
774 /* XXX validate key index */
775 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
776 ads->ds_ctl0 |= AR_DestIdxValid;
779 if (flags & RTSCTS) {
780 if (!isValidTxRate(rtsctsRate)) {
783 /* XXX validate rtsctsDuration */
784 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
785 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
786 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
787 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
794 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
795 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
796 const struct ath_tx_desc *ds0)
798 struct ar5416_desc *ads = AR5416DESC(ds);
800 HALASSERT((segLen &~ AR_BufLen) == 0);
804 * First descriptor, don't clobber xmit control data
805 * setup by ar5416SetupTxDesc.
807 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
808 } else if (lastSeg) {
810 * Last descriptor in a multi-descriptor frame,
811 * copy the multi-rate transmit parameters from
812 * the first frame for processing on completion.
815 ads->ds_ctl1 = segLen;
816 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
817 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
820 * Intermediate descriptor in a multi-descriptor frame.
823 ads->ds_ctl1 = segLen | AR_TxMore;
827 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
832 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
833 HAL_KEY_TYPE keyType)
835 struct ar5416_desc *ads = AR5416DESC(ds);
837 ads->ds_ctl6 = SM(keyType, AR_EncrType);
841 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
843 struct ar5416_desc *ads = AR5416DESC(gds);
844 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
846 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
847 return HAL_EINPROGRESS;
849 ads->ds_txstatus9 &= ~AR_TxDone;
851 /* Update software copies of the HW status */
852 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
853 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
854 ds->ds_txstat.ts_status = 0;
855 ds->ds_txstat.ts_flags = 0;
857 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
858 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
859 if (ads->ds_txstatus1 & AR_Filtered)
860 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
861 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
862 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
863 if (ads->ds_txstatus9 & AR_TxOpExceeded)
864 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
865 if (ads->ds_txstatus1 & AR_TxTimerExpired)
866 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
868 if (ads->ds_txstatus1 & AR_DescCfgErr)
869 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
870 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
871 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
872 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
874 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
875 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
876 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
878 if (ads->ds_txstatus0 & AR_TxBaStatus) {
879 ds->ds_txstat.ts_flags |= HAL_TX_BA;
880 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
881 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
885 * Extract the transmit rate used and mark the rate as
886 * ``alternate'' if it wasn't the series 0 rate.
888 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
889 ds->ds_txstat.ts_rssi_combined =
890 MS(ads->ds_txstatus5, AR_TxRSSICombined);
891 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
892 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
893 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
894 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
895 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
896 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
897 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
898 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
899 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
900 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
901 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
902 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
903 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
908 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
909 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
910 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
913 struct ar5416_desc *ads = AR5416DESC(ds);
915 HALASSERT(isValidPktType(type));
916 HALASSERT(isValidKeyType(keyType));
921 ads->ds_ctl0 = (pktLen & AR_FrameLen)
922 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
923 | SM(txPower, AR_XmitPower)
924 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
925 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
926 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
927 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
928 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
929 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
931 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
932 | SM(type, AR_FrameType)
933 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
934 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
935 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
937 ads->ds_ctl6 = SM(keyType, AR_EncrType);
942 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
943 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
944 a_uint32_t rtsctsDuration,
945 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
948 struct ar5416_desc *ads = AR5416DESC(ds);
951 HALASSERT(nseries == 4);
955 * Rate control settings override
957 ds_ctl0 = ads->ds_ctl0;
959 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
960 if (flags & HAL_TXDESC_RTSENA) {
961 ds_ctl0 &= ~AR_CTSEnable;
962 ds_ctl0 |= AR_RTSEnable;
964 ds_ctl0 &= ~AR_RTSEnable;
965 ds_ctl0 |= AR_CTSEnable;
968 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
971 ads->ds_ctl0 = ds_ctl0;
973 ads->ds_ctl2 = set11nTries(series, 0)
974 | set11nTries(series, 1)
975 | set11nTries(series, 2)
976 | set11nTries(series, 3)
977 | (durUpdateEn ? AR_DurUpdateEn : 0);
979 ads->ds_ctl3 = set11nRate(series, 0)
980 | set11nRate(series, 1)
981 | set11nRate(series, 2)
982 | set11nRate(series, 3);
984 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
985 | set11nPktDurRTSCTS(series, 1);
987 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
988 | set11nPktDurRTSCTS(series, 3);
990 ads->ds_ctl7 = set11nRateFlags(series, 0)
991 | set11nRateFlags(series, 1)
992 | set11nRateFlags(series, 2)
993 | set11nRateFlags(series, 3)
994 | SM(rtsctsRate, AR_RTSCTSRate);
999 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1000 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
1001 a_uint32_t rtsctsDuration,
1002 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
1005 struct ar5416_desc *ads = AR5416DESC(ds);
1008 HALASSERT(nseries == 4);
1012 * Rate control settings override
1014 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
1015 ds_ctl0 = ads->ds_ctl0;
1017 if (flags & HAL_TXDESC_RTSENA) {
1018 ds_ctl0 &= ~AR_CTSEnable;
1019 ds_ctl0 |= AR_RTSEnable;
1021 ds_ctl0 &= ~AR_RTSEnable;
1022 ds_ctl0 |= AR_CTSEnable;
1025 ads->ds_ctl0 = ds_ctl0;
1028 ads->ds_ctl2 = set11nTries(series, 0)
1029 | set11nTries(series, 1)
1030 | set11nTries(series, 2)
1031 | set11nTries(series, 3)
1032 | (durUpdateEn ? AR_DurUpdateEn : 0);
1034 ads->ds_ctl3 = set11nRate(series, 0)
1035 | set11nRate(series, 1)
1036 | set11nRate(series, 2)
1037 | set11nRate(series, 3);
1039 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1040 | set11nPktDurRTSCTS(series, 1);
1042 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1043 | set11nPktDurRTSCTS(series, 3);
1045 ads->ds_ctl7 = set11nRateFlags(series, 0)
1046 | set11nRateFlags(series, 1)
1047 | set11nRateFlags(series, 2)
1048 | set11nRateFlags(series, 3)
1049 | SM(rtsctsRate, AR_RTSCTSRate);
1054 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
1055 a_uint32_t numDelims)
1057 struct ar5416_desc *ads = AR5416DESC(ds);
1059 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1061 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
1062 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
1063 SM(numDelims, AR_PadDelim);
1066 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
1068 struct ar5416_desc *ads = AR5416DESC(ds);
1071 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1074 * We use a stack variable to manipulate ctl6 to reduce uncached
1075 * read modify, modfiy, write.
1077 ctl6 = ads->ds_ctl6;
1078 ctl6 &= ~AR_PadDelim;
1079 ctl6 |= SM(numDelims, AR_PadDelim);
1080 ads->ds_ctl6 = ctl6;
1083 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1085 struct ar5416_desc *ads = AR5416DESC(ds);
1087 ads->ds_ctl1 |= AR_IsAggr;
1088 ads->ds_ctl1 &= ~AR_MoreAggr;
1089 ads->ds_ctl6 &= ~AR_PadDelim;
1092 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1094 struct ar5416_desc *ads = AR5416DESC(ds);
1096 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1099 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1100 a_uint32_t burstDuration)
1102 struct ar5416_desc *ads = AR5416DESC(ds);
1104 ads->ds_ctl2 &= ~AR_BurstDur;
1105 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1108 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1111 struct ar5416_desc *ads = AR5416DESC(ds);
1114 ads->ds_ctl0 |= AR_VirtMoreFrag;
1116 ads->ds_ctl0 &= ~AR_VirtMoreFrag;