2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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36 #include <ar5416desc.h>
38 extern HAL_STATUS ar5416GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
39 a_uint32_t, a_uint32_t *);
40 extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, a_uint32_t mode);
41 extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah);
42 extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
43 extern HAL_INT ar5416GetInterrupts(struct ath_hal *ah);
44 extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints);
45 extern a_uint32_t ar5416Get11nExtBusy(struct ath_hal *ah);
46 extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah);
47 extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear);
48 extern a_uint32_t ar5416GetTsf32(struct ath_hal *ah);
49 extern u_int64_t ar5416GetTsf64(struct ath_hal *ah);
50 extern void ar5416ResetTsf(struct ath_hal *ah);
51 extern void ar5416Detach(struct ath_hal *ah);
53 typedef enum Ar5416_Rates {
54 rate6mb, rate9mb, rate12mb, rate18mb,
55 rate24mb, rate36mb, rate48mb, rate54mb,
56 rate1l, rate2l, rate2s, rate5_5l,
57 rate5_5s, rate11l, rate11s, rateXr,
58 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
59 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
60 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
61 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
62 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
67 #define AR_SREV_HOWL(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_HOWL)
68 #define IS_5416_HOWL AR_SREV_HOWL
70 #define AR5416_RATES_OFDM_OFFSET 0
71 #define AR5416_RATES_CCK_OFFSET 8
72 #define AR5416_RATES_HT20_OFFSET 16
73 #define AR5416_RATES_HT40_OFFSET 24
75 /* Delta from which to start power to pdadc table */
77 #define AR5416_PWR_TABLE_OFFSET -5
78 #define AR5416_LEGACY_CHAINMASK 1
79 #define AR5416_1_CHAINMASK 1
80 #define AR5416_2LOHI_CHAINMASK 5
81 #define AR5416_2LOMID_CHAINMASK 3
82 #define AR5416_3_CHAINMASK 7
84 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
88 #endif // MAGPIE_MERLIN
90 #define AR5416_LEGACY_CHAINMASK 1
92 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
95 * Various fifo fill before Tx start, in 64-byte units
96 * i.e. put the frame in the air while still DMAing
98 #define MIN_TX_FIFO_THRESHOLD 0x1
99 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1)
100 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
104 struct ath_hal_private ah_priv; /* base class */
105 a_uint16_t ah_antennaSwitchSwap; /* Controls mapping of OID request */
106 a_uint32_t ah_maskReg; /* copy of AR_IMR */
108 a_uint32_t ah_slottime; /* user-specified slot time */
109 a_int16_t ah_txPowerIndexOffset;
111 a_uint32_t ah_intrTxqs;
113 a_uint16_t ah_ratesArray[Ar5416RateSize];