2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
37 #include <linux/irq.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/barrier.h>
46 #include <asm/mpspec.h>
47 #include <asm/i8259.h>
48 #include <asm/proto.h>
50 #include <asm/io_apic.h>
58 #include <asm/hypervisor.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/intel-family.h>
61 #include <asm/irq_regs.h>
63 unsigned int num_processors;
65 unsigned disabled_cpus;
67 /* Processor that is doing the boot up */
68 unsigned int boot_cpu_physical_apicid = -1U;
69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
71 u8 boot_cpu_apic_version;
74 * The highest APIC ID seen during enumeration.
76 static unsigned int max_physical_apicid;
79 * Bitmask of physically existing CPUs:
81 physid_mask_t phys_cpu_present_map;
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
94 static int apic_extnmi = APIC_EXTNMI_BSP;
97 * Map cpu index to physical APIC ID
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase;
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
127 static inline void imcr_pic_to_apic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go through APIC */
135 static inline void imcr_apic_to_pic(void)
137 /* select IMCR register */
139 /* NMI and 8259 INTR go directly to BSP */
145 * Knob to control our willingness to enable the local APIC.
149 static int force_enable_local_apic __initdata;
152 * APIC command line parameters
154 static int __init parse_lapic(char *arg)
156 if (IS_ENABLED(CONFIG_X86_32) && !arg)
157 force_enable_local_apic = 1;
158 else if (arg && !strncmp(arg, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
162 early_param("lapic", parse_lapic);
165 static int apic_calibrate_pmtmr __initdata;
166 static __init int setup_apicpmtimer(char *s)
168 apic_calibrate_pmtmr = 1;
172 __setup("apicpmtimer", setup_apicpmtimer);
175 unsigned long mp_lapic_addr;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
184 * Debug level, exported for io_apic.c
190 /* Have we found an MP table */
191 int smp_found_config;
193 static struct resource lapic_resource = {
194 .name = "Local APIC",
195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
198 unsigned int lapic_timer_frequency = 0;
200 static void apic_pm_activate(void);
202 static unsigned long apic_phys;
205 * Get the LAPIC version
207 static inline int lapic_get_version(void)
209 return GET_APIC_VERSION(apic_read(APIC_LVR));
213 * Check, if the APIC is integrated or a separate chip
215 static inline int lapic_is_integrated(void)
220 return APIC_INTEGRATED(lapic_get_version());
225 * Check, whether this is a modern or a first generation APIC
227 static int modern_apic(void)
229 /* AMD systems use old APIC versions, so check the CPU */
230 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
231 boot_cpu_data.x86 >= 0xf)
233 return lapic_get_version() >= 0x14;
237 * right after this call apic become NOOP driven
238 * so apic->write/read doesn't do anything
240 static void __init apic_disable(void)
242 pr_info("APIC: switched to apic NOOP\n");
246 void native_apic_wait_icr_idle(void)
248 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
252 u32 native_safe_apic_wait_icr_idle(void)
259 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 inc_irq_stat(icr_read_retry_count);
264 } while (timeout++ < 1000);
269 void native_apic_icr_write(u32 low, u32 id)
273 local_irq_save(flags);
274 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
275 apic_write(APIC_ICR, low);
276 local_irq_restore(flags);
279 u64 native_apic_icr_read(void)
283 icr2 = apic_read(APIC_ICR2);
284 icr1 = apic_read(APIC_ICR);
286 return icr1 | ((u64)icr2 << 32);
291 * get_physical_broadcast - Get number of physical broadcast IDs
293 int get_physical_broadcast(void)
295 return modern_apic() ? 0xff : 0xf;
300 * lapic_get_maxlvt - get the maximum number of local vector table entries
302 int lapic_get_maxlvt(void)
306 v = apic_read(APIC_LVR);
308 * - we always have APIC integrated on 64bit mode
309 * - 82489DXs do not report # of LVT entries
311 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
319 #define APIC_DIVISOR 16
320 #define TSC_DIVISOR 8
323 * This function sets up the local APIC timer, with a timeout of
324 * 'clocks' APIC bus clock. During calibration we actually call
325 * this function twice on the boot CPU, once with a bogus timeout
326 * value, second time for real. The other (noncalibrating) CPUs
327 * call this function only once, with the real, calibrated value.
329 * We do reads before writes even if unnecessary, to get around the
330 * P5 APIC double write bug.
332 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
334 unsigned int lvtt_value, tmp_value;
336 lvtt_value = LOCAL_TIMER_VECTOR;
338 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
339 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
340 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
342 if (!lapic_is_integrated())
343 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
346 lvtt_value |= APIC_LVT_MASKED;
348 apic_write(APIC_LVTT, lvtt_value);
350 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
352 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
353 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
354 * According to Intel, MFENCE can do the serialization here.
356 asm volatile("mfence" : : : "memory");
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 unsigned int rsvd, vector;
405 if (offset >= APIC_EILVT_NR_MAX)
408 rsvd = atomic_read(&eilvt_offsets[offset]);
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
417 rsvd &= ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
456 apic_write(reg, new);
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
463 * Program the next event, relative to now
465 static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
468 apic_write(APIC_TMICT, delta);
472 static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
477 /* This MSR is special and need a special fence: */
481 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
485 static int lapic_timer_shutdown(struct clock_event_device *evt)
489 /* Lapic used as dummy for broadcast ? */
490 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
493 v = apic_read(APIC_LVTT);
494 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
495 apic_write(APIC_LVTT, v);
496 apic_write(APIC_TMICT, 0);
501 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
503 /* Lapic used as dummy for broadcast ? */
504 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
507 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
511 static int lapic_timer_set_periodic(struct clock_event_device *evt)
513 return lapic_timer_set_periodic_oneshot(evt, false);
516 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
518 return lapic_timer_set_periodic_oneshot(evt, true);
522 * Local APIC timer broadcast function
524 static void lapic_timer_broadcast(const struct cpumask *mask)
527 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
533 * The local apic timer can be used for any function which is CPU local.
535 static struct clock_event_device lapic_clockevent = {
537 .features = CLOCK_EVT_FEAT_PERIODIC |
538 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
539 | CLOCK_EVT_FEAT_DUMMY,
541 .set_state_shutdown = lapic_timer_shutdown,
542 .set_state_periodic = lapic_timer_set_periodic,
543 .set_state_oneshot = lapic_timer_set_oneshot,
544 .set_state_oneshot_stopped = lapic_timer_shutdown,
545 .set_next_event = lapic_next_event,
546 .broadcast = lapic_timer_broadcast,
550 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
552 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
555 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
556 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
558 static __init u32 hsx_deadline_rev(void)
560 switch (boot_cpu_data.x86_stepping) {
561 case 0x02: return 0x3a; /* EP */
562 case 0x04: return 0x0f; /* EX */
568 static __init u32 bdx_deadline_rev(void)
570 switch (boot_cpu_data.x86_stepping) {
571 case 0x02: return 0x00000011;
572 case 0x03: return 0x0700000e;
573 case 0x04: return 0x0f00000c;
574 case 0x05: return 0x0e000003;
580 static __init u32 skx_deadline_rev(void)
582 switch (boot_cpu_data.x86_stepping) {
583 case 0x03: return 0x01000136;
584 case 0x04: return 0x02000014;
587 if (boot_cpu_data.x86_stepping > 4)
593 static const struct x86_cpu_id deadline_match[] __initconst = {
594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
596 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
597 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
609 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
610 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
615 static __init bool apic_validate_deadline_timer(void)
617 const struct x86_cpu_id *m;
620 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
622 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
625 m = x86_match_cpu(deadline_match);
630 * Function pointers will have the MSB set due to address layout,
631 * immediate revisions will not.
633 if ((long)m->driver_data < 0)
634 rev = ((u32 (*)(void))(m->driver_data))();
636 rev = (u32)m->driver_data;
638 if (boot_cpu_data.microcode >= rev)
641 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
642 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
643 "/*(DEBLOBBED)*/\n", rev);
648 * Setup the local APIC timer for this CPU. Copy the initialized values
649 * of the boot CPU and register the clock event in the framework.
651 static void setup_APIC_timer(void)
653 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
655 if (this_cpu_has(X86_FEATURE_ARAT)) {
656 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
657 /* Make LAPIC timer preferrable over percpu HPET */
658 lapic_clockevent.rating = 150;
661 memcpy(levt, &lapic_clockevent, sizeof(*levt));
662 levt->cpumask = cpumask_of(smp_processor_id());
664 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
665 levt->name = "lapic-deadline";
666 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
667 CLOCK_EVT_FEAT_DUMMY);
668 levt->set_next_event = lapic_next_deadline;
669 clockevents_config_and_register(levt,
670 tsc_khz * (1000 / TSC_DIVISOR),
673 clockevents_register_device(levt);
677 * Install the updated TSC frequency from recalibration at the TSC
678 * deadline clockevent devices.
680 static void __lapic_update_tsc_freq(void *info)
682 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
684 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
687 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
690 void lapic_update_tsc_freq(void)
693 * The clockevent device's ->mult and ->shift can both be
694 * changed. In order to avoid races, schedule the frequency
695 * update code on each CPU.
697 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
701 * In this functions we calibrate APIC bus clocks to the external timer.
703 * We want to do the calibration only once since we want to have local timer
704 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
707 * This was previously done by reading the PIT/HPET and waiting for a wrap
708 * around to find out, that a tick has elapsed. I have a box, where the PIT
709 * readout is broken, so it never gets out of the wait loop again. This was
710 * also reported by others.
712 * Monitoring the jiffies value is inaccurate and the clockevents
713 * infrastructure allows us to do a simple substitution of the interrupt
716 * The calibration routine also uses the pm_timer when possible, as the PIT
717 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
718 * back to normal later in the boot process).
721 #define LAPIC_CAL_LOOPS (HZ/10)
723 static __initdata int lapic_cal_loops = -1;
724 static __initdata long lapic_cal_t1, lapic_cal_t2;
725 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
726 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
727 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
730 * Temporary interrupt handler and polled calibration function.
732 static void __init lapic_cal_handler(struct clock_event_device *dev)
734 unsigned long long tsc = 0;
735 long tapic = apic_read(APIC_TMCCT);
736 unsigned long pm = acpi_pm_read_early();
738 if (boot_cpu_has(X86_FEATURE_TSC))
741 switch (lapic_cal_loops++) {
743 lapic_cal_t1 = tapic;
744 lapic_cal_tsc1 = tsc;
746 lapic_cal_j1 = jiffies;
749 case LAPIC_CAL_LOOPS:
750 lapic_cal_t2 = tapic;
751 lapic_cal_tsc2 = tsc;
752 if (pm < lapic_cal_pm1)
753 pm += ACPI_PM_OVRRUN;
755 lapic_cal_j2 = jiffies;
761 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
763 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
764 const long pm_thresh = pm_100ms / 100;
768 #ifndef CONFIG_X86_PM_TIMER
772 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
774 /* Check, if the PM timer is available */
778 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
780 if (deltapm > (pm_100ms - pm_thresh) &&
781 deltapm < (pm_100ms + pm_thresh)) {
782 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
786 res = (((u64)deltapm) * mult) >> 22;
787 do_div(res, 1000000);
788 pr_warning("APIC calibration not consistent "
789 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
791 /* Correct the lapic counter value */
792 res = (((u64)(*delta)) * pm_100ms);
793 do_div(res, deltapm);
794 pr_info("APIC delta adjusted to PM-Timer: "
795 "%lu (%ld)\n", (unsigned long)res, *delta);
798 /* Correct the tsc counter value */
799 if (boot_cpu_has(X86_FEATURE_TSC)) {
800 res = (((u64)(*deltatsc)) * pm_100ms);
801 do_div(res, deltapm);
802 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
803 "PM-Timer: %lu (%ld)\n",
804 (unsigned long)res, *deltatsc);
805 *deltatsc = (long)res;
811 static int __init calibrate_APIC_clock(void)
813 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
814 u64 tsc_perj = 0, tsc_start = 0;
815 unsigned long jif_start;
816 unsigned long deltaj;
817 long delta, deltatsc;
818 int pm_referenced = 0;
821 * check if lapic timer has already been calibrated by platform
822 * specific routine, such as tsc calibration code. if so, we just fill
823 * in the clockevent structure and return.
826 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
828 } else if (lapic_timer_frequency) {
829 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
830 lapic_timer_frequency);
831 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
832 TICK_NSEC, lapic_clockevent.shift);
833 lapic_clockevent.max_delta_ns =
834 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
835 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
836 lapic_clockevent.min_delta_ns =
837 clockevent_delta2ns(0xF, &lapic_clockevent);
838 lapic_clockevent.min_delta_ticks = 0xF;
839 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
843 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
844 "calibrating APIC timer ...\n");
847 * There are platforms w/o global clockevent devices. Instead of
848 * making the calibration conditional on that, use a polling based
849 * approach everywhere.
854 * Setup the APIC counter to maximum. There is no way the lapic
855 * can underflow in the 100ms detection time frame
857 __setup_APIC_LVTT(0xffffffff, 0, 0);
860 * Methods to terminate the calibration loop:
861 * 1) Global clockevent if available (jiffies)
862 * 2) TSC if available and frequency is known
864 jif_start = READ_ONCE(jiffies);
868 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
872 * Enable interrupts so the tick can fire, if a global
873 * clockevent device is available
877 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
878 /* Wait for a tick to elapse */
881 u64 tsc_now = rdtsc();
882 if ((tsc_now - tsc_start) >= tsc_perj) {
883 tsc_start += tsc_perj;
887 unsigned long jif_now = READ_ONCE(jiffies);
889 if (time_after(jif_now, jif_start)) {
897 /* Invoke the calibration routine */
899 lapic_cal_handler(NULL);
905 /* Build delta t1-t2 as apic timer counts down */
906 delta = lapic_cal_t1 - lapic_cal_t2;
907 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
909 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
911 /* we trust the PM based calibration if possible */
912 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
915 /* Calculate the scaled math multiplication factor */
916 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
917 lapic_clockevent.shift);
918 lapic_clockevent.max_delta_ns =
919 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
920 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
921 lapic_clockevent.min_delta_ns =
922 clockevent_delta2ns(0xF, &lapic_clockevent);
923 lapic_clockevent.min_delta_ticks = 0xF;
925 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
927 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
928 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
929 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
930 lapic_timer_frequency);
932 if (boot_cpu_has(X86_FEATURE_TSC)) {
933 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
935 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
936 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
939 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
941 lapic_timer_frequency / (1000000 / HZ),
942 lapic_timer_frequency % (1000000 / HZ));
945 * Do a sanity check on the APIC calibration result
947 if (lapic_timer_frequency < (1000000 / HZ)) {
949 pr_warning("APIC frequency too slow, disabling apic timer\n");
953 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
956 * PM timer calibration failed or not turned on so lets try APIC
957 * timer based calibration, if a global clockevent device is
960 if (!pm_referenced && global_clock_event) {
961 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
964 * Setup the apic timer manually
966 levt->event_handler = lapic_cal_handler;
967 lapic_timer_set_periodic(levt);
968 lapic_cal_loops = -1;
970 /* Let the interrupts run */
973 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
976 /* Stop the lapic timer */
978 lapic_timer_shutdown(levt);
981 deltaj = lapic_cal_j2 - lapic_cal_j1;
982 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
984 /* Check, if the jiffies result is consistent */
985 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
986 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
988 levt->features |= CLOCK_EVT_FEAT_DUMMY;
992 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
993 pr_warning("APIC timer disabled due to verification failure\n");
1001 * Setup the boot APIC
1003 * Calibrate and verify the result.
1005 void __init setup_boot_APIC_clock(void)
1008 * The local apic timer can be disabled via the kernel
1009 * commandline or from the CPU detection code. Register the lapic
1010 * timer as a dummy clock event source on SMP systems, so the
1011 * broadcast mechanism is used. On UP systems simply ignore it.
1013 if (disable_apic_timer) {
1014 pr_info("Disabling APIC timer\n");
1015 /* No broadcast on UP ! */
1016 if (num_possible_cpus() > 1) {
1017 lapic_clockevent.mult = 1;
1023 if (calibrate_APIC_clock()) {
1024 /* No broadcast on UP ! */
1025 if (num_possible_cpus() > 1)
1031 * If nmi_watchdog is set to IO_APIC, we need the
1032 * PIT/HPET going. Otherwise register lapic as a dummy
1035 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1037 /* Setup the lapic or request the broadcast */
1039 amd_e400_c1e_apic_setup();
1042 void setup_secondary_APIC_clock(void)
1045 amd_e400_c1e_apic_setup();
1049 * The guts of the apic timer interrupt
1051 static void local_apic_timer_interrupt(void)
1053 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1056 * Normally we should not be here till LAPIC has been initialized but
1057 * in some cases like kdump, its possible that there is a pending LAPIC
1058 * timer interrupt from previous kernel's context and is delivered in
1059 * new kernel the moment interrupts are enabled.
1061 * Interrupts are enabled early and LAPIC is setup much later, hence
1062 * its possible that when we get here evt->event_handler is NULL.
1063 * Check for event_handler being NULL and discard the interrupt as
1066 if (!evt->event_handler) {
1067 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1068 smp_processor_id());
1070 lapic_timer_shutdown(evt);
1075 * the NMI deadlock-detector uses this.
1077 inc_irq_stat(apic_timer_irqs);
1079 evt->event_handler(evt);
1083 * Local APIC timer interrupt. This is the most natural way for doing
1084 * local interrupts, but local timer interrupts can be emulated by
1085 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1087 * [ if a single-CPU system runs an SMP kernel then we call the local
1088 * interrupt as well. Thus we cannot inline the local irq ... ]
1090 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1092 struct pt_regs *old_regs = set_irq_regs(regs);
1095 * NOTE! We'd better ACK the irq immediately,
1096 * because timer handling can be slow.
1098 * update_process_times() expects us to have done irq_enter().
1099 * Besides, if we don't timer interrupts ignore the global
1100 * interrupt lock, which is the WrongThing (tm) to do.
1103 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1104 local_apic_timer_interrupt();
1105 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1108 set_irq_regs(old_regs);
1111 int setup_profiling_timer(unsigned int multiplier)
1117 * Local APIC start and shutdown
1121 * clear_local_APIC - shutdown the local APIC
1123 * This is called, when a CPU is disabled and before rebooting, so the state of
1124 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1125 * leftovers during boot.
1127 void clear_local_APIC(void)
1132 /* APIC hasn't been mapped yet */
1133 if (!x2apic_mode && !apic_phys)
1136 maxlvt = lapic_get_maxlvt();
1138 * Masking an LVT entry can trigger a local APIC error
1139 * if the vector is zero. Mask LVTERR first to prevent this.
1142 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1143 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1146 * Careful: we have to set masks only first to deassert
1147 * any level-triggered sources.
1149 v = apic_read(APIC_LVTT);
1150 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1151 v = apic_read(APIC_LVT0);
1152 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1153 v = apic_read(APIC_LVT1);
1154 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1156 v = apic_read(APIC_LVTPC);
1157 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1160 /* lets not touch this if we didn't frob it */
1161 #ifdef CONFIG_X86_THERMAL_VECTOR
1163 v = apic_read(APIC_LVTTHMR);
1164 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1167 #ifdef CONFIG_X86_MCE_INTEL
1169 v = apic_read(APIC_LVTCMCI);
1170 if (!(v & APIC_LVT_MASKED))
1171 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1176 * Clean APIC state for other OSs:
1178 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1179 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1180 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1182 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1184 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1186 /* Integrated APIC (!82489DX) ? */
1187 if (lapic_is_integrated()) {
1189 /* Clear ESR due to Pentium errata 3AP and 11AP */
1190 apic_write(APIC_ESR, 0);
1191 apic_read(APIC_ESR);
1196 * disable_local_APIC - clear and disable the local APIC
1198 void disable_local_APIC(void)
1202 /* APIC hasn't been mapped yet */
1203 if (!x2apic_mode && !apic_phys)
1209 * Disable APIC (implies clearing of registers
1212 value = apic_read(APIC_SPIV);
1213 value &= ~APIC_SPIV_APIC_ENABLED;
1214 apic_write(APIC_SPIV, value);
1216 #ifdef CONFIG_X86_32
1218 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1219 * restore the disabled state.
1221 if (enabled_via_apicbase) {
1224 rdmsr(MSR_IA32_APICBASE, l, h);
1225 l &= ~MSR_IA32_APICBASE_ENABLE;
1226 wrmsr(MSR_IA32_APICBASE, l, h);
1232 * If Linux enabled the LAPIC against the BIOS default disable it down before
1233 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1234 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1235 * for the case where Linux didn't enable the LAPIC.
1237 void lapic_shutdown(void)
1239 unsigned long flags;
1241 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1244 local_irq_save(flags);
1246 #ifdef CONFIG_X86_32
1247 if (!enabled_via_apicbase)
1251 disable_local_APIC();
1254 local_irq_restore(flags);
1258 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1260 void __init sync_Arb_IDs(void)
1263 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1266 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1272 apic_wait_icr_idle();
1274 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1275 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1276 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1280 * An initial setup of the virtual wire mode.
1282 void __init init_bsp_APIC(void)
1287 * Don't do the setup now if we have a SMP BIOS as the
1288 * through-I/O-APIC virtual wire mode might be active.
1290 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1294 * Do not trust the local APIC being empty at bootup.
1301 value = apic_read(APIC_SPIV);
1302 value &= ~APIC_VECTOR_MASK;
1303 value |= APIC_SPIV_APIC_ENABLED;
1305 #ifdef CONFIG_X86_32
1306 /* This bit is reserved on P4/Xeon and should be cleared */
1307 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1308 (boot_cpu_data.x86 == 15))
1309 value &= ~APIC_SPIV_FOCUS_DISABLED;
1312 value |= APIC_SPIV_FOCUS_DISABLED;
1313 value |= SPURIOUS_APIC_VECTOR;
1314 apic_write(APIC_SPIV, value);
1317 * Set up the virtual wire mode.
1319 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1320 value = APIC_DM_NMI;
1321 if (!lapic_is_integrated()) /* 82489DX */
1322 value |= APIC_LVT_LEVEL_TRIGGER;
1323 if (apic_extnmi == APIC_EXTNMI_NONE)
1324 value |= APIC_LVT_MASKED;
1325 apic_write(APIC_LVT1, value);
1328 static void lapic_setup_esr(void)
1330 unsigned int oldvalue, value, maxlvt;
1332 if (!lapic_is_integrated()) {
1333 pr_info("No ESR for 82489DX.\n");
1337 if (apic->disable_esr) {
1339 * Something untraceable is creating bad interrupts on
1340 * secondary quads ... for the moment, just leave the
1341 * ESR disabled - we can't do anything useful with the
1342 * errors anyway - mbligh
1344 pr_info("Leaving ESR disabled.\n");
1348 maxlvt = lapic_get_maxlvt();
1349 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1350 apic_write(APIC_ESR, 0);
1351 oldvalue = apic_read(APIC_ESR);
1353 /* enables sending errors */
1354 value = ERROR_APIC_VECTOR;
1355 apic_write(APIC_LVTERR, value);
1358 * spec says clear errors after enabling vector.
1361 apic_write(APIC_ESR, 0);
1362 value = apic_read(APIC_ESR);
1363 if (value != oldvalue)
1364 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1365 "vector: 0x%08x after: 0x%08x\n",
1369 static void apic_pending_intr_clear(void)
1371 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1372 unsigned long long tsc = 0, ntsc;
1373 unsigned int value, queued;
1374 int i, j, acked = 0;
1376 if (boot_cpu_has(X86_FEATURE_TSC))
1379 * After a crash, we no longer service the interrupts and a pending
1380 * interrupt from previous kernel might still have ISR bit set.
1382 * Most probably by now CPU has serviced that pending interrupt and
1383 * it might not have done the ack_APIC_irq() because it thought,
1384 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1385 * does not clear the ISR bit and cpu thinks it has already serivced
1386 * the interrupt. Hence a vector might get locked. It was noticed
1387 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1391 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1392 queued |= apic_read(APIC_IRR + i*0x10);
1394 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1395 value = apic_read(APIC_ISR + i*0x10);
1396 for (j = 31; j >= 0; j--) {
1397 if (value & (1<<j)) {
1404 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1409 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1411 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1415 } while (queued && max_loops > 0);
1416 WARN_ON(max_loops <= 0);
1420 * setup_local_APIC - setup the local APIC
1422 * Used to setup local APIC while initializing BSP or bringing up APs.
1423 * Always called with preemption disabled.
1425 void setup_local_APIC(void)
1427 int cpu = smp_processor_id();
1432 disable_ioapic_support();
1437 * If this comes from kexec/kcrash the APIC might be enabled in
1438 * SPIV. Soft disable it before doing further initialization.
1440 value = apic_read(APIC_SPIV);
1441 value &= ~APIC_SPIV_APIC_ENABLED;
1442 apic_write(APIC_SPIV, value);
1444 #ifdef CONFIG_X86_32
1445 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1446 if (lapic_is_integrated() && apic->disable_esr) {
1447 apic_write(APIC_ESR, 0);
1448 apic_write(APIC_ESR, 0);
1449 apic_write(APIC_ESR, 0);
1450 apic_write(APIC_ESR, 0);
1453 perf_events_lapic_init();
1456 * Double-check whether this APIC is really registered.
1457 * This is meaningless in clustered apic mode, so we skip it.
1459 BUG_ON(!apic->apic_id_registered());
1462 * Intel recommends to set DFR, LDR and TPR before enabling
1463 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1464 * document number 292116). So here it goes...
1466 apic->init_apic_ldr();
1468 #ifdef CONFIG_X86_32
1469 if (apic->dest_logical) {
1470 int logical_apicid, ldr_apicid;
1473 * APIC LDR is initialized. If logical_apicid mapping was
1474 * initialized during get_smp_config(), make sure it matches
1477 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1478 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1479 if (logical_apicid != BAD_APICID)
1480 WARN_ON(logical_apicid != ldr_apicid);
1481 /* Always use the value from LDR. */
1482 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1487 * Set Task Priority to 'accept all'. We never change this
1490 value = apic_read(APIC_TASKPRI);
1491 value &= ~APIC_TPRI_MASK;
1492 apic_write(APIC_TASKPRI, value);
1494 apic_pending_intr_clear();
1497 * Now that we are all set up, enable the APIC
1499 value = apic_read(APIC_SPIV);
1500 value &= ~APIC_VECTOR_MASK;
1504 value |= APIC_SPIV_APIC_ENABLED;
1506 #ifdef CONFIG_X86_32
1508 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1509 * certain networking cards. If high frequency interrupts are
1510 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1511 * entry is masked/unmasked at a high rate as well then sooner or
1512 * later IOAPIC line gets 'stuck', no more interrupts are received
1513 * from the device. If focus CPU is disabled then the hang goes
1516 * [ This bug can be reproduced easily with a level-triggered
1517 * PCI Ne2000 networking cards and PII/PIII processors, dual
1521 * Actually disabling the focus CPU check just makes the hang less
1522 * frequent as it makes the interrupt distributon model be more
1523 * like LRU than MRU (the short-term load is more even across CPUs).
1527 * - enable focus processor (bit==0)
1528 * - 64bit mode always use processor focus
1529 * so no need to set it
1531 value &= ~APIC_SPIV_FOCUS_DISABLED;
1535 * Set spurious IRQ vector
1537 value |= SPURIOUS_APIC_VECTOR;
1538 apic_write(APIC_SPIV, value);
1541 * Set up LVT0, LVT1:
1543 * set up through-local-APIC on the BP's LINT0. This is not
1544 * strictly necessary in pure symmetric-IO mode, but sometimes
1545 * we delegate interrupts to the 8259A.
1548 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1550 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1551 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1552 value = APIC_DM_EXTINT;
1553 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1555 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1556 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1558 apic_write(APIC_LVT0, value);
1561 * Only the BSP sees the LINT1 NMI signal by default. This can be
1562 * modified by apic_extnmi= boot option.
1564 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1565 apic_extnmi == APIC_EXTNMI_ALL)
1566 value = APIC_DM_NMI;
1568 value = APIC_DM_NMI | APIC_LVT_MASKED;
1569 if (!lapic_is_integrated()) /* 82489DX */
1570 value |= APIC_LVT_LEVEL_TRIGGER;
1571 apic_write(APIC_LVT1, value);
1573 #ifdef CONFIG_X86_MCE_INTEL
1574 /* Recheck CMCI information after local APIC is up on CPU #0 */
1580 static void end_local_APIC_setup(void)
1584 #ifdef CONFIG_X86_32
1587 /* Disable the local apic timer */
1588 value = apic_read(APIC_LVTT);
1589 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1590 apic_write(APIC_LVTT, value);
1598 * APIC setup function for application processors. Called from smpboot.c
1600 void apic_ap_setup(void)
1603 end_local_APIC_setup();
1606 #ifdef CONFIG_X86_X2APIC
1614 static int x2apic_state;
1616 static void __x2apic_disable(void)
1620 if (!boot_cpu_has(X86_FEATURE_APIC))
1623 rdmsrl(MSR_IA32_APICBASE, msr);
1624 if (!(msr & X2APIC_ENABLE))
1626 /* Disable xapic and x2apic first and then reenable xapic mode */
1627 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1628 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1629 printk_once(KERN_INFO "x2apic disabled\n");
1632 static void __x2apic_enable(void)
1636 rdmsrl(MSR_IA32_APICBASE, msr);
1637 if (msr & X2APIC_ENABLE)
1639 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1640 printk_once(KERN_INFO "x2apic enabled\n");
1643 static int __init setup_nox2apic(char *str)
1645 if (x2apic_enabled()) {
1646 int apicid = native_apic_msr_read(APIC_ID);
1648 if (apicid >= 255) {
1649 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1653 pr_warning("x2apic already enabled.\n");
1656 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1657 x2apic_state = X2APIC_DISABLED;
1661 early_param("nox2apic", setup_nox2apic);
1663 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1664 void x2apic_setup(void)
1667 * If x2apic is not in ON state, disable it if already enabled
1670 if (x2apic_state != X2APIC_ON) {
1677 static __init void x2apic_disable(void)
1679 u32 x2apic_id, state = x2apic_state;
1682 x2apic_state = X2APIC_DISABLED;
1684 if (state != X2APIC_ON)
1687 x2apic_id = read_apic_id();
1688 if (x2apic_id >= 255)
1689 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1692 register_lapic_address(mp_lapic_addr);
1695 static __init void x2apic_enable(void)
1697 if (x2apic_state != X2APIC_OFF)
1701 x2apic_state = X2APIC_ON;
1705 static __init void try_to_enable_x2apic(int remap_mode)
1707 if (x2apic_state == X2APIC_DISABLED)
1710 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1711 /* IR is required if there is APIC ID > 255 even when running
1714 if (max_physical_apicid > 255 ||
1715 !x86_init.hyper.x2apic_available()) {
1716 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1722 * without IR all CPUs can be addressed by IOAPIC/MSI
1723 * only in physical mode
1730 void __init check_x2apic(void)
1732 if (x2apic_enabled()) {
1733 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1735 x2apic_state = X2APIC_ON;
1736 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1737 x2apic_state = X2APIC_DISABLED;
1740 #else /* CONFIG_X86_X2APIC */
1741 static int __init validate_x2apic(void)
1743 if (!apic_is_x2apic_enabled())
1746 * Checkme: Can we simply turn off x2apic here instead of panic?
1748 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1750 early_initcall(validate_x2apic);
1752 static inline void try_to_enable_x2apic(int remap_mode) { }
1753 static inline void __x2apic_enable(void) { }
1754 #endif /* !CONFIG_X86_X2APIC */
1756 void __init enable_IR_x2apic(void)
1758 unsigned long flags;
1761 if (skip_ioapic_setup) {
1762 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1766 ir_stat = irq_remapping_prepare();
1767 if (ir_stat < 0 && !x2apic_supported())
1770 ret = save_ioapic_entries();
1772 pr_info("Saving IO-APIC state failed: %d\n", ret);
1776 local_irq_save(flags);
1777 legacy_pic->mask_all();
1778 mask_ioapic_entries();
1780 /* If irq_remapping_prepare() succeeded, try to enable it */
1782 ir_stat = irq_remapping_enable();
1783 /* ir_stat contains the remap mode or an error code */
1784 try_to_enable_x2apic(ir_stat);
1787 restore_ioapic_entries();
1788 legacy_pic->restore_mask();
1789 local_irq_restore(flags);
1792 #ifdef CONFIG_X86_64
1794 * Detect and enable local APICs on non-SMP boards.
1795 * Original code written by Keir Fraser.
1796 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1797 * not correctly set up (usually the APIC timer won't work etc.)
1799 static int __init detect_init_APIC(void)
1801 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1802 pr_info("No local APIC present\n");
1806 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1811 static int __init apic_verify(void)
1816 * The APIC feature bit should now be enabled
1819 features = cpuid_edx(1);
1820 if (!(features & (1 << X86_FEATURE_APIC))) {
1821 pr_warning("Could not enable APIC!\n");
1824 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1825 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1827 /* The BIOS may have set up the APIC at some other address */
1828 if (boot_cpu_data.x86 >= 6) {
1829 rdmsr(MSR_IA32_APICBASE, l, h);
1830 if (l & MSR_IA32_APICBASE_ENABLE)
1831 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1834 pr_info("Found and enabled local APIC!\n");
1838 int __init apic_force_enable(unsigned long addr)
1846 * Some BIOSes disable the local APIC in the APIC_BASE
1847 * MSR. This can only be done in software for Intel P6 or later
1848 * and AMD K7 (Model > 1) or later.
1850 if (boot_cpu_data.x86 >= 6) {
1851 rdmsr(MSR_IA32_APICBASE, l, h);
1852 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1853 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1854 l &= ~MSR_IA32_APICBASE_BASE;
1855 l |= MSR_IA32_APICBASE_ENABLE | addr;
1856 wrmsr(MSR_IA32_APICBASE, l, h);
1857 enabled_via_apicbase = 1;
1860 return apic_verify();
1864 * Detect and initialize APIC
1866 static int __init detect_init_APIC(void)
1868 /* Disabled by kernel option? */
1872 switch (boot_cpu_data.x86_vendor) {
1873 case X86_VENDOR_AMD:
1874 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1875 (boot_cpu_data.x86 >= 15))
1878 case X86_VENDOR_INTEL:
1879 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1880 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1887 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1889 * Over-ride BIOS and try to enable the local APIC only if
1890 * "lapic" specified.
1892 if (!force_enable_local_apic) {
1893 pr_info("Local APIC disabled by BIOS -- "
1894 "you can enable it with \"lapic\"\n");
1897 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1909 pr_info("No local APIC present or hardware disabled\n");
1915 * init_apic_mappings - initialize APIC mappings
1917 void __init init_apic_mappings(void)
1919 unsigned int new_apicid;
1921 if (apic_validate_deadline_timer())
1922 pr_info("TSC deadline timer available\n");
1925 boot_cpu_physical_apicid = read_apic_id();
1929 /* If no local APIC can be found return early */
1930 if (!smp_found_config && detect_init_APIC()) {
1931 /* lets NOP'ify apic operations */
1932 pr_info("APIC: disable apic facility\n");
1935 apic_phys = mp_lapic_addr;
1938 * If the system has ACPI MADT tables or MP info, the LAPIC
1939 * address is already registered.
1941 if (!acpi_lapic && !smp_found_config)
1942 register_lapic_address(apic_phys);
1946 * Fetch the APIC ID of the BSP in case we have a
1947 * default configuration (or the MP table is broken).
1949 new_apicid = read_apic_id();
1950 if (boot_cpu_physical_apicid != new_apicid) {
1951 boot_cpu_physical_apicid = new_apicid;
1953 * yeah -- we lie about apic_version
1954 * in case if apic was disabled via boot option
1955 * but it's not a problem for SMP compiled kernel
1956 * since smp_sanity_check is prepared for such a case
1957 * and disable smp mode
1959 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1963 void __init register_lapic_address(unsigned long address)
1965 mp_lapic_addr = address;
1968 set_fixmap_nocache(FIX_APIC_BASE, address);
1969 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1970 APIC_BASE, address);
1972 if (boot_cpu_physical_apicid == -1U) {
1973 boot_cpu_physical_apicid = read_apic_id();
1974 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1979 * Local APIC interrupts
1983 * This interrupt should _never_ happen with our APIC/SMP architecture
1985 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1987 u8 vector = ~regs->orig_ax;
1991 trace_spurious_apic_entry(vector);
1994 * Check if this really is a spurious interrupt and ACK it
1995 * if it is a vectored one. Just in case...
1996 * Spurious interrupts should not be ACKed.
1998 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1999 if (v & (1 << (vector & 0x1f)))
2002 inc_irq_stat(irq_spurious_count);
2004 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
2005 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
2006 "should never happen.\n", vector, smp_processor_id());
2008 trace_spurious_apic_exit(vector);
2013 * This interrupt should never happen with our APIC/SMP architecture
2015 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2017 static const char * const error_interrupt_reason[] = {
2018 "Send CS error", /* APIC Error Bit 0 */
2019 "Receive CS error", /* APIC Error Bit 1 */
2020 "Send accept error", /* APIC Error Bit 2 */
2021 "Receive accept error", /* APIC Error Bit 3 */
2022 "Redirectable IPI", /* APIC Error Bit 4 */
2023 "Send illegal vector", /* APIC Error Bit 5 */
2024 "Received illegal vector", /* APIC Error Bit 6 */
2025 "Illegal register address", /* APIC Error Bit 7 */
2030 trace_error_apic_entry(ERROR_APIC_VECTOR);
2032 /* First tickle the hardware, only then report what went on. -- REW */
2033 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2034 apic_write(APIC_ESR, 0);
2035 v = apic_read(APIC_ESR);
2037 atomic_inc(&irq_err_count);
2039 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2040 smp_processor_id(), v);
2045 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2050 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2052 trace_error_apic_exit(ERROR_APIC_VECTOR);
2057 * connect_bsp_APIC - attach the APIC to the interrupt system
2059 static void __init connect_bsp_APIC(void)
2061 #ifdef CONFIG_X86_32
2064 * Do not trust the local APIC being empty at bootup.
2068 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2069 * local APIC to INT and NMI lines.
2071 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2072 "enabling APIC mode.\n");
2079 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2080 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2082 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2085 void disconnect_bsp_APIC(int virt_wire_setup)
2089 #ifdef CONFIG_X86_32
2092 * Put the board back into PIC mode (has an effect only on
2093 * certain older boards). Note that APIC interrupts, including
2094 * IPIs, won't work beyond this point! The only exception are
2097 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2098 "entering PIC mode.\n");
2104 /* Go back to Virtual Wire compatibility mode */
2106 /* For the spurious interrupt use vector F, and enable it */
2107 value = apic_read(APIC_SPIV);
2108 value &= ~APIC_VECTOR_MASK;
2109 value |= APIC_SPIV_APIC_ENABLED;
2111 apic_write(APIC_SPIV, value);
2113 if (!virt_wire_setup) {
2115 * For LVT0 make it edge triggered, active high,
2116 * external and enabled
2118 value = apic_read(APIC_LVT0);
2119 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2120 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2121 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2122 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2123 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2124 apic_write(APIC_LVT0, value);
2127 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2131 * For LVT1 make it edge triggered, active high,
2134 value = apic_read(APIC_LVT1);
2135 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2136 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2137 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2138 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2139 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2140 apic_write(APIC_LVT1, value);
2144 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2145 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2146 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2147 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2149 * NOTE: Reserve 0 for BSP.
2151 static int nr_logical_cpuids = 1;
2154 * Used to store mapping between logical CPU IDs and APIC IDs.
2156 static int cpuid_to_apicid[] = {
2157 [0 ... NR_CPUS - 1] = -1,
2162 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2163 * @id: APIC ID to check
2165 bool apic_id_is_primary_thread(unsigned int apicid)
2169 if (smp_num_siblings == 1)
2171 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2172 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2173 return !(apicid & mask);
2178 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2179 * and cpuid_to_apicid[] synchronized.
2181 static int allocate_logical_cpuid(int apicid)
2186 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2187 * check if the kernel has allocated a cpuid for it.
2189 for (i = 0; i < nr_logical_cpuids; i++) {
2190 if (cpuid_to_apicid[i] == apicid)
2194 /* Allocate a new cpuid. */
2195 if (nr_logical_cpuids >= nr_cpu_ids) {
2196 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2197 "Processor %d/0x%x and the rest are ignored.\n",
2198 nr_cpu_ids, nr_logical_cpuids, apicid);
2202 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2203 return nr_logical_cpuids++;
2206 int generic_processor_info(int apicid, int version)
2208 int cpu, max = nr_cpu_ids;
2209 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2210 phys_cpu_present_map);
2213 * boot_cpu_physical_apicid is designed to have the apicid
2214 * returned by read_apic_id(), i.e, the apicid of the
2215 * currently booting-up processor. However, on some platforms,
2216 * it is temporarily modified by the apicid reported as BSP
2217 * through MP table. Concretely:
2219 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2220 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2222 * This function is executed with the modified
2223 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2224 * parameter doesn't work to disable APs on kdump 2nd kernel.
2226 * Since fixing handling of boot_cpu_physical_apicid requires
2227 * another discussion and tests on each platform, we leave it
2228 * for now and here we use read_apic_id() directly in this
2229 * function, generic_processor_info().
2231 if (disabled_cpu_apicid != BAD_APICID &&
2232 disabled_cpu_apicid != read_apic_id() &&
2233 disabled_cpu_apicid == apicid) {
2234 int thiscpu = num_processors + disabled_cpus;
2236 pr_warning("APIC: Disabling requested cpu."
2237 " Processor %d/0x%x ignored.\n",
2245 * If boot cpu has not been detected yet, then only allow upto
2246 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2248 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2249 apicid != boot_cpu_physical_apicid) {
2250 int thiscpu = max + disabled_cpus - 1;
2253 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2254 " reached. Keeping one slot for boot cpu."
2255 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2261 if (num_processors >= nr_cpu_ids) {
2262 int thiscpu = max + disabled_cpus;
2264 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2265 "reached. Processor %d/0x%x ignored.\n",
2266 max, thiscpu, apicid);
2272 if (apicid == boot_cpu_physical_apicid) {
2274 * x86_bios_cpu_apicid is required to have processors listed
2275 * in same order as logical cpu numbers. Hence the first
2276 * entry is BSP, and so on.
2277 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2282 /* Logical cpuid 0 is reserved for BSP. */
2283 cpuid_to_apicid[0] = apicid;
2285 cpu = allocate_logical_cpuid(apicid);
2295 if (version == 0x0) {
2296 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2301 if (version != boot_cpu_apic_version) {
2302 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2303 boot_cpu_apic_version, cpu, version);
2306 if (apicid > max_physical_apicid)
2307 max_physical_apicid = apicid;
2309 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2310 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2311 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2313 #ifdef CONFIG_X86_32
2314 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2315 apic->x86_32_early_logical_apicid(cpu);
2317 set_cpu_possible(cpu, true);
2318 physid_set(apicid, phys_cpu_present_map);
2319 set_cpu_present(cpu, true);
2325 int hard_smp_processor_id(void)
2327 return read_apic_id();
2330 void default_init_apic_ldr(void)
2334 apic_write(APIC_DFR, APIC_DFR_VALUE);
2335 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2336 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2337 apic_write(APIC_LDR, val);
2340 int default_cpu_mask_to_apicid(const struct cpumask *mask,
2341 struct irq_data *irqdata,
2342 unsigned int *apicid)
2344 unsigned int cpu = cpumask_first(mask);
2346 if (cpu >= nr_cpu_ids)
2348 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2349 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2353 int flat_cpu_mask_to_apicid(const struct cpumask *mask,
2354 struct irq_data *irqdata,
2355 unsigned int *apicid)
2358 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2359 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2363 *apicid = (unsigned int)cpu_mask;
2364 cpumask_bits(effmsk)[0] = cpu_mask;
2369 * Override the generic EOI implementation with an optimized version.
2370 * Only called during early boot when only one CPU is active and with
2371 * interrupts disabled, so we know this does not race with actual APIC driver
2374 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2378 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2379 /* Should happen once for each apic */
2380 WARN_ON((*drv)->eoi_write == eoi_write);
2381 (*drv)->native_eoi_write = (*drv)->eoi_write;
2382 (*drv)->eoi_write = eoi_write;
2386 static void __init apic_bsp_up_setup(void)
2388 #ifdef CONFIG_X86_64
2389 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2392 * Hack: In case of kdump, after a crash, kernel might be booting
2393 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2394 * might be zero if read from MP tables. Get it from LAPIC.
2396 # ifdef CONFIG_CRASH_DUMP
2397 boot_cpu_physical_apicid = read_apic_id();
2400 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2404 * apic_bsp_setup - Setup function for local apic and io-apic
2405 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2408 * apic_id of BSP APIC
2410 int __init apic_bsp_setup(bool upmode)
2416 apic_bsp_up_setup();
2420 id = apic_read(APIC_LDR);
2422 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2425 end_local_APIC_setup();
2426 irq_remap_enable_fault_handling();
2428 /* Setup local timer */
2429 x86_init.timers.setup_percpu_clockev();
2434 * This initializes the IO-APIC and APIC hardware if this is
2437 int __init APIC_init_uniprocessor(void)
2440 pr_info("Apic disabled\n");
2443 #ifdef CONFIG_X86_64
2444 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2446 pr_info("Apic disabled by BIOS\n");
2450 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2454 * Complain if the BIOS pretends there is one.
2456 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2457 APIC_INTEGRATED(boot_cpu_apic_version)) {
2458 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2459 boot_cpu_physical_apicid);
2464 if (!smp_found_config)
2465 disable_ioapic_support();
2467 default_setup_apic_routing();
2468 apic_bsp_setup(true);
2472 #ifdef CONFIG_UP_LATE_INIT
2473 void __init up_late_init(void)
2475 APIC_init_uniprocessor();
2486 * 'active' is true if the local APIC was enabled by us and
2487 * not the BIOS; this signifies that we are also responsible
2488 * for disabling it before entering apm/acpi suspend
2491 /* r/w apic fields */
2492 unsigned int apic_id;
2493 unsigned int apic_taskpri;
2494 unsigned int apic_ldr;
2495 unsigned int apic_dfr;
2496 unsigned int apic_spiv;
2497 unsigned int apic_lvtt;
2498 unsigned int apic_lvtpc;
2499 unsigned int apic_lvt0;
2500 unsigned int apic_lvt1;
2501 unsigned int apic_lvterr;
2502 unsigned int apic_tmict;
2503 unsigned int apic_tdcr;
2504 unsigned int apic_thmr;
2505 unsigned int apic_cmci;
2508 static int lapic_suspend(void)
2510 unsigned long flags;
2513 if (!apic_pm_state.active)
2516 maxlvt = lapic_get_maxlvt();
2518 apic_pm_state.apic_id = apic_read(APIC_ID);
2519 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2520 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2521 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2522 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2523 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2525 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2526 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2527 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2528 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2529 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2530 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2531 #ifdef CONFIG_X86_THERMAL_VECTOR
2533 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2535 #ifdef CONFIG_X86_MCE_INTEL
2537 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2540 local_irq_save(flags);
2541 disable_local_APIC();
2543 irq_remapping_disable();
2545 local_irq_restore(flags);
2549 static void lapic_resume(void)
2552 unsigned long flags;
2555 if (!apic_pm_state.active)
2558 local_irq_save(flags);
2561 * IO-APIC and PIC have their own resume routines.
2562 * We just mask them here to make sure the interrupt
2563 * subsystem is completely quiet while we enable x2apic
2564 * and interrupt-remapping.
2566 mask_ioapic_entries();
2567 legacy_pic->mask_all();
2573 * Make sure the APICBASE points to the right address
2575 * FIXME! This will be wrong if we ever support suspend on
2576 * SMP! We'll need to do this as part of the CPU restore!
2578 if (boot_cpu_data.x86 >= 6) {
2579 rdmsr(MSR_IA32_APICBASE, l, h);
2580 l &= ~MSR_IA32_APICBASE_BASE;
2581 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2582 wrmsr(MSR_IA32_APICBASE, l, h);
2586 maxlvt = lapic_get_maxlvt();
2587 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2588 apic_write(APIC_ID, apic_pm_state.apic_id);
2589 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2590 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2591 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2592 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2593 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2594 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2595 #ifdef CONFIG_X86_THERMAL_VECTOR
2597 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2599 #ifdef CONFIG_X86_MCE_INTEL
2601 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2604 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2605 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2606 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2607 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2608 apic_write(APIC_ESR, 0);
2609 apic_read(APIC_ESR);
2610 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2611 apic_write(APIC_ESR, 0);
2612 apic_read(APIC_ESR);
2614 irq_remapping_reenable(x2apic_mode);
2616 local_irq_restore(flags);
2620 * This device has no shutdown method - fully functioning local APICs
2621 * are needed on every CPU up until machine_halt/restart/poweroff.
2624 static struct syscore_ops lapic_syscore_ops = {
2625 .resume = lapic_resume,
2626 .suspend = lapic_suspend,
2629 static void apic_pm_activate(void)
2631 apic_pm_state.active = 1;
2634 static int __init init_lapic_sysfs(void)
2636 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2637 if (boot_cpu_has(X86_FEATURE_APIC))
2638 register_syscore_ops(&lapic_syscore_ops);
2643 /* local apic needs to resume before other devices access its registers. */
2644 core_initcall(init_lapic_sysfs);
2646 #else /* CONFIG_PM */
2648 static void apic_pm_activate(void) { }
2650 #endif /* CONFIG_PM */
2652 #ifdef CONFIG_X86_64
2654 static int multi_checked;
2657 static int set_multi(const struct dmi_system_id *d)
2661 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2666 static const struct dmi_system_id multi_dmi_table[] = {
2668 .callback = set_multi,
2669 .ident = "IBM System Summit2",
2671 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2672 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2678 static void dmi_check_multi(void)
2683 dmi_check_system(multi_dmi_table);
2688 * apic_is_clustered_box() -- Check if we can expect good TSC
2690 * Thus far, the major user of this is IBM's Summit2 series:
2691 * Clustered boxes may have unsynced TSC problems if they are
2693 * Use DMI to check them
2695 int apic_is_clustered_box(void)
2703 * APIC command line parameters
2705 static int __init setup_disableapic(char *arg)
2708 setup_clear_cpu_cap(X86_FEATURE_APIC);
2711 early_param("disableapic", setup_disableapic);
2713 /* same as disableapic, for compatibility */
2714 static int __init setup_nolapic(char *arg)
2716 return setup_disableapic(arg);
2718 early_param("nolapic", setup_nolapic);
2720 static int __init parse_lapic_timer_c2_ok(char *arg)
2722 local_apic_timer_c2_ok = 1;
2725 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2727 static int __init parse_disable_apic_timer(char *arg)
2729 disable_apic_timer = 1;
2732 early_param("noapictimer", parse_disable_apic_timer);
2734 static int __init parse_nolapic_timer(char *arg)
2736 disable_apic_timer = 1;
2739 early_param("nolapic_timer", parse_nolapic_timer);
2741 static int __init apic_set_verbosity(char *arg)
2744 #ifdef CONFIG_X86_64
2745 skip_ioapic_setup = 0;
2751 if (strcmp("debug", arg) == 0)
2752 apic_verbosity = APIC_DEBUG;
2753 else if (strcmp("verbose", arg) == 0)
2754 apic_verbosity = APIC_VERBOSE;
2756 pr_warning("APIC Verbosity level %s not recognised"
2757 " use apic=verbose or apic=debug\n", arg);
2763 early_param("apic", apic_set_verbosity);
2765 static int __init lapic_insert_resource(void)
2770 /* Put local APIC into the resource map. */
2771 lapic_resource.start = apic_phys;
2772 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2773 insert_resource(&iomem_resource, &lapic_resource);
2779 * need call insert after e820__reserve_resources()
2780 * that is using request_resource
2782 late_initcall(lapic_insert_resource);
2784 static int __init apic_set_disabled_cpu_apicid(char *arg)
2786 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2791 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2793 static int __init apic_set_extnmi(char *arg)
2798 if (!strncmp("all", arg, 3))
2799 apic_extnmi = APIC_EXTNMI_ALL;
2800 else if (!strncmp("none", arg, 4))
2801 apic_extnmi = APIC_EXTNMI_NONE;
2802 else if (!strncmp("bsp", arg, 3))
2803 apic_extnmi = APIC_EXTNMI_BSP;
2805 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2811 early_param("apic_extnmi", apic_set_extnmi);