2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/iopoll.h>
32 #include <asm/pci-direct.h>
33 #include <asm/iommu.h>
35 #include <asm/x86_init.h>
36 #include <asm/iommu_table.h>
37 #include <asm/io_apic.h>
38 #include <asm/irq_remapping.h>
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
42 #include "irq_remapping.h"
45 * definitions for the ACPI scanning code
47 #define IVRS_HEADER_LENGTH 48
49 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
50 #define ACPI_IVMD_TYPE_ALL 0x20
51 #define ACPI_IVMD_TYPE 0x21
52 #define ACPI_IVMD_TYPE_RANGE 0x22
54 #define IVHD_DEV_ALL 0x01
55 #define IVHD_DEV_SELECT 0x02
56 #define IVHD_DEV_SELECT_RANGE_START 0x03
57 #define IVHD_DEV_RANGE_END 0x04
58 #define IVHD_DEV_ALIAS 0x42
59 #define IVHD_DEV_ALIAS_RANGE 0x43
60 #define IVHD_DEV_EXT_SELECT 0x46
61 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
62 #define IVHD_DEV_SPECIAL 0x48
63 #define IVHD_DEV_ACPI_HID 0xf0
65 #define UID_NOT_PRESENT 0
66 #define UID_IS_INTEGER 1
67 #define UID_IS_CHARACTER 2
69 #define IVHD_SPECIAL_IOAPIC 1
70 #define IVHD_SPECIAL_HPET 2
72 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
73 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
74 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
75 #define IVHD_FLAG_ISOC_EN_MASK 0x08
77 #define IVMD_FLAG_EXCL_RANGE 0x08
78 #define IVMD_FLAG_UNITY_MAP 0x01
80 #define ACPI_DEVFLAG_INITPASS 0x01
81 #define ACPI_DEVFLAG_EXTINT 0x02
82 #define ACPI_DEVFLAG_NMI 0x04
83 #define ACPI_DEVFLAG_SYSMGT1 0x10
84 #define ACPI_DEVFLAG_SYSMGT2 0x20
85 #define ACPI_DEVFLAG_LINT0 0x40
86 #define ACPI_DEVFLAG_LINT1 0x80
87 #define ACPI_DEVFLAG_ATSDIS 0x10000000
89 #define LOOP_TIMEOUT 2000000
91 * ACPI table definitions
93 * These data structures are laid over the table to parse the important values
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
99 * or more ivhd_entrys.
112 /* Following only valid on IVHD type 11h and 40h */
113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
115 } __attribute__((packed));
118 * A device entry describing which devices a specific IOMMU translates and
119 * which requestor ids they use.
131 } __attribute__((packed));
134 * An AMD IOMMU memory definition structure. It defines things like exclusion
135 * ranges for devices and regions that should be unity mapped.
146 } __attribute__((packed));
149 bool amd_iommu_irq_remap __read_mostly;
151 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153 static bool amd_iommu_detected;
154 static bool __initdata amd_iommu_disabled;
155 static int amd_iommu_target_ivhd_type;
157 u16 amd_iommu_last_bdf; /* largest PCI device id we have
159 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
161 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
163 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
166 /* Array to assign indices to IOMMUs*/
167 struct amd_iommu *amd_iommus[MAX_IOMMUS];
168 int amd_iommus_present;
170 /* IOMMUs have a non-present cache? */
171 bool amd_iommu_np_cache __read_mostly;
172 bool amd_iommu_iotlb_sup __read_mostly = true;
174 u32 amd_iommu_max_pasid __read_mostly = ~0;
176 bool amd_iommu_v2_present __read_mostly;
177 static bool amd_iommu_pc_present __read_mostly;
179 bool amd_iommu_force_isolation __read_mostly;
182 * List of protection domains - used during resume
184 LIST_HEAD(amd_iommu_pd_list);
185 spinlock_t amd_iommu_pd_lock;
188 * Pointer to the device table which is shared by all AMD IOMMUs
189 * it is indexed by the PCI device id or the HT unit id and contains
190 * information about the domain the device belongs to as well as the
191 * page table root pointer.
193 struct dev_table_entry *amd_iommu_dev_table;
196 * The alias table is a driver specific data structure which contains the
197 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
198 * More than one device can share the same requestor id.
200 u16 *amd_iommu_alias_table;
203 * The rlookup table is used to find the IOMMU which is responsible
204 * for a specific device. It is also indexed by the PCI device id.
206 struct amd_iommu **amd_iommu_rlookup_table;
209 * This table is used to find the irq remapping table for a given device id
212 struct irq_remap_table **irq_lookup_table;
215 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
216 * to know which ones are already in use.
218 unsigned long *amd_iommu_pd_alloc_bitmap;
220 static u32 dev_table_size; /* size of the device table */
221 static u32 alias_table_size; /* size of the alias table */
222 static u32 rlookup_table_size; /* size if the rlookup table */
224 enum iommu_init_state {
237 /* Early ioapic and hpet maps from kernel command line */
238 #define EARLY_MAP_SIZE 4
239 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
240 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
241 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
243 static int __initdata early_ioapic_map_size;
244 static int __initdata early_hpet_map_size;
245 static int __initdata early_acpihid_map_size;
247 static bool __initdata cmdline_maps;
249 static enum iommu_init_state init_state = IOMMU_START_STATE;
251 static int amd_iommu_enable_interrupts(void);
252 static int __init iommu_go_to_state(enum iommu_init_state state);
253 static void init_device_table_dma(void);
255 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
256 u8 bank, u8 cntr, u8 fxn,
257 u64 *value, bool is_write);
259 static inline void update_last_devid(u16 devid)
261 if (devid > amd_iommu_last_bdf)
262 amd_iommu_last_bdf = devid;
265 static inline unsigned long tbl_size(int entry_size)
267 unsigned shift = PAGE_SHIFT +
268 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
273 /* Access to l1 and l2 indexed register spaces */
275 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
279 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
280 pci_read_config_dword(iommu->dev, 0xfc, &val);
284 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
286 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
287 pci_write_config_dword(iommu->dev, 0xfc, val);
288 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
291 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
295 pci_write_config_dword(iommu->dev, 0xf0, address);
296 pci_read_config_dword(iommu->dev, 0xf4, &val);
300 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
302 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
303 pci_write_config_dword(iommu->dev, 0xf4, val);
306 /****************************************************************************
308 * AMD IOMMU MMIO register space handling functions
310 * These functions are used to program the IOMMU device registers in
311 * MMIO space required for that driver.
313 ****************************************************************************/
316 * This function set the exclusion range in the IOMMU. DMA accesses to the
317 * exclusion range are passed through untranslated
319 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
321 u64 start = iommu->exclusion_start & PAGE_MASK;
322 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
325 if (!iommu->exclusion_start)
328 entry = start | MMIO_EXCL_ENABLE_MASK;
329 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
330 &entry, sizeof(entry));
333 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
334 &entry, sizeof(entry));
337 /* Programs the physical address of the device table into the IOMMU hardware */
338 static void iommu_set_device_table(struct amd_iommu *iommu)
342 BUG_ON(iommu->mmio_base == NULL);
344 entry = virt_to_phys(amd_iommu_dev_table);
345 entry |= (dev_table_size >> 12) - 1;
346 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
347 &entry, sizeof(entry));
350 /* Generic functions to enable/disable certain features of the IOMMU. */
351 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
355 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
357 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
360 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
364 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
366 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
369 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
373 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
374 ctrl &= ~CTRL_INV_TO_MASK;
375 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
376 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
379 /* Function to enable the hardware */
380 static void iommu_enable(struct amd_iommu *iommu)
382 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
385 static void iommu_disable(struct amd_iommu *iommu)
387 if (!iommu->mmio_base)
390 /* Disable command buffer */
391 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
393 /* Disable event logging and event interrupts */
394 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
395 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
397 /* Disable IOMMU GA_LOG */
398 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
399 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
401 /* Disable IOMMU hardware itself */
402 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
406 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
407 * the system has one.
409 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
411 if (!request_mem_region(address, end, "amd_iommu")) {
412 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
414 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
418 return (u8 __iomem *)ioremap_nocache(address, end);
421 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
423 if (iommu->mmio_base)
424 iounmap(iommu->mmio_base);
425 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
428 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
444 /****************************************************************************
446 * The functions below belong to the first pass of AMD IOMMU ACPI table
447 * parsing. In this pass we try to find out the highest device id this
448 * code has to handle. Upon this information the size of the shared data
449 * structures is determined later.
451 ****************************************************************************/
454 * This function calculates the length of a given IVHD entry
456 static inline int ivhd_entry_length(u8 *ivhd)
458 u32 type = ((struct ivhd_entry *)ivhd)->type;
461 return 0x04 << (*ivhd >> 6);
462 } else if (type == IVHD_DEV_ACPI_HID) {
463 /* For ACPI_HID, offset 21 is uid len */
464 return *((u8 *)ivhd + 21) + 22;
470 * After reading the highest device id from the IOMMU PCI capability header
471 * this function looks if there is a higher device id defined in the ACPI table
473 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
475 u8 *p = (void *)h, *end = (void *)h;
476 struct ivhd_entry *dev;
478 u32 ivhd_size = get_ivhd_header_size(h);
481 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
489 dev = (struct ivhd_entry *)p;
492 /* Use maximum BDF value for DEV_ALL */
493 update_last_devid(0xffff);
495 case IVHD_DEV_SELECT:
496 case IVHD_DEV_RANGE_END:
498 case IVHD_DEV_EXT_SELECT:
499 /* all the above subfield types refer to device ids */
500 update_last_devid(dev->devid);
505 p += ivhd_entry_length(p);
513 static int __init check_ivrs_checksum(struct acpi_table_header *table)
516 u8 checksum = 0, *p = (u8 *)table;
518 for (i = 0; i < table->length; ++i)
521 /* ACPI table corrupt */
522 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
530 * Iterate over all IVHD entries in the ACPI table and find the highest device
531 * id which we need to handle. This is the first of three functions which parse
532 * the ACPI table. So we check the checksum here.
534 static int __init find_last_devid_acpi(struct acpi_table_header *table)
536 u8 *p = (u8 *)table, *end = (u8 *)table;
537 struct ivhd_header *h;
539 p += IVRS_HEADER_LENGTH;
541 end += table->length;
543 h = (struct ivhd_header *)p;
544 if (h->type == amd_iommu_target_ivhd_type) {
545 int ret = find_last_devid_from_ivhd(h);
557 /****************************************************************************
559 * The following functions belong to the code path which parses the ACPI table
560 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
561 * data structures, initialize the device/alias/rlookup table and also
562 * basically initialize the hardware.
564 ****************************************************************************/
567 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
568 * write commands to that buffer later and the IOMMU will execute them
571 static int __init alloc_command_buffer(struct amd_iommu *iommu)
573 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
574 get_order(CMD_BUFFER_SIZE));
576 return iommu->cmd_buf ? 0 : -ENOMEM;
580 * This function resets the command buffer if the IOMMU stopped fetching
583 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
585 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
587 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
588 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
590 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
594 * This function writes the command buffer address to the hardware and
597 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
601 BUG_ON(iommu->cmd_buf == NULL);
603 entry = (u64)virt_to_phys(iommu->cmd_buf);
604 entry |= MMIO_CMD_SIZE_512;
606 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
607 &entry, sizeof(entry));
609 amd_iommu_reset_cmd_buffer(iommu);
612 static void __init free_command_buffer(struct amd_iommu *iommu)
614 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
617 /* allocates the memory where the IOMMU will log its events to */
618 static int __init alloc_event_buffer(struct amd_iommu *iommu)
620 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
621 get_order(EVT_BUFFER_SIZE));
623 return iommu->evt_buf ? 0 : -ENOMEM;
626 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
630 BUG_ON(iommu->evt_buf == NULL);
632 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
634 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
635 &entry, sizeof(entry));
637 /* set head and tail to zero manually */
638 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
641 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
644 static void __init free_event_buffer(struct amd_iommu *iommu)
646 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
649 /* allocates the memory where the IOMMU will log its events to */
650 static int __init alloc_ppr_log(struct amd_iommu *iommu)
652 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
653 get_order(PPR_LOG_SIZE));
655 return iommu->ppr_log ? 0 : -ENOMEM;
658 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
662 if (iommu->ppr_log == NULL)
665 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
667 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
668 &entry, sizeof(entry));
670 /* set head and tail to zero manually */
671 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
674 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
675 iommu_feature_enable(iommu, CONTROL_PPR_EN);
678 static void __init free_ppr_log(struct amd_iommu *iommu)
680 if (iommu->ppr_log == NULL)
683 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
686 static void free_ga_log(struct amd_iommu *iommu)
688 #ifdef CONFIG_IRQ_REMAP
690 free_pages((unsigned long)iommu->ga_log,
691 get_order(GA_LOG_SIZE));
692 if (iommu->ga_log_tail)
693 free_pages((unsigned long)iommu->ga_log_tail,
698 static int iommu_ga_log_enable(struct amd_iommu *iommu)
700 #ifdef CONFIG_IRQ_REMAP
706 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
708 /* Check if already running */
709 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
712 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
713 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
715 for (i = 0; i < LOOP_TIMEOUT; ++i) {
716 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
717 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
722 if (i >= LOOP_TIMEOUT)
724 #endif /* CONFIG_IRQ_REMAP */
728 #ifdef CONFIG_IRQ_REMAP
729 static int iommu_init_ga_log(struct amd_iommu *iommu)
733 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
736 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
737 get_order(GA_LOG_SIZE));
741 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
743 if (!iommu->ga_log_tail)
746 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
747 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
748 &entry, sizeof(entry));
749 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
750 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
751 &entry, sizeof(entry));
752 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
753 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
760 #endif /* CONFIG_IRQ_REMAP */
762 static int iommu_init_ga(struct amd_iommu *iommu)
766 #ifdef CONFIG_IRQ_REMAP
767 /* Note: We have already checked GASup from IVRS table.
768 * Now, we need to make sure that GAMSup is set.
770 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
771 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
772 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
774 ret = iommu_init_ga_log(iommu);
775 #endif /* CONFIG_IRQ_REMAP */
780 static void iommu_enable_gt(struct amd_iommu *iommu)
782 if (!iommu_feature(iommu, FEATURE_GT))
785 iommu_feature_enable(iommu, CONTROL_GT_EN);
788 /* sets a specific bit in the device table entry. */
789 static void set_dev_entry_bit(u16 devid, u8 bit)
791 int i = (bit >> 6) & 0x03;
792 int _bit = bit & 0x3f;
794 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
797 static int get_dev_entry_bit(u16 devid, u8 bit)
799 int i = (bit >> 6) & 0x03;
800 int _bit = bit & 0x3f;
802 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
806 void amd_iommu_apply_erratum_63(u16 devid)
810 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
811 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
814 set_dev_entry_bit(devid, DEV_ENTRY_IW);
817 /* Writes the specific IOMMU for a device into the rlookup table */
818 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
820 amd_iommu_rlookup_table[devid] = iommu;
824 * This function takes the device specific flags read from the ACPI
825 * table and sets up the device table entry with that information
827 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
828 u16 devid, u32 flags, u32 ext_flags)
830 if (flags & ACPI_DEVFLAG_INITPASS)
831 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
832 if (flags & ACPI_DEVFLAG_EXTINT)
833 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
834 if (flags & ACPI_DEVFLAG_NMI)
835 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
836 if (flags & ACPI_DEVFLAG_SYSMGT1)
837 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
838 if (flags & ACPI_DEVFLAG_SYSMGT2)
839 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
840 if (flags & ACPI_DEVFLAG_LINT0)
841 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
842 if (flags & ACPI_DEVFLAG_LINT1)
843 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
845 amd_iommu_apply_erratum_63(devid);
847 set_iommu_for_device(iommu, devid);
850 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
852 struct devid_map *entry;
853 struct list_head *list;
855 if (type == IVHD_SPECIAL_IOAPIC)
857 else if (type == IVHD_SPECIAL_HPET)
862 list_for_each_entry(entry, list, list) {
863 if (!(entry->id == id && entry->cmd_line))
866 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
867 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
869 *devid = entry->devid;
874 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
879 entry->devid = *devid;
880 entry->cmd_line = cmd_line;
882 list_add_tail(&entry->list, list);
887 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
890 struct acpihid_map_entry *entry;
891 struct list_head *list = &acpihid_map;
893 list_for_each_entry(entry, list, list) {
894 if (strcmp(entry->hid, hid) ||
895 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
899 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
901 *devid = entry->devid;
905 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
909 memcpy(entry->uid, uid, strlen(uid));
910 memcpy(entry->hid, hid, strlen(hid));
911 entry->devid = *devid;
912 entry->cmd_line = cmd_line;
913 entry->root_devid = (entry->devid & (~0x7));
915 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
916 entry->cmd_line ? "cmd" : "ivrs",
917 entry->hid, entry->uid, entry->root_devid);
919 list_add_tail(&entry->list, list);
923 static int __init add_early_maps(void)
927 for (i = 0; i < early_ioapic_map_size; ++i) {
928 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
929 early_ioapic_map[i].id,
930 &early_ioapic_map[i].devid,
931 early_ioapic_map[i].cmd_line);
936 for (i = 0; i < early_hpet_map_size; ++i) {
937 ret = add_special_device(IVHD_SPECIAL_HPET,
938 early_hpet_map[i].id,
939 &early_hpet_map[i].devid,
940 early_hpet_map[i].cmd_line);
945 for (i = 0; i < early_acpihid_map_size; ++i) {
946 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
947 early_acpihid_map[i].uid,
948 &early_acpihid_map[i].devid,
949 early_acpihid_map[i].cmd_line);
958 * Reads the device exclusion range from ACPI and initializes the IOMMU with
961 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
963 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
965 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
970 * We only can configure exclusion ranges per IOMMU, not
971 * per device. But we can enable the exclusion range per
972 * device. This is done here
974 set_dev_entry_bit(devid, DEV_ENTRY_EX);
975 iommu->exclusion_start = m->range_start;
976 iommu->exclusion_length = m->range_length;
981 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
982 * initializes the hardware and our data structures with it.
984 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
985 struct ivhd_header *h)
988 u8 *end = p, flags = 0;
989 u16 devid = 0, devid_start = 0, devid_to = 0;
990 u32 dev_i, ext_flags = 0;
992 struct ivhd_entry *e;
997 ret = add_early_maps();
1002 * First save the recommended feature enable bits from ACPI
1004 iommu->acpi_flags = h->flags;
1007 * Done. Now parse the device entries
1009 ivhd_size = get_ivhd_header_size(h);
1011 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1021 e = (struct ivhd_entry *)p;
1025 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1027 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1028 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1030 case IVHD_DEV_SELECT:
1032 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1034 PCI_BUS_NUM(e->devid),
1040 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1042 case IVHD_DEV_SELECT_RANGE_START:
1044 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1045 "devid: %02x:%02x.%x flags: %02x\n",
1046 PCI_BUS_NUM(e->devid),
1051 devid_start = e->devid;
1056 case IVHD_DEV_ALIAS:
1058 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1059 "flags: %02x devid_to: %02x:%02x.%x\n",
1060 PCI_BUS_NUM(e->devid),
1064 PCI_BUS_NUM(e->ext >> 8),
1065 PCI_SLOT(e->ext >> 8),
1066 PCI_FUNC(e->ext >> 8));
1069 devid_to = e->ext >> 8;
1070 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1071 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1072 amd_iommu_alias_table[devid] = devid_to;
1074 case IVHD_DEV_ALIAS_RANGE:
1076 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1077 "devid: %02x:%02x.%x flags: %02x "
1078 "devid_to: %02x:%02x.%x\n",
1079 PCI_BUS_NUM(e->devid),
1083 PCI_BUS_NUM(e->ext >> 8),
1084 PCI_SLOT(e->ext >> 8),
1085 PCI_FUNC(e->ext >> 8));
1087 devid_start = e->devid;
1089 devid_to = e->ext >> 8;
1093 case IVHD_DEV_EXT_SELECT:
1095 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1096 "flags: %02x ext: %08x\n",
1097 PCI_BUS_NUM(e->devid),
1103 set_dev_entry_from_acpi(iommu, devid, e->flags,
1106 case IVHD_DEV_EXT_SELECT_RANGE:
1108 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1109 "%02x:%02x.%x flags: %02x ext: %08x\n",
1110 PCI_BUS_NUM(e->devid),
1115 devid_start = e->devid;
1120 case IVHD_DEV_RANGE_END:
1122 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1123 PCI_BUS_NUM(e->devid),
1125 PCI_FUNC(e->devid));
1128 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1130 amd_iommu_alias_table[dev_i] = devid_to;
1131 set_dev_entry_from_acpi(iommu,
1132 devid_to, flags, ext_flags);
1134 set_dev_entry_from_acpi(iommu, dev_i,
1138 case IVHD_DEV_SPECIAL: {
1144 handle = e->ext & 0xff;
1145 devid = (e->ext >> 8) & 0xffff;
1146 type = (e->ext >> 24) & 0xff;
1148 if (type == IVHD_SPECIAL_IOAPIC)
1150 else if (type == IVHD_SPECIAL_HPET)
1155 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1161 ret = add_special_device(type, handle, &devid, false);
1166 * add_special_device might update the devid in case a
1167 * command-line override is present. So call
1168 * set_dev_entry_from_acpi after add_special_device.
1170 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1174 case IVHD_DEV_ACPI_HID: {
1176 u8 hid[ACPIHID_HID_LEN];
1177 u8 uid[ACPIHID_UID_LEN];
1180 if (h->type != 0x40) {
1181 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1186 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1187 hid[ACPIHID_HID_LEN - 1] = '\0';
1190 pr_err(FW_BUG "Invalid HID.\n");
1196 case UID_NOT_PRESENT:
1199 pr_warn(FW_BUG "Invalid UID length.\n");
1202 case UID_IS_INTEGER:
1204 sprintf(uid, "%d", e->uid);
1207 case UID_IS_CHARACTER:
1209 memcpy(uid, &e->uid, e->uidl);
1210 uid[e->uidl] = '\0';
1218 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1226 ret = add_acpi_hid_device(hid, uid, &devid, false);
1231 * add_special_device might update the devid in case a
1232 * command-line override is present. So call
1233 * set_dev_entry_from_acpi after add_special_device.
1235 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1243 p += ivhd_entry_length(p);
1249 static void __init free_iommu_one(struct amd_iommu *iommu)
1251 free_command_buffer(iommu);
1252 free_event_buffer(iommu);
1253 free_ppr_log(iommu);
1255 iommu_unmap_mmio_space(iommu);
1258 static void __init free_iommu_all(void)
1260 struct amd_iommu *iommu, *next;
1262 for_each_iommu_safe(iommu, next) {
1263 list_del(&iommu->list);
1264 free_iommu_one(iommu);
1270 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1272 * BIOS should disable L2B micellaneous clock gating by setting
1273 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1275 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1279 if ((boot_cpu_data.x86 != 0x15) ||
1280 (boot_cpu_data.x86_model < 0x10) ||
1281 (boot_cpu_data.x86_model > 0x1f))
1284 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1285 pci_read_config_dword(iommu->dev, 0xf4, &value);
1290 /* Select NB indirect register 0x90 and enable writing */
1291 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1293 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1294 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1295 dev_name(&iommu->dev->dev));
1297 /* Clear the enable writing bit */
1298 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1302 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1304 * BIOS should enable ATS write permission check by setting
1305 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1307 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1311 if ((boot_cpu_data.x86 != 0x15) ||
1312 (boot_cpu_data.x86_model < 0x30) ||
1313 (boot_cpu_data.x86_model > 0x3f))
1316 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1317 value = iommu_read_l2(iommu, 0x47);
1322 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1323 iommu_write_l2(iommu, 0x47, value | BIT(0));
1325 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1326 dev_name(&iommu->dev->dev));
1330 * This function clues the initialization function for one IOMMU
1331 * together and also allocates the command buffer and programs the
1332 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1334 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1338 spin_lock_init(&iommu->lock);
1340 /* Add IOMMU to internal data structures */
1341 list_add_tail(&iommu->list, &amd_iommu_list);
1342 iommu->index = amd_iommus_present++;
1344 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1345 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1349 /* Index is fine - add IOMMU to the array */
1350 amd_iommus[iommu->index] = iommu;
1353 * Copy data from ACPI table entry to the iommu struct
1355 iommu->devid = h->devid;
1356 iommu->cap_ptr = h->cap_ptr;
1357 iommu->pci_seg = h->pci_seg;
1358 iommu->mmio_phys = h->mmio_phys;
1362 /* Check if IVHD EFR contains proper max banks/counters */
1363 if ((h->efr_attr != 0) &&
1364 ((h->efr_attr & (0xF << 13)) != 0) &&
1365 ((h->efr_attr & (0x3F << 17)) != 0))
1366 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1368 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1369 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1370 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1374 if (h->efr_reg & (1 << 9))
1375 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1377 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1378 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1379 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1385 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1386 iommu->mmio_phys_end);
1387 if (!iommu->mmio_base)
1390 if (alloc_command_buffer(iommu))
1393 if (alloc_event_buffer(iommu))
1396 iommu->int_enabled = false;
1398 ret = init_iommu_from_acpi(iommu, h);
1402 ret = amd_iommu_create_irq_domain(iommu);
1407 * Make sure IOMMU is not considered to translate itself. The IVRS
1408 * table tells us so, but this is a lie!
1410 amd_iommu_rlookup_table[iommu->devid] = NULL;
1416 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1417 * @ivrs Pointer to the IVRS header
1419 * This function search through all IVDB of the maximum supported IVHD
1421 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1423 u8 *base = (u8 *)ivrs;
1424 struct ivhd_header *ivhd = (struct ivhd_header *)
1425 (base + IVRS_HEADER_LENGTH);
1426 u8 last_type = ivhd->type;
1427 u16 devid = ivhd->devid;
1429 while (((u8 *)ivhd - base < ivrs->length) &&
1430 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1431 u8 *p = (u8 *) ivhd;
1433 if (ivhd->devid == devid)
1434 last_type = ivhd->type;
1435 ivhd = (struct ivhd_header *)(p + ivhd->length);
1442 * Iterates over all IOMMU entries in the ACPI table, allocates the
1443 * IOMMU structure and initializes it with init_iommu_one()
1445 static int __init init_iommu_all(struct acpi_table_header *table)
1447 u8 *p = (u8 *)table, *end = (u8 *)table;
1448 struct ivhd_header *h;
1449 struct amd_iommu *iommu;
1452 end += table->length;
1453 p += IVRS_HEADER_LENGTH;
1456 h = (struct ivhd_header *)p;
1457 if (*p == amd_iommu_target_ivhd_type) {
1459 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1460 "seg: %d flags: %01x info %04x\n",
1461 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1462 PCI_FUNC(h->devid), h->cap_ptr,
1463 h->pci_seg, h->flags, h->info);
1464 DUMP_printk(" mmio-addr: %016llx\n",
1467 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1471 ret = init_iommu_one(iommu, h);
1484 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1486 u64 val = 0xabcd, val2 = 0;
1488 if (!iommu_feature(iommu, FEATURE_PC))
1491 amd_iommu_pc_present = true;
1493 /* Check if the performance counters can be written to */
1494 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1495 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
1497 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1498 amd_iommu_pc_present = false;
1502 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1504 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1505 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1506 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1509 static ssize_t amd_iommu_show_cap(struct device *dev,
1510 struct device_attribute *attr,
1513 struct amd_iommu *iommu = dev_get_drvdata(dev);
1514 return sprintf(buf, "%x\n", iommu->cap);
1516 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1518 static ssize_t amd_iommu_show_features(struct device *dev,
1519 struct device_attribute *attr,
1522 struct amd_iommu *iommu = dev_get_drvdata(dev);
1523 return sprintf(buf, "%llx\n", iommu->features);
1525 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1527 static struct attribute *amd_iommu_attrs[] = {
1529 &dev_attr_features.attr,
1533 static struct attribute_group amd_iommu_group = {
1534 .name = "amd-iommu",
1535 .attrs = amd_iommu_attrs,
1538 static const struct attribute_group *amd_iommu_groups[] = {
1543 static int __init iommu_init_pci(struct amd_iommu *iommu)
1545 int cap_ptr = iommu->cap_ptr;
1546 u32 range, misc, low, high;
1549 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1550 iommu->devid & 0xff);
1554 /* Prevent binding other PCI device drivers to IOMMU devices */
1555 iommu->dev->match_driver = false;
1557 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1559 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1561 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1564 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1565 amd_iommu_iotlb_sup = false;
1567 /* read extended feature bits */
1568 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1569 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1571 iommu->features = ((u64)high << 32) | low;
1573 if (iommu_feature(iommu, FEATURE_GT)) {
1578 pasmax = iommu->features & FEATURE_PASID_MASK;
1579 pasmax >>= FEATURE_PASID_SHIFT;
1580 max_pasid = (1 << (pasmax + 1)) - 1;
1582 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1584 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1586 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1587 glxval >>= FEATURE_GLXVAL_SHIFT;
1589 if (amd_iommu_max_glx_val == -1)
1590 amd_iommu_max_glx_val = glxval;
1592 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1595 if (iommu_feature(iommu, FEATURE_GT) &&
1596 iommu_feature(iommu, FEATURE_PPR)) {
1597 iommu->is_iommu_v2 = true;
1598 amd_iommu_v2_present = true;
1601 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1604 ret = iommu_init_ga(iommu);
1608 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1609 amd_iommu_np_cache = true;
1611 init_iommu_perf_ctr(iommu);
1613 if (is_rd890_iommu(iommu->dev)) {
1616 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1620 * Some rd890 systems may not be fully reconfigured by the
1621 * BIOS, so it's necessary for us to store this information so
1622 * it can be reprogrammed on resume
1624 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1625 &iommu->stored_addr_lo);
1626 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1627 &iommu->stored_addr_hi);
1629 /* Low bit locks writes to configuration space */
1630 iommu->stored_addr_lo &= ~1;
1632 for (i = 0; i < 6; i++)
1633 for (j = 0; j < 0x12; j++)
1634 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1636 for (i = 0; i < 0x83; i++)
1637 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1640 amd_iommu_erratum_746_workaround(iommu);
1641 amd_iommu_ats_write_check_workaround(iommu);
1643 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1644 amd_iommu_groups, "ivhd%d",
1647 return pci_enable_device(iommu->dev);
1650 static void print_iommu_info(void)
1652 static const char * const feat_str[] = {
1653 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1654 "IA", "GA", "HE", "PC"
1656 struct amd_iommu *iommu;
1658 for_each_iommu(iommu) {
1661 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1662 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1664 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1665 pr_info("AMD-Vi: Extended features (%#llx):\n",
1667 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1668 if (iommu_feature(iommu, (1ULL << i)))
1669 pr_cont(" %s", feat_str[i]);
1672 if (iommu->features & FEATURE_GAM_VAPIC)
1673 pr_cont(" GA_vAPIC");
1678 if (irq_remapping_enabled) {
1679 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1680 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1681 pr_info("AMD-Vi: virtual APIC enabled\n");
1685 static int __init amd_iommu_init_pci(void)
1687 struct amd_iommu *iommu;
1690 for_each_iommu(iommu) {
1691 ret = iommu_init_pci(iommu);
1697 * Order is important here to make sure any unity map requirements are
1698 * fulfilled. The unity mappings are created and written to the device
1699 * table during the amd_iommu_init_api() call.
1701 * After that we call init_device_table_dma() to make sure any
1702 * uninitialized DTE will block DMA, and in the end we flush the caches
1703 * of all IOMMUs to make sure the changes to the device table are
1706 ret = amd_iommu_init_api();
1708 init_device_table_dma();
1710 for_each_iommu(iommu)
1711 iommu_flush_all_caches(iommu);
1719 /****************************************************************************
1721 * The following functions initialize the MSI interrupts for all IOMMUs
1722 * in the system. It's a bit challenging because there could be multiple
1723 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1726 ****************************************************************************/
1728 static int iommu_setup_msi(struct amd_iommu *iommu)
1732 r = pci_enable_msi(iommu->dev);
1736 r = request_threaded_irq(iommu->dev->irq,
1737 amd_iommu_int_handler,
1738 amd_iommu_int_thread,
1743 pci_disable_msi(iommu->dev);
1747 iommu->int_enabled = true;
1752 static int iommu_init_msi(struct amd_iommu *iommu)
1756 if (iommu->int_enabled)
1759 if (iommu->dev->msi_cap)
1760 ret = iommu_setup_msi(iommu);
1768 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1770 if (iommu->ppr_log != NULL)
1771 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1773 iommu_ga_log_enable(iommu);
1778 /****************************************************************************
1780 * The next functions belong to the third pass of parsing the ACPI
1781 * table. In this last pass the memory mapping requirements are
1782 * gathered (like exclusion and unity mapping ranges).
1784 ****************************************************************************/
1786 static void __init free_unity_maps(void)
1788 struct unity_map_entry *entry, *next;
1790 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1791 list_del(&entry->list);
1796 /* called when we find an exclusion range definition in ACPI */
1797 static int __init init_exclusion_range(struct ivmd_header *m)
1802 case ACPI_IVMD_TYPE:
1803 set_device_exclusion_range(m->devid, m);
1805 case ACPI_IVMD_TYPE_ALL:
1806 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1807 set_device_exclusion_range(i, m);
1809 case ACPI_IVMD_TYPE_RANGE:
1810 for (i = m->devid; i <= m->aux; ++i)
1811 set_device_exclusion_range(i, m);
1820 /* called for unity map ACPI definition */
1821 static int __init init_unity_map_range(struct ivmd_header *m)
1823 struct unity_map_entry *e = NULL;
1826 e = kzalloc(sizeof(*e), GFP_KERNEL);
1834 case ACPI_IVMD_TYPE:
1835 s = "IVMD_TYPEi\t\t\t";
1836 e->devid_start = e->devid_end = m->devid;
1838 case ACPI_IVMD_TYPE_ALL:
1839 s = "IVMD_TYPE_ALL\t\t";
1841 e->devid_end = amd_iommu_last_bdf;
1843 case ACPI_IVMD_TYPE_RANGE:
1844 s = "IVMD_TYPE_RANGE\t\t";
1845 e->devid_start = m->devid;
1846 e->devid_end = m->aux;
1849 e->address_start = PAGE_ALIGN(m->range_start);
1850 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1851 e->prot = m->flags >> 1;
1853 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1854 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1855 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1856 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1857 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1858 e->address_start, e->address_end, m->flags);
1860 list_add_tail(&e->list, &amd_iommu_unity_map);
1865 /* iterates over all memory definitions we find in the ACPI table */
1866 static int __init init_memory_definitions(struct acpi_table_header *table)
1868 u8 *p = (u8 *)table, *end = (u8 *)table;
1869 struct ivmd_header *m;
1871 end += table->length;
1872 p += IVRS_HEADER_LENGTH;
1875 m = (struct ivmd_header *)p;
1876 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1877 init_exclusion_range(m);
1878 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1879 init_unity_map_range(m);
1888 * Init the device table to not allow DMA access for devices and
1889 * suppress all page faults
1891 static void init_device_table_dma(void)
1895 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1896 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1897 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1901 static void __init uninit_device_table_dma(void)
1905 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1906 amd_iommu_dev_table[devid].data[0] = 0ULL;
1907 amd_iommu_dev_table[devid].data[1] = 0ULL;
1911 static void init_device_table(void)
1915 if (!amd_iommu_irq_remap)
1918 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1919 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1922 static void iommu_init_flags(struct amd_iommu *iommu)
1924 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1925 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1926 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1928 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1929 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1930 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1932 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1933 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1934 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1936 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1937 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1938 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1941 * make IOMMU memory accesses cache coherent
1943 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1945 /* Set IOTLB invalidation timeout to 1s */
1946 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1949 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1952 u32 ioc_feature_control;
1953 struct pci_dev *pdev = iommu->root_pdev;
1955 /* RD890 BIOSes may not have completely reconfigured the iommu */
1956 if (!is_rd890_iommu(iommu->dev) || !pdev)
1960 * First, we need to ensure that the iommu is enabled. This is
1961 * controlled by a register in the northbridge
1964 /* Select Northbridge indirect register 0x75 and enable writing */
1965 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1966 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1968 /* Enable the iommu */
1969 if (!(ioc_feature_control & 0x1))
1970 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1972 /* Restore the iommu BAR */
1973 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1974 iommu->stored_addr_lo);
1975 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1976 iommu->stored_addr_hi);
1978 /* Restore the l1 indirect regs for each of the 6 l1s */
1979 for (i = 0; i < 6; i++)
1980 for (j = 0; j < 0x12; j++)
1981 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1983 /* Restore the l2 indirect regs */
1984 for (i = 0; i < 0x83; i++)
1985 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1987 /* Lock PCI setup registers */
1988 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1989 iommu->stored_addr_lo | 1);
1992 static void iommu_enable_ga(struct amd_iommu *iommu)
1994 #ifdef CONFIG_IRQ_REMAP
1995 switch (amd_iommu_guest_ir) {
1996 case AMD_IOMMU_GUEST_IR_VAPIC:
1997 iommu_feature_enable(iommu, CONTROL_GAM_EN);
1999 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2000 iommu_feature_enable(iommu, CONTROL_GA_EN);
2001 iommu->irte_ops = &irte_128_ops;
2004 iommu->irte_ops = &irte_32_ops;
2011 * This function finally enables all IOMMUs found in the system after
2012 * they have been initialized
2014 static void early_enable_iommus(void)
2016 struct amd_iommu *iommu;
2018 for_each_iommu(iommu) {
2019 iommu_disable(iommu);
2020 iommu_init_flags(iommu);
2021 iommu_set_device_table(iommu);
2022 iommu_enable_command_buffer(iommu);
2023 iommu_enable_event_buffer(iommu);
2024 iommu_set_exclusion_range(iommu);
2025 iommu_enable_ga(iommu);
2026 iommu_enable(iommu);
2027 iommu_flush_all_caches(iommu);
2030 #ifdef CONFIG_IRQ_REMAP
2031 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2032 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2036 static void enable_iommus_v2(void)
2038 struct amd_iommu *iommu;
2040 for_each_iommu(iommu) {
2041 iommu_enable_ppr_log(iommu);
2042 iommu_enable_gt(iommu);
2046 static void enable_iommus(void)
2048 early_enable_iommus();
2053 static void disable_iommus(void)
2055 struct amd_iommu *iommu;
2057 for_each_iommu(iommu)
2058 iommu_disable(iommu);
2060 #ifdef CONFIG_IRQ_REMAP
2061 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2062 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2067 * Suspend/Resume support
2068 * disable suspend until real resume implemented
2071 static void amd_iommu_resume(void)
2073 struct amd_iommu *iommu;
2075 for_each_iommu(iommu)
2076 iommu_apply_resume_quirks(iommu);
2078 /* re-load the hardware */
2081 amd_iommu_enable_interrupts();
2084 static int amd_iommu_suspend(void)
2086 /* disable IOMMUs to go out of the way for BIOS */
2092 static struct syscore_ops amd_iommu_syscore_ops = {
2093 .suspend = amd_iommu_suspend,
2094 .resume = amd_iommu_resume,
2097 static void __init free_on_init_error(void)
2099 free_pages((unsigned long)irq_lookup_table,
2100 get_order(rlookup_table_size));
2102 kmem_cache_destroy(amd_iommu_irq_cache);
2103 amd_iommu_irq_cache = NULL;
2105 free_pages((unsigned long)amd_iommu_rlookup_table,
2106 get_order(rlookup_table_size));
2108 free_pages((unsigned long)amd_iommu_alias_table,
2109 get_order(alias_table_size));
2111 free_pages((unsigned long)amd_iommu_dev_table,
2112 get_order(dev_table_size));
2116 #ifdef CONFIG_GART_IOMMU
2118 * We failed to initialize the AMD IOMMU - try fallback to GART
2126 /* SB IOAPIC is always on this device in AMD systems */
2127 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2129 static bool __init check_ioapic_information(void)
2131 const char *fw_bug = FW_BUG;
2132 bool ret, has_sb_ioapic;
2135 has_sb_ioapic = false;
2139 * If we have map overrides on the kernel command line the
2140 * messages in this function might not describe firmware bugs
2141 * anymore - so be careful
2146 for (idx = 0; idx < nr_ioapics; idx++) {
2147 int devid, id = mpc_ioapic_id(idx);
2149 devid = get_ioapic_devid(id);
2151 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2154 } else if (devid == IOAPIC_SB_DEVID) {
2155 has_sb_ioapic = true;
2160 if (!has_sb_ioapic) {
2162 * We expect the SB IOAPIC to be listed in the IVRS
2163 * table. The system timer is connected to the SB IOAPIC
2164 * and if we don't have it in the list the system will
2165 * panic at boot time. This situation usually happens
2166 * when the BIOS is buggy and provides us the wrong
2167 * device id for the IOAPIC in the system.
2169 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2173 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2178 static void __init free_dma_resources(void)
2180 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2181 get_order(MAX_DOMAIN_ID/8));
2187 * This is the hardware init function for AMD IOMMU in the system.
2188 * This function is called either from amd_iommu_init or from the interrupt
2189 * remapping setup code.
2191 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2194 * 1 pass) Discover the most comprehensive IVHD type to use.
2196 * 2 pass) Find the highest PCI device id the driver has to handle.
2197 * Upon this information the size of the data structures is
2198 * determined that needs to be allocated.
2200 * 3 pass) Initialize the data structures just allocated with the
2201 * information in the ACPI table about available AMD IOMMUs
2202 * in the system. It also maps the PCI devices in the
2203 * system to specific IOMMUs
2205 * 4 pass) After the basic data structures are allocated and
2206 * initialized we update them with information about memory
2207 * remapping requirements parsed out of the ACPI table in
2210 * After everything is set up the IOMMUs are enabled and the necessary
2211 * hotplug and suspend notifiers are registered.
2213 static int __init early_amd_iommu_init(void)
2215 struct acpi_table_header *ivrs_base;
2216 acpi_size ivrs_size;
2218 int i, remap_cache_sz, ret = 0;
2220 if (!amd_iommu_detected)
2223 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2224 if (status == AE_NOT_FOUND)
2226 else if (ACPI_FAILURE(status)) {
2227 const char *err = acpi_format_exception(status);
2228 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2233 * Validate checksum here so we don't need to do it when
2234 * we actually parse the table
2236 ret = check_ivrs_checksum(ivrs_base);
2240 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2241 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2244 * First parse ACPI tables to find the largest Bus/Dev/Func
2245 * we need to handle. Upon this information the shared data
2246 * structures for the IOMMUs in the system will be allocated
2248 ret = find_last_devid_acpi(ivrs_base);
2252 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2253 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2254 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2256 /* Device table - directly used by all IOMMUs */
2258 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2259 get_order(dev_table_size));
2260 if (amd_iommu_dev_table == NULL)
2264 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2265 * IOMMU see for that device
2267 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2268 get_order(alias_table_size));
2269 if (amd_iommu_alias_table == NULL)
2272 /* IOMMU rlookup table - find the IOMMU for a specific device */
2273 amd_iommu_rlookup_table = (void *)__get_free_pages(
2274 GFP_KERNEL | __GFP_ZERO,
2275 get_order(rlookup_table_size));
2276 if (amd_iommu_rlookup_table == NULL)
2279 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2280 GFP_KERNEL | __GFP_ZERO,
2281 get_order(MAX_DOMAIN_ID/8));
2282 if (amd_iommu_pd_alloc_bitmap == NULL)
2286 * let all alias entries point to itself
2288 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2289 amd_iommu_alias_table[i] = i;
2292 * never allocate domain 0 because its used as the non-allocated and
2293 * error value placeholder
2295 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2297 spin_lock_init(&amd_iommu_pd_lock);
2300 * now the data structures are allocated and basically initialized
2301 * start the real acpi table scan
2303 ret = init_iommu_all(ivrs_base);
2307 if (amd_iommu_irq_remap)
2308 amd_iommu_irq_remap = check_ioapic_information();
2310 if (amd_iommu_irq_remap) {
2312 * Interrupt remapping enabled, create kmem_cache for the
2316 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2317 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2319 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2320 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2322 IRQ_TABLE_ALIGNMENT,
2324 if (!amd_iommu_irq_cache)
2327 irq_lookup_table = (void *)__get_free_pages(
2328 GFP_KERNEL | __GFP_ZERO,
2329 get_order(rlookup_table_size));
2330 if (!irq_lookup_table)
2334 ret = init_memory_definitions(ivrs_base);
2338 /* init the device table */
2339 init_device_table();
2342 /* Don't leak any ACPI memory */
2343 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2349 static int amd_iommu_enable_interrupts(void)
2351 struct amd_iommu *iommu;
2354 for_each_iommu(iommu) {
2355 ret = iommu_init_msi(iommu);
2364 static bool detect_ivrs(void)
2366 struct acpi_table_header *ivrs_base;
2367 acpi_size ivrs_size;
2370 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2371 if (status == AE_NOT_FOUND)
2373 else if (ACPI_FAILURE(status)) {
2374 const char *err = acpi_format_exception(status);
2375 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2379 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2381 /* Make sure ACS will be enabled during PCI probe */
2387 /****************************************************************************
2389 * AMD IOMMU Initialization State Machine
2391 ****************************************************************************/
2393 static int __init state_next(void)
2397 switch (init_state) {
2398 case IOMMU_START_STATE:
2399 if (!detect_ivrs()) {
2400 init_state = IOMMU_NOT_FOUND;
2403 init_state = IOMMU_IVRS_DETECTED;
2406 case IOMMU_IVRS_DETECTED:
2407 ret = early_amd_iommu_init();
2408 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2410 case IOMMU_ACPI_FINISHED:
2411 early_enable_iommus();
2412 register_syscore_ops(&amd_iommu_syscore_ops);
2413 x86_platform.iommu_shutdown = disable_iommus;
2414 init_state = IOMMU_ENABLED;
2417 ret = amd_iommu_init_pci();
2418 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2421 case IOMMU_PCI_INIT:
2422 ret = amd_iommu_enable_interrupts();
2423 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2425 case IOMMU_INTERRUPTS_EN:
2426 ret = amd_iommu_init_dma_ops();
2427 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2430 init_state = IOMMU_INITIALIZED;
2432 case IOMMU_INITIALIZED:
2435 case IOMMU_NOT_FOUND:
2436 case IOMMU_INIT_ERROR:
2437 /* Error states => do nothing */
2448 static int __init iommu_go_to_state(enum iommu_init_state state)
2452 while (init_state != state) {
2454 if (init_state == IOMMU_NOT_FOUND ||
2455 init_state == IOMMU_INIT_ERROR)
2462 #ifdef CONFIG_IRQ_REMAP
2463 int __init amd_iommu_prepare(void)
2467 amd_iommu_irq_remap = true;
2469 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2472 return amd_iommu_irq_remap ? 0 : -ENODEV;
2475 int __init amd_iommu_enable(void)
2479 ret = iommu_go_to_state(IOMMU_ENABLED);
2483 irq_remapping_enabled = 1;
2488 void amd_iommu_disable(void)
2490 amd_iommu_suspend();
2493 int amd_iommu_reenable(int mode)
2500 int __init amd_iommu_enable_faulting(void)
2502 /* We enable MSI later when PCI is initialized */
2508 * This is the core init function for AMD IOMMU hardware in the system.
2509 * This function is called from the generic x86 DMA layer initialization
2512 static int __init amd_iommu_init(void)
2516 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2518 free_dma_resources();
2519 if (!irq_remapping_enabled) {
2521 free_on_init_error();
2523 struct amd_iommu *iommu;
2525 uninit_device_table_dma();
2526 for_each_iommu(iommu)
2527 iommu_flush_all_caches(iommu);
2534 /****************************************************************************
2536 * Early detect code. This code runs at IOMMU detection time in the DMA
2537 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2540 ****************************************************************************/
2541 int __init amd_iommu_detect(void)
2545 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2548 if (amd_iommu_disabled)
2551 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2555 amd_iommu_detected = true;
2557 x86_init.iommu.iommu_init = amd_iommu_init;
2562 /****************************************************************************
2564 * Parsing functions for the AMD IOMMU specific kernel command line
2567 ****************************************************************************/
2569 static int __init parse_amd_iommu_dump(char *str)
2571 amd_iommu_dump = true;
2576 static int __init parse_amd_iommu_intr(char *str)
2578 for (; *str; ++str) {
2579 if (strncmp(str, "legacy", 6) == 0) {
2580 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
2583 if (strncmp(str, "vapic", 5) == 0) {
2584 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2591 static int __init parse_amd_iommu_options(char *str)
2593 for (; *str; ++str) {
2594 if (strncmp(str, "fullflush", 9) == 0)
2595 amd_iommu_unmap_flush = true;
2596 if (strncmp(str, "off", 3) == 0)
2597 amd_iommu_disabled = true;
2598 if (strncmp(str, "force_isolation", 15) == 0)
2599 amd_iommu_force_isolation = true;
2605 static int __init parse_ivrs_ioapic(char *str)
2607 unsigned int bus, dev, fn;
2611 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2614 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2618 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2619 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2624 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2626 cmdline_maps = true;
2627 i = early_ioapic_map_size++;
2628 early_ioapic_map[i].id = id;
2629 early_ioapic_map[i].devid = devid;
2630 early_ioapic_map[i].cmd_line = true;
2635 static int __init parse_ivrs_hpet(char *str)
2637 unsigned int bus, dev, fn;
2641 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2644 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2648 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2649 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2654 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2656 cmdline_maps = true;
2657 i = early_hpet_map_size++;
2658 early_hpet_map[i].id = id;
2659 early_hpet_map[i].devid = devid;
2660 early_hpet_map[i].cmd_line = true;
2665 static int __init parse_ivrs_acpihid(char *str)
2668 char *hid, *uid, *p;
2669 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2672 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2674 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2679 hid = strsep(&p, ":");
2682 if (!hid || !(*hid) || !uid) {
2683 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2687 i = early_acpihid_map_size++;
2688 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2689 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2690 early_acpihid_map[i].devid =
2691 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2692 early_acpihid_map[i].cmd_line = true;
2697 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2698 __setup("amd_iommu=", parse_amd_iommu_options);
2699 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2700 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2701 __setup("ivrs_hpet", parse_ivrs_hpet);
2702 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2704 IOMMU_INIT_FINISH(amd_iommu_detect,
2705 gart_iommu_hole_init,
2709 bool amd_iommu_v2_supported(void)
2711 return amd_iommu_v2_present;
2713 EXPORT_SYMBOL(amd_iommu_v2_supported);
2715 /****************************************************************************
2717 * IOMMU EFR Performance Counter support functionality. This code allows
2718 * access to the IOMMU PC functionality.
2720 ****************************************************************************/
2722 u8 amd_iommu_pc_get_max_banks(u16 devid)
2724 struct amd_iommu *iommu;
2727 /* locate the iommu governing the devid */
2728 iommu = amd_iommu_rlookup_table[devid];
2730 ret = iommu->max_banks;
2734 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2736 bool amd_iommu_pc_supported(void)
2738 return amd_iommu_pc_present;
2740 EXPORT_SYMBOL(amd_iommu_pc_supported);
2742 u8 amd_iommu_pc_get_max_counters(u16 devid)
2744 struct amd_iommu *iommu;
2747 /* locate the iommu governing the devid */
2748 iommu = amd_iommu_rlookup_table[devid];
2750 ret = iommu->max_counters;
2754 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2756 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2757 u8 bank, u8 cntr, u8 fxn,
2758 u64 *value, bool is_write)
2763 /* Check for valid iommu and pc register indexing */
2764 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
2767 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2769 /* Limit the offset to the hw defined mmio region aperture */
2770 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2771 (iommu->max_counters << 8) | 0x28);
2772 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2773 (offset > max_offset_lim))
2777 writel((u32)*value, iommu->mmio_base + offset);
2778 writel((*value >> 32), iommu->mmio_base + offset + 4);
2780 *value = readl(iommu->mmio_base + offset + 4);
2782 *value = readl(iommu->mmio_base + offset);
2787 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
2789 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2790 u64 *value, bool is_write)
2792 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2794 /* Make sure the IOMMU PC resource is available */
2795 if (!amd_iommu_pc_present || iommu == NULL)
2798 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,