2 * AMD CPU Microcode Update Driver for Linux
4 * This driver allows to upgrade microcode on F10h AMD
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
8 * 2013-2016 Borislav Petkov <bp@alien8.de>
10 * Author: Peter Oruba <peter.oruba@amd.com>
13 * Tigran Aivazian <aivazian.tigran@gmail.com>
16 * Copyright (C) 2013 Advanced Micro Devices, Inc.
18 * Author: Jacob Shin <jacob.shin@amd.com>
19 * Fixes: Borislav Petkov <bp@suse.de>
21 * Licensed under the terms of the GNU General Public
22 * License version 2. See file COPYING for details.
24 #define pr_fmt(fmt) "microcode: " fmt
26 #include <linux/earlycpio.h>
27 #include <linux/firmware.h>
28 #include <linux/uaccess.h>
29 #include <linux/vmalloc.h>
30 #include <linux/initrd.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
34 #include <asm/microcode_amd.h>
35 #include <asm/microcode.h>
36 #include <asm/processor.h>
37 #include <asm/setup.h>
41 static struct equiv_cpu_entry *equiv_cpu_table;
44 * This points to the current valid container of microcode patches which we will
45 * save from the initrd/builtin before jettisoning its contents. @mc is the
46 * microcode patch we found to match.
49 struct microcode_amd *mc;
56 static u32 ucode_new_rev;
57 static u8 amd_ucode_patch[PATCH_MAX_SIZE];
60 * Microcode patch container file is prepended to the initrd in cpio
61 * format. See Documentation/x86/early-microcode.txt
64 ucode_path[] __maybe_unused = "/*(DEBLOBBED)*/";
66 static u16 find_equiv_id(struct equiv_cpu_entry *equiv_table, u32 sig)
68 for (; equiv_table && equiv_table->installed_cpu; equiv_table++) {
69 if (sig == equiv_table->installed_cpu)
70 return equiv_table->equiv_cpu;
77 * This scans the ucode blob for the proper container as we can have multiple
78 * containers glued together. Returns the equivalence ID from the equivalence
79 * table or 0 if none found.
80 * Returns the amount of bytes consumed while scanning. @desc contains all the
81 * data we're going to use in later stages of the application.
83 static ssize_t parse_container(u8 *ucode, ssize_t size, struct cont_desc *desc)
85 struct equiv_cpu_entry *eq;
86 ssize_t orig_size = size;
87 u32 *hdr = (u32 *)ucode;
91 /* Am I looking at an equivalence table header? */
92 if (hdr[0] != UCODE_MAGIC ||
93 hdr[1] != UCODE_EQUIV_CPU_TABLE_TYPE ||
95 return CONTAINER_HDR_SZ;
99 eq = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
101 /* Find the equivalence ID of our CPU in this table: */
102 eq_id = find_equiv_id(eq, desc->cpuid_1_eax);
104 buf += hdr[2] + CONTAINER_HDR_SZ;
105 size -= hdr[2] + CONTAINER_HDR_SZ;
108 * Scan through the rest of the container to find where it ends. We do
109 * some basic sanity-checking too.
112 struct microcode_amd *mc;
117 if (hdr[0] != UCODE_UCODE_TYPE)
120 /* Sanity-check patch size. */
122 if (patch_size > PATCH_MAX_SIZE)
125 /* Skip patch section header: */
126 buf += SECTION_HDR_SIZE;
127 size -= SECTION_HDR_SIZE;
129 mc = (struct microcode_amd *)buf;
130 if (eq_id == mc->hdr.processor_rev_id) {
131 desc->psize = patch_size;
140 * If we have found a patch (desc->mc), it means we're looking at the
141 * container which has a patch for this CPU so return 0 to mean, @ucode
142 * already points to the proper container. Otherwise, we return the size
143 * we scanned so that we can advance to the next container in the
148 desc->size = orig_size - size;
153 return orig_size - size;
157 * Scan the ucode blob for the proper container as we can have multiple
158 * containers glued together.
160 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
165 ssize_t s = parse_container(ucode, rem, desc);
174 static int __apply_microcode_amd(struct microcode_amd *mc)
178 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code);
180 /* verify patch application was successful */
181 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
182 if (rev != mc->hdr.patch_id)
189 * Early load occurs before we can vmalloc(). So we look for the microcode
190 * patch container file in initrd, traverse equivalent cpu table, look for a
191 * matching microcode patch, and update, all in initrd memory in place.
192 * When vmalloc() is available for use later -- on 64-bit during first AP load,
193 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
194 * load_microcode_amd() to save equivalent cpu table and microcode patches in
195 * kernel heap memory.
197 * Returns true if container found (sets @desc), false otherwise.
200 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch)
202 struct cont_desc desc = { 0 };
203 u8 (*patch)[PATCH_MAX_SIZE];
204 struct microcode_amd *mc;
205 u32 rev, dummy, *new_rev;
209 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
210 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
212 new_rev = &ucode_new_rev;
213 patch = &amd_ucode_patch;
216 desc.cpuid_1_eax = cpuid_1_eax;
218 scan_containers(ucode, size, &desc);
224 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
227 * Allow application of the same revision to pick up SMT-specific
228 * changes even if the revision of the other SMT thread is already
231 if (rev > mc->hdr.patch_id)
234 if (!__apply_microcode_amd(mc)) {
235 *new_rev = mc->hdr.patch_id;
239 memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE));
245 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family)
248 char fw_name[36] = "/*(DEBLOBBED)*/";
251 snprintf(fw_name, sizeof(fw_name),
252 "/*(DEBLOBBED)*/", family);
254 return get_builtin_firmware(cp, fw_name);
260 static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret)
262 struct ucode_cpu_info *uci;
267 if (IS_ENABLED(CONFIG_X86_32)) {
268 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info);
269 path = (const char *)__pa_nodebug(ucode_path);
272 uci = ucode_cpu_info;
277 if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax)))
278 cp = find_microcode_in_initrd(path, use_pa);
280 /* Needed in load_microcode_amd() */
281 uci->cpu_sig.sig = cpuid_1_eax;
286 void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax)
288 struct cpio_data cp = { };
290 __load_ucode_amd(cpuid_1_eax, &cp);
291 if (!(cp.data && cp.size))
294 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true);
297 void load_ucode_amd_ap(unsigned int cpuid_1_eax)
299 struct microcode_amd *mc;
301 u32 *new_rev, rev, dummy;
303 if (IS_ENABLED(CONFIG_X86_32)) {
304 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
305 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
307 mc = (struct microcode_amd *)amd_ucode_patch;
308 new_rev = &ucode_new_rev;
311 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
314 * Check whether a new patch has been saved already. Also, allow application of
315 * the same revision in order to pick up SMT-thread-specific configuration even
316 * if the sibling SMT thread already has an up-to-date revision.
318 if (*new_rev && rev <= mc->hdr.patch_id) {
319 if (!__apply_microcode_amd(mc)) {
320 *new_rev = mc->hdr.patch_id;
325 __load_ucode_amd(cpuid_1_eax, &cp);
326 if (!(cp.data && cp.size))
329 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false);
332 static enum ucode_state
333 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
335 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
337 struct cont_desc desc = { 0 };
338 enum ucode_state ret;
341 cp = find_microcode_in_initrd(ucode_path, false);
342 if (!(cp.data && cp.size))
345 desc.cpuid_1_eax = cpuid_1_eax;
347 scan_containers(cp.data, cp.size, &desc);
351 ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
352 if (ret > UCODE_UPDATED)
358 void reload_ucode_amd(void)
360 struct microcode_amd *mc;
363 mc = (struct microcode_amd *)amd_ucode_patch;
365 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
367 if (rev < mc->hdr.patch_id) {
368 if (!__apply_microcode_amd(mc)) {
369 ucode_new_rev = mc->hdr.patch_id;
370 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
374 static u16 __find_equiv_id(unsigned int cpu)
376 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
377 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
380 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
384 BUG_ON(!equiv_cpu_table);
386 while (equiv_cpu_table[i].equiv_cpu != 0) {
387 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
388 return equiv_cpu_table[i].installed_cpu;
395 * a small, trivial cache of per-family ucode patches
397 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
399 struct ucode_patch *p;
401 list_for_each_entry(p, µcode_cache, plist)
402 if (p->equiv_cpu == equiv_cpu)
407 static void update_cache(struct ucode_patch *new_patch)
409 struct ucode_patch *p;
411 list_for_each_entry(p, µcode_cache, plist) {
412 if (p->equiv_cpu == new_patch->equiv_cpu) {
413 if (p->patch_id >= new_patch->patch_id) {
414 /* we already have the latest patch */
415 kfree(new_patch->data);
420 list_replace(&p->plist, &new_patch->plist);
426 /* no patch found, add it */
427 list_add_tail(&new_patch->plist, µcode_cache);
430 static void free_cache(void)
432 struct ucode_patch *p, *tmp;
434 list_for_each_entry_safe(p, tmp, µcode_cache, plist) {
435 __list_del(p->plist.prev, p->plist.next);
441 static struct ucode_patch *find_patch(unsigned int cpu)
445 equiv_id = __find_equiv_id(cpu);
449 return cache_find_patch(equiv_id);
452 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
454 struct cpuinfo_x86 *c = &cpu_data(cpu);
455 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
456 struct ucode_patch *p;
458 csig->sig = cpuid_eax(0x00000001);
459 csig->rev = c->microcode;
462 * a patch could have been loaded early, set uci->mc so that
463 * mc_bp_resume() can call apply_microcode()
466 if (p && (p->patch_id == csig->rev))
469 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
474 static unsigned int verify_patch_size(u8 family, u32 patch_size,
479 #define F1XH_MPB_MAX_SIZE 2048
480 #define F14H_MPB_MAX_SIZE 1824
481 #define F15H_MPB_MAX_SIZE 4096
482 #define F16H_MPB_MAX_SIZE 3458
483 #define F17H_MPB_MAX_SIZE 3200
487 max_size = F14H_MPB_MAX_SIZE;
490 max_size = F15H_MPB_MAX_SIZE;
493 max_size = F16H_MPB_MAX_SIZE;
496 max_size = F17H_MPB_MAX_SIZE;
499 max_size = F1XH_MPB_MAX_SIZE;
503 if (patch_size > min_t(u32, size, max_size)) {
504 pr_err("patch size mismatch\n");
511 static enum ucode_state apply_microcode_amd(int cpu)
513 struct cpuinfo_x86 *c = &cpu_data(cpu);
514 struct microcode_amd *mc_amd;
515 struct ucode_cpu_info *uci;
516 struct ucode_patch *p;
517 enum ucode_state ret;
520 BUG_ON(raw_smp_processor_id() != cpu);
522 uci = ucode_cpu_info + cpu;
531 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
533 /* need to apply patch? */
534 if (rev >= mc_amd->hdr.patch_id) {
539 if (__apply_microcode_amd(mc_amd)) {
540 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
541 cpu, mc_amd->hdr.patch_id);
545 rev = mc_amd->hdr.patch_id;
548 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
551 uci->cpu_sig.rev = rev;
554 /* Update boot_cpu_data's revision too, if we're on the BSP: */
555 if (c->cpu_index == boot_cpu_data.cpu_index)
556 boot_cpu_data.microcode = rev;
561 static int install_equiv_cpu_table(const u8 *buf)
563 unsigned int *ibuf = (unsigned int *)buf;
564 unsigned int type = ibuf[1];
565 unsigned int size = ibuf[2];
567 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
568 pr_err("empty section/"
569 "invalid type field in container file section header\n");
573 equiv_cpu_table = vmalloc(size);
574 if (!equiv_cpu_table) {
575 pr_err("failed to allocate equivalent CPU table\n");
579 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
581 /* add header length */
582 return size + CONTAINER_HDR_SZ;
585 static void free_equiv_cpu_table(void)
587 vfree(equiv_cpu_table);
588 equiv_cpu_table = NULL;
591 static void cleanup(void)
593 free_equiv_cpu_table();
598 * We return the current size even if some of the checks failed so that
599 * we can skip over the next patch. If we return a negative value, we
600 * signal a grave error like a memory allocation has failed and the
601 * driver cannot continue functioning normally. In such cases, we tear
602 * down everything we've used up so far and exit.
604 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
606 struct microcode_header_amd *mc_hdr;
607 struct ucode_patch *patch;
608 unsigned int patch_size, crnt_size, ret;
612 patch_size = *(u32 *)(fw + 4);
613 crnt_size = patch_size + SECTION_HDR_SIZE;
614 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
615 proc_id = mc_hdr->processor_rev_id;
617 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
619 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
623 /* check if patch is for the current family */
624 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
625 if (proc_fam != family)
628 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
629 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
634 ret = verify_patch_size(family, patch_size, leftover);
636 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
640 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
642 pr_err("Patch allocation failure.\n");
646 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL);
648 pr_err("Patch data allocation failure.\n");
653 INIT_LIST_HEAD(&patch->plist);
654 patch->patch_id = mc_hdr->patch_id;
655 patch->equiv_cpu = proc_id;
657 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
658 __func__, patch->patch_id, proc_id);
660 /* ... and add to cache. */
666 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
669 enum ucode_state ret = UCODE_ERROR;
670 unsigned int leftover;
675 offset = install_equiv_cpu_table(data);
677 pr_err("failed to create equivalent cpu table\n");
681 leftover = size - offset;
683 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
684 pr_err("invalid type field in container file section header\n");
685 free_equiv_cpu_table();
690 crnt_size = verify_and_add_patch(family, fw, leftover);
695 leftover -= crnt_size;
701 static enum ucode_state
702 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
704 struct ucode_patch *p;
705 enum ucode_state ret;
707 /* free old equiv table */
708 free_equiv_cpu_table();
710 ret = __load_microcode_amd(family, data, size);
711 if (ret != UCODE_OK) {
720 if (boot_cpu_data.microcode >= p->patch_id)
726 /* save BSP's matching patch for early load */
730 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
731 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
737 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
740 char fw_name[36] = "/*(DEBLOBBED)*/";
741 struct cpuinfo_x86 *c = &cpu_data(cpu);
742 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
743 enum ucode_state ret = UCODE_NFOUND;
744 const struct firmware *fw;
746 /* reload ucode container only on the boot cpu */
747 if (!refresh_fw || !bsp)
751 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", c->x86);
753 if (reject_firmware_direct(&fw, (const char *)fw_name, device)) {
754 pr_debug("failed to load file %s\n", fw_name);
759 if (*(u32 *)fw->data != UCODE_MAGIC) {
760 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
764 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
767 release_firmware(fw);
773 static enum ucode_state
774 request_microcode_user(int cpu, const void __user *buf, size_t size)
779 static void microcode_fini_cpu_amd(int cpu)
781 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
786 static struct microcode_ops microcode_amd_ops = {
787 .request_microcode_user = request_microcode_user,
788 .request_microcode_fw = request_microcode_amd,
789 .collect_cpu_info = collect_cpu_info_amd,
790 .apply_microcode = apply_microcode_amd,
791 .microcode_fini_cpu = microcode_fini_cpu_amd,
794 struct microcode_ops * __init init_amd_microcode(void)
796 struct cpuinfo_x86 *c = &boot_cpu_data;
798 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
799 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
804 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
807 return µcode_amd_ops;
810 void __exit exit_amd_microcode(void)