2 * ahci.h - Common AHCI SATA definitions and declarations
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
38 #include <linux/pci.h>
39 #include <linux/clk.h>
40 #include <linux/libata.h>
41 #include <linux/phy/phy.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/bits.h>
45 /* Enclosure Management Control */
46 #define EM_CTRL_MSG_TYPE 0x000f0000
48 /* Enclosure Management LED Message Type */
49 #define EM_MSG_LED_HBA_PORT 0x0000000f
50 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
51 #define EM_MSG_LED_VALUE 0xffff0000
52 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
53 #define EM_MSG_LED_VALUE_OFF 0xfff80000
54 #define EM_MSG_LED_VALUE_ON 0x00010000
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
63 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_CMD_TBL_CDB = 0x40,
66 AHCI_CMD_TBL_HDR_SZ = 0x80,
67 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
68 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
69 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
73 (AHCI_RX_FIS_SZ * 16),
74 AHCI_IRQ_ON_SG = BIT(31),
75 AHCI_CMD_ATAPI = BIT(5),
76 AHCI_CMD_WRITE = BIT(6),
77 AHCI_CMD_PREFETCH = BIT(7),
78 AHCI_CMD_RESET = BIT(8),
79 AHCI_CMD_CLR_BUSY = BIT(10),
81 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
93 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
94 HOST_CAP2 = 0x24, /* host capabilities, extended */
97 HOST_RESET = BIT(0), /* reset controller; self-clear */
98 HOST_IRQ_EN = BIT(1), /* global IRQ enable */
99 HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
100 HOST_AHCI_EN = BIT(31), /* AHCI enabled */
103 HOST_CAP_SXS = BIT(5), /* Supports External SATA */
104 HOST_CAP_EMS = BIT(6), /* Enclosure Management support */
105 HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */
106 HOST_CAP_PART = BIT(13), /* Partial state capable */
107 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
108 HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */
109 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
110 HOST_CAP_PMP = BIT(17), /* Port Multiplier support */
111 HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */
112 HOST_CAP_CLO = BIT(24), /* Command List Override support */
113 HOST_CAP_LED = BIT(25), /* Supports activity LED */
114 HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */
115 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
116 HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */
117 HOST_CAP_SNTF = BIT(29), /* SNotification register */
118 HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */
119 HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
122 HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */
123 HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */
124 HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */
125 HOST_CAP2_SDS = BIT(3), /* Support device sleep */
126 HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */
127 HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */
129 /* registers for each SATA port */
130 PORT_LST_ADDR = 0x00, /* command list DMA addr */
131 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
132 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
133 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
134 PORT_IRQ_STAT = 0x10, /* interrupt status */
135 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
136 PORT_CMD = 0x18, /* port command */
137 PORT_TFDATA = 0x20, /* taskfile data */
138 PORT_SIG = 0x24, /* device TF signature */
139 PORT_CMD_ISSUE = 0x38, /* command issue */
140 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
141 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
142 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
143 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
144 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
145 PORT_FBS = 0x40, /* FIS-based Switching */
146 PORT_DEVSLP = 0x44, /* device sleep */
148 /* PORT_IRQ_{STAT,MASK} bits */
149 PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */
150 PORT_IRQ_TF_ERR = BIT(30), /* task file error */
151 PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */
152 PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */
153 PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */
154 PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */
155 PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */
156 PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */
158 PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */
159 PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */
160 PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */
161 PORT_IRQ_CONNECT = BIT(6), /* port connect change status */
162 PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */
163 PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */
164 PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */
165 PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */
166 PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */
167 PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */
169 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
175 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
177 PORT_IRQ_HBUS_DATA_ERR,
178 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
179 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
180 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
183 PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */
184 PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */
185 PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */
186 PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */
187 PORT_CMD_ESP = BIT(21), /* External Sata Port */
188 PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */
189 PORT_CMD_PMP = BIT(17), /* PMP attached */
190 PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */
191 PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */
192 PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */
193 PORT_CMD_CLO = BIT(3), /* Command list override */
194 PORT_CMD_POWER_ON = BIT(2), /* Power up device */
195 PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */
196 PORT_CMD_START = BIT(0), /* Enable port DMA engine */
198 PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */
199 PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */
200 PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */
201 PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */
204 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
205 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
206 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
207 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
208 PORT_FBS_SDE = BIT(2), /* FBS single device error */
209 PORT_FBS_DEC = BIT(1), /* FBS device error clear */
210 PORT_FBS_EN = BIT(0), /* Enable FBS */
212 /* PORT_DEVSLP bits */
213 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
214 PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
215 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
216 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
217 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
218 PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */
219 PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */
221 /* hpriv->flags bits */
223 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
225 AHCI_HFLAG_NO_NCQ = BIT(0),
226 AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */
227 AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */
228 AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */
229 AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */
230 AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */
231 AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */
232 AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */
233 AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */
234 AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */
235 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as
237 AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */
238 AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */
239 AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */
240 AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on
241 port start (wait until
242 error-handling stage) */
243 AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */
244 AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */
246 #ifdef CONFIG_PCI_MSI
247 AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */
249 /* compile out MSI infrastructure */
250 AHCI_HFLAG_MULTI_MSI = 0,
252 AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */
253 AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */
254 AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read
259 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
260 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
262 ICH_MAP = 0x90, /* ICH MAP register */
265 EM_MAX_SLOTS = SATA_PMP_MAX_PORTS,
269 EM_CTL_RST = BIT(9), /* Reset */
270 EM_CTL_TM = BIT(8), /* Transmit Message */
271 EM_CTL_MR = BIT(0), /* Message Received */
272 EM_CTL_ALHD = BIT(26), /* Activity LED */
273 EM_CTL_XMT = BIT(25), /* Transmit Only */
274 EM_CTL_SMB = BIT(24), /* Single Message Buffer */
275 EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */
276 EM_CTL_SES = BIT(18), /* SES-2 messages supported */
277 EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */
278 EM_CTL_LED = BIT(16), /* LED messages supported */
280 /* em message type */
281 EM_MSG_TYPE_LED = BIT(0), /* LED */
282 EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */
283 EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */
284 EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */
287 struct ahci_cmd_hdr {
302 struct ahci_em_priv {
303 enum sw_activity blink_policy;
304 struct timer_list timer;
305 unsigned long saved_activity;
306 unsigned long activity;
307 unsigned long led_state;
310 struct ahci_port_priv {
311 struct ata_link *active_link;
312 struct ahci_cmd_hdr *cmd_slot;
313 dma_addr_t cmd_slot_dma;
315 dma_addr_t cmd_tbl_dma;
317 dma_addr_t rx_fis_dma;
318 /* for NCQ spurious interrupt analysis */
319 unsigned int ncq_saw_d2h:1;
320 unsigned int ncq_saw_dmas:1;
321 unsigned int ncq_saw_sdb:1;
322 spinlock_t lock; /* protects parent ata_port */
323 u32 intr_mask; /* interrupts to enable */
324 bool fbs_supported; /* set iff FBS is supported */
325 bool fbs_enabled; /* set iff FBS is enabled */
326 int fbs_last_dev; /* save FBS.DEV of last FIS */
327 /* enclosure management info per PM slot */
328 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
329 char *irq_desc; /* desc in /proc/interrupts */
332 struct ahci_host_priv {
334 unsigned int flags; /* AHCI_HFLAG_* */
335 u32 force_port_map; /* force port map */
336 u32 mask_port_map; /* mask out particular bits */
338 void __iomem * mmio; /* bus-independent mem map */
339 u32 cap; /* cap to use */
340 u32 cap2; /* cap2 to use */
341 u32 version; /* cached version */
342 u32 port_map; /* port map to use */
343 u32 saved_cap; /* saved initial cap */
344 u32 saved_cap2; /* saved initial cap2 */
345 u32 saved_port_map; /* saved initial port_map */
346 u32 em_loc; /* enclosure management location */
347 u32 em_buf_sz; /* EM buffer size in byte */
348 u32 em_msg_type; /* EM message type */
349 bool got_runtime_pm; /* Did we do pm_runtime_get? */
350 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
351 struct regulator **target_pwrs; /* Optional */
353 * If platform uses PHYs. There is a 1:1 relation between the port number and
354 * the PHY position in this array.
357 unsigned nports; /* Number of ports */
358 void *plat_data; /* Other platform data */
359 unsigned int irq; /* interrupt line */
361 * Optional ahci_start_engine override, if not set this gets set to the
362 * default ahci_start_engine during ahci_save_initial_config, this can
363 * be overridden anytime before the host is activated.
365 void (*start_engine)(struct ata_port *ap);
367 * Optional ahci_stop_engine override, if not set this gets set to the
368 * default ahci_stop_engine during ahci_save_initial_config, this can
369 * be overridden anytime before the host is activated.
371 int (*stop_engine)(struct ata_port *ap);
373 irqreturn_t (*irq_handler)(int irq, void *dev_instance);
375 /* only required for per-port MSI(-X) support */
376 int (*get_irq_vector)(struct ata_host *host,
380 extern int ahci_ignore_sss;
382 extern struct device_attribute *ahci_shost_attrs[];
383 extern struct device_attribute *ahci_sdev_attrs[];
386 * This must be instantiated by the edge drivers. Read the comments
389 #define AHCI_SHT(drv_name) \
390 ATA_NCQ_SHT(drv_name), \
391 .can_queue = AHCI_MAX_CMDS - 1, \
392 .sg_tablesize = AHCI_MAX_SG, \
393 .dma_boundary = AHCI_DMA_BOUNDARY, \
394 .shost_attrs = ahci_shost_attrs, \
395 .sdev_attrs = ahci_sdev_attrs
397 extern struct ata_port_operations ahci_ops;
398 extern struct ata_port_operations ahci_platform_ops;
399 extern struct ata_port_operations ahci_pmp_retry_srst_ops;
401 unsigned int ahci_dev_classify(struct ata_port *ap);
402 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
404 void ahci_save_initial_config(struct device *dev,
405 struct ahci_host_priv *hpriv);
406 void ahci_init_controller(struct ata_host *host);
407 int ahci_reset_controller(struct ata_host *host);
409 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
410 int pmp, unsigned long deadline,
411 int (*check_ready)(struct ata_link *link));
413 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
414 unsigned long deadline, bool *online);
416 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
417 int ahci_stop_engine(struct ata_port *ap);
418 void ahci_start_fis_rx(struct ata_port *ap);
419 void ahci_start_engine(struct ata_port *ap);
420 int ahci_check_ready(struct ata_link *link);
421 int ahci_kick_engine(struct ata_port *ap);
422 int ahci_port_resume(struct ata_port *ap);
423 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
424 struct ata_port_info *pi);
425 int ahci_reset_em(struct ata_host *host);
426 void ahci_print_info(struct ata_host *host, const char *scc_s);
427 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
428 void ahci_error_handler(struct ata_port *ap);
429 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
431 static inline void __iomem *__ahci_port_base(struct ata_host *host,
432 unsigned int port_no)
434 struct ahci_host_priv *hpriv = host->private_data;
435 void __iomem *mmio = hpriv->mmio;
437 return mmio + 0x100 + (port_no * 0x80);
440 static inline void __iomem *ahci_port_base(struct ata_port *ap)
442 return __ahci_port_base(ap->host, ap->port_no);
445 static inline int ahci_nr_ports(u32 cap)
447 return (cap & 0x1f) + 1;