2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
65 /* board IDs by feature in alphabetical order */
74 /* board IDs for specific chipsets in alphabetical order */
81 board_ahci_sb700, /* for SB700 and SB800 */
85 * board IDs for Intel chipsets that support more than 6 ports
86 * *and* end up needing the PCS quirk.
91 board_ahci_mcp_linux = board_ahci_mcp65,
92 board_ahci_mcp67 = board_ahci_mcp65,
93 board_ahci_mcp73 = board_ahci_mcp65,
94 board_ahci_mcp79 = board_ahci_mcp77,
97 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
98 static void ahci_remove_one(struct pci_dev *dev);
99 static void ahci_shutdown_one(struct pci_dev *dev);
100 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
101 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
102 unsigned long deadline);
103 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
104 unsigned long deadline);
105 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
106 static bool is_mcp89_apple(struct pci_dev *pdev);
107 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
108 unsigned long deadline);
110 static int ahci_pci_device_runtime_suspend(struct device *dev);
111 static int ahci_pci_device_runtime_resume(struct device *dev);
112 #ifdef CONFIG_PM_SLEEP
113 static int ahci_pci_device_suspend(struct device *dev);
114 static int ahci_pci_device_resume(struct device *dev);
116 #endif /* CONFIG_PM */
118 static struct scsi_host_template ahci_sht = {
122 static struct ata_port_operations ahci_vt8251_ops = {
123 .inherits = &ahci_ops,
124 .hardreset = ahci_vt8251_hardreset,
127 static struct ata_port_operations ahci_p5wdh_ops = {
128 .inherits = &ahci_ops,
129 .hardreset = ahci_p5wdh_hardreset,
132 static struct ata_port_operations ahci_avn_ops = {
133 .inherits = &ahci_ops,
134 .hardreset = ahci_avn_hardreset,
137 static const struct ata_port_info ahci_port_info[] = {
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
145 [board_ahci_ign_iferr] = {
146 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
152 [board_ahci_mobile] = {
153 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
159 [board_ahci_nomsi] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
166 [board_ahci_noncq] = {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
173 [board_ahci_nosntf] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
180 [board_ahci_yes_fbs] = {
181 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_ops,
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_avn_ops,
194 [board_ahci_mcp65] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
197 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
202 [board_ahci_mcp77] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
209 [board_ahci_mcp89] = {
210 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
218 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
219 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
224 [board_ahci_sb600] = {
225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
226 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
227 AHCI_HFLAG_32BIT_ONLY),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
233 [board_ahci_sb700] = { /* for SB700 and SB800 */
234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_pmp_retry_srst_ops,
240 [board_ahci_vt8251] = {
241 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
242 .flags = AHCI_FLAG_COMMON,
243 .pio_mask = ATA_PIO4,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &ahci_vt8251_ops,
247 [board_ahci_pcs7] = {
248 .flags = AHCI_FLAG_COMMON,
249 .pio_mask = ATA_PIO4,
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &ahci_ops,
255 static const struct pci_device_id ahci_pci_tbl[] = {
257 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
258 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
259 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
260 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
261 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
262 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
263 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
264 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
265 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
266 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
267 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
268 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
269 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
270 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
271 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
272 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
273 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
282 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
284 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
285 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
286 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
287 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
288 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
289 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
291 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
292 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
293 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
294 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
295 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
296 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
318 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
319 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
320 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
321 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
322 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
323 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
324 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
325 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
326 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
327 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
328 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
330 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
331 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
332 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
333 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
334 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
336 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
337 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
338 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
339 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
340 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
341 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
342 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
343 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
344 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
346 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
371 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
375 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
377 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
378 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
379 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
380 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
382 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
383 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
384 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
385 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
386 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
387 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
388 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
389 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
390 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
391 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
392 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
393 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
394 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
395 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
396 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
398 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
399 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
400 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
402 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
405 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
409 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
411 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
412 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
413 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
414 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
415 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
416 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
417 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
418 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426 /* May need to update quirk_jmicron_async_suspend() for additions */
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
439 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
440 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
441 /* AMD is using RAID class only for ahci controllers */
442 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
443 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
446 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
447 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
450 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
537 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
538 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
540 /* ST Microelectronics */
541 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
544 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
545 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
547 .class = PCI_CLASS_STORAGE_SATA_AHCI,
548 .class_mask = 0xffffff,
549 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
551 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
552 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
553 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
554 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
556 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
558 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
562 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
564 .driver_data = board_ahci_yes_fbs },
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
566 .driver_data = board_ahci_yes_fbs },
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
574 .driver_data = board_ahci_yes_fbs },
577 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
578 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
581 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
582 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
583 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
584 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
585 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
586 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
589 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
590 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
592 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
593 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
596 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
598 /* Generic, PCI class code for AHCI */
599 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
600 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
602 { } /* terminate list */
605 static const struct dev_pm_ops ahci_pci_pm_ops = {
606 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
607 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
608 ahci_pci_device_runtime_resume, NULL)
611 static struct pci_driver ahci_pci_driver = {
613 .id_table = ahci_pci_tbl,
614 .probe = ahci_init_one,
615 .remove = ahci_remove_one,
616 .shutdown = ahci_shutdown_one,
618 .pm = &ahci_pci_pm_ops,
622 #if IS_ENABLED(CONFIG_PATA_MARVELL)
623 static int marvell_enable;
625 static int marvell_enable = 1;
627 module_param(marvell_enable, int, 0644);
628 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
630 static int mobile_lpm_policy = -1;
631 module_param(mobile_lpm_policy, int, 0644);
632 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
634 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
635 struct ahci_host_priv *hpriv)
637 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
638 dev_info(&pdev->dev, "JMB361 has only one port\n");
639 hpriv->force_port_map = 1;
643 * Temporary Marvell 6145 hack: PATA port presence
644 * is asserted through the standard AHCI port
645 * presence register, as bit 4 (counting from 0)
647 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
648 if (pdev->device == 0x6121)
649 hpriv->mask_port_map = 0x3;
651 hpriv->mask_port_map = 0xf;
653 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
656 ahci_save_initial_config(&pdev->dev, hpriv);
659 static int ahci_pci_reset_controller(struct ata_host *host)
661 struct pci_dev *pdev = to_pci_dev(host->dev);
662 struct ahci_host_priv *hpriv = host->private_data;
665 rc = ahci_reset_controller(host);
670 * If platform firmware failed to enable ports, try to enable
673 ahci_intel_pcs_quirk(pdev, hpriv);
678 static void ahci_pci_init_controller(struct ata_host *host)
680 struct ahci_host_priv *hpriv = host->private_data;
681 struct pci_dev *pdev = to_pci_dev(host->dev);
682 void __iomem *port_mmio;
686 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
687 if (pdev->device == 0x6121)
691 port_mmio = __ahci_port_base(host, mv);
693 writel(0, port_mmio + PORT_IRQ_MASK);
696 tmp = readl(port_mmio + PORT_IRQ_STAT);
697 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
699 writel(tmp, port_mmio + PORT_IRQ_STAT);
702 ahci_init_controller(host);
705 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
706 unsigned long deadline)
708 struct ata_port *ap = link->ap;
709 struct ahci_host_priv *hpriv = ap->host->private_data;
715 hpriv->stop_engine(ap);
717 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
718 deadline, &online, NULL);
720 hpriv->start_engine(ap);
722 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
724 /* vt8251 doesn't clear BSY on signature FIS reception,
725 * request follow-up softreset.
727 return online ? -EAGAIN : rc;
730 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
731 unsigned long deadline)
733 struct ata_port *ap = link->ap;
734 struct ahci_port_priv *pp = ap->private_data;
735 struct ahci_host_priv *hpriv = ap->host->private_data;
736 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
737 struct ata_taskfile tf;
741 hpriv->stop_engine(ap);
743 /* clear D2H reception area to properly wait for D2H FIS */
744 ata_tf_init(link->device, &tf);
745 tf.command = ATA_BUSY;
746 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
748 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
749 deadline, &online, NULL);
751 hpriv->start_engine(ap);
753 /* The pseudo configuration device on SIMG4726 attached to
754 * ASUS P5W-DH Deluxe doesn't send signature FIS after
755 * hardreset if no device is attached to the first downstream
756 * port && the pseudo device locks up on SRST w/ PMP==0. To
757 * work around this, wait for !BSY only briefly. If BSY isn't
758 * cleared, perform CLO and proceed to IDENTIFY (achieved by
759 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
761 * Wait for two seconds. Devices attached to downstream port
762 * which can't process the following IDENTIFY after this will
763 * have to be reset again. For most cases, this should
764 * suffice while making probing snappish enough.
767 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
770 ahci_kick_engine(ap);
776 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
778 * It has been observed with some SSDs that the timing of events in the
779 * link synchronization phase can leave the port in a state that can not
780 * be recovered by a SATA-hard-reset alone. The failing signature is
781 * SStatus.DET stuck at 1 ("Device presence detected but Phy
782 * communication not established"). It was found that unloading and
783 * reloading the driver when this problem occurs allows the drive
784 * connection to be recovered (DET advanced to 0x3). The critical
785 * component of reloading the driver is that the port state machines are
786 * reset by bouncing "port enable" in the AHCI PCS configuration
787 * register. So, reproduce that effect by bouncing a port whenever we
788 * see DET==1 after a reset.
790 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
791 unsigned long deadline)
793 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
794 struct ata_port *ap = link->ap;
795 struct ahci_port_priv *pp = ap->private_data;
796 struct ahci_host_priv *hpriv = ap->host->private_data;
797 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
798 unsigned long tmo = deadline - jiffies;
799 struct ata_taskfile tf;
805 hpriv->stop_engine(ap);
807 for (i = 0; i < 2; i++) {
810 int port = ap->port_no;
811 struct ata_host *host = ap->host;
812 struct pci_dev *pdev = to_pci_dev(host->dev);
814 /* clear D2H reception area to properly wait for D2H FIS */
815 ata_tf_init(link->device, &tf);
816 tf.command = ATA_BUSY;
817 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
819 rc = sata_link_hardreset(link, timing, deadline, &online,
822 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
823 (sstatus & 0xf) != 1)
826 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
829 pci_read_config_word(pdev, 0x92, &val);
831 pci_write_config_word(pdev, 0x92, val);
832 ata_msleep(ap, 1000);
834 pci_write_config_word(pdev, 0x92, val);
838 hpriv->start_engine(ap);
841 *class = ahci_dev_classify(ap);
843 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
849 static void ahci_pci_disable_interrupts(struct ata_host *host)
851 struct ahci_host_priv *hpriv = host->private_data;
852 void __iomem *mmio = hpriv->mmio;
855 /* AHCI spec rev1.1 section 8.3.3:
856 * Software must disable interrupts prior to requesting a
857 * transition of the HBA to D3 state.
859 ctl = readl(mmio + HOST_CTL);
861 writel(ctl, mmio + HOST_CTL);
862 readl(mmio + HOST_CTL); /* flush */
865 static int ahci_pci_device_runtime_suspend(struct device *dev)
867 struct pci_dev *pdev = to_pci_dev(dev);
868 struct ata_host *host = pci_get_drvdata(pdev);
870 ahci_pci_disable_interrupts(host);
874 static int ahci_pci_device_runtime_resume(struct device *dev)
876 struct pci_dev *pdev = to_pci_dev(dev);
877 struct ata_host *host = pci_get_drvdata(pdev);
880 rc = ahci_pci_reset_controller(host);
883 ahci_pci_init_controller(host);
887 #ifdef CONFIG_PM_SLEEP
888 static int ahci_pci_device_suspend(struct device *dev)
890 struct pci_dev *pdev = to_pci_dev(dev);
891 struct ata_host *host = pci_get_drvdata(pdev);
892 struct ahci_host_priv *hpriv = host->private_data;
894 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
896 "BIOS update required for suspend/resume\n");
900 ahci_pci_disable_interrupts(host);
901 return ata_host_suspend(host, PMSG_SUSPEND);
904 static int ahci_pci_device_resume(struct device *dev)
906 struct pci_dev *pdev = to_pci_dev(dev);
907 struct ata_host *host = pci_get_drvdata(pdev);
910 /* Apple BIOS helpfully mangles the registers on resume */
911 if (is_mcp89_apple(pdev))
912 ahci_mcp89_apple_enable(pdev);
914 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
915 rc = ahci_pci_reset_controller(host);
919 ahci_pci_init_controller(host);
922 ata_host_resume(host);
928 #endif /* CONFIG_PM */
930 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
935 * If the device fixup already set the dma_mask to some non-standard
936 * value, don't extend it here. This happens on STA2X11, for example.
938 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
942 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
943 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
945 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
948 "64-bit DMA enable failed\n");
953 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
955 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
958 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
961 "32-bit consistent DMA enable failed\n");
968 static void ahci_pci_print_info(struct ata_host *host)
970 struct pci_dev *pdev = to_pci_dev(host->dev);
974 pci_read_config_word(pdev, 0x0a, &cc);
975 if (cc == PCI_CLASS_STORAGE_IDE)
977 else if (cc == PCI_CLASS_STORAGE_SATA)
979 else if (cc == PCI_CLASS_STORAGE_RAID)
984 ahci_print_info(host, scc_s);
987 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
988 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
989 * support PMP and the 4726 either directly exports the device
990 * attached to the first downstream port or acts as a hardware storage
991 * controller and emulate a single ATA device (can be RAID 0/1 or some
992 * other configuration).
994 * When there's no device attached to the first downstream port of the
995 * 4726, "Config Disk" appears, which is a pseudo ATA device to
996 * configure the 4726. However, ATA emulation of the device is very
997 * lame. It doesn't send signature D2H Reg FIS after the initial
998 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1000 * The following function works around the problem by always using
1001 * hardreset on the port and not depending on receiving signature FIS
1002 * afterward. If signature FIS isn't received soon, ATA class is
1003 * assumed without follow-up softreset.
1005 static void ahci_p5wdh_workaround(struct ata_host *host)
1007 static const struct dmi_system_id sysids[] = {
1009 .ident = "P5W DH Deluxe",
1011 DMI_MATCH(DMI_SYS_VENDOR,
1012 "ASUSTEK COMPUTER INC"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1018 struct pci_dev *pdev = to_pci_dev(host->dev);
1020 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1021 dmi_check_system(sysids)) {
1022 struct ata_port *ap = host->ports[1];
1024 dev_info(&pdev->dev,
1025 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1027 ap->ops = &ahci_p5wdh_ops;
1028 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1033 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1034 * booting in BIOS compatibility mode. We restore the registers but not ID.
1036 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1040 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1042 pci_read_config_dword(pdev, 0xf8, &val);
1044 /* the following changes the device ID, but appears not to affect function */
1045 /* val = (val & ~0xf0000000) | 0x80000000; */
1046 pci_write_config_dword(pdev, 0xf8, val);
1048 pci_read_config_dword(pdev, 0x54c, &val);
1050 pci_write_config_dword(pdev, 0x54c, val);
1052 pci_read_config_dword(pdev, 0x4a4, &val);
1055 pci_write_config_dword(pdev, 0x4a4, val);
1057 pci_read_config_dword(pdev, 0x54c, &val);
1059 pci_write_config_dword(pdev, 0x54c, val);
1061 pci_read_config_dword(pdev, 0xf8, &val);
1062 val &= ~(1 << 0x1b);
1063 pci_write_config_dword(pdev, 0xf8, val);
1066 static bool is_mcp89_apple(struct pci_dev *pdev)
1068 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1069 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1070 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1071 pdev->subsystem_device == 0xcb89;
1074 /* only some SB600 ahci controllers can do 64bit DMA */
1075 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1077 static const struct dmi_system_id sysids[] = {
1079 * The oldest version known to be broken is 0901 and
1080 * working is 1501 which was released on 2007-10-26.
1081 * Enable 64bit DMA on 1501 and anything newer.
1083 * Please read bko#9412 for more info.
1086 .ident = "ASUS M2A-VM",
1088 DMI_MATCH(DMI_BOARD_VENDOR,
1089 "ASUSTeK Computer INC."),
1090 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1092 .driver_data = "20071026", /* yyyymmdd */
1095 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1096 * support 64bit DMA.
1098 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1099 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1100 * This spelling mistake was fixed in BIOS version 1.5, so
1101 * 1.5 and later have the Manufacturer as
1102 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1103 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1105 * BIOS versions earlier than 1.9 had a Board Product Name
1106 * DMI field of "MS-7376". This was changed to be
1107 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1108 * match on DMI_BOARD_NAME of "MS-7376".
1111 .ident = "MSI K9A2 Platinum",
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "MICRO-STAR INTER"),
1115 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1119 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1122 * This board also had the typo mentioned above in the
1123 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1124 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1127 .ident = "MSI K9AGM2",
1129 DMI_MATCH(DMI_BOARD_VENDOR,
1130 "MICRO-STAR INTER"),
1131 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1135 * All BIOS versions for the Asus M3A support 64bit DMA.
1136 * (all release versions from 0301 to 1206 were tested)
1139 .ident = "ASUS M3A",
1141 DMI_MATCH(DMI_BOARD_VENDOR,
1142 "ASUSTeK Computer INC."),
1143 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1148 const struct dmi_system_id *match;
1149 int year, month, date;
1152 match = dmi_first_match(sysids);
1153 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1157 if (!match->driver_data)
1160 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1161 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1163 if (strcmp(buf, match->driver_data) >= 0)
1166 dev_warn(&pdev->dev,
1167 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1173 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1177 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1179 static const struct dmi_system_id broken_systems[] = {
1181 .ident = "HP Compaq nx6310",
1183 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1184 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1186 /* PCI slot number of the controller */
1187 .driver_data = (void *)0x1FUL,
1190 .ident = "HP Compaq 6720s",
1192 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1193 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1195 /* PCI slot number of the controller */
1196 .driver_data = (void *)0x1FUL,
1199 { } /* terminate list */
1201 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1204 unsigned long slot = (unsigned long)dmi->driver_data;
1205 /* apply the quirk only to on-board controllers */
1206 return slot == PCI_SLOT(pdev->devfn);
1212 static bool ahci_broken_suspend(struct pci_dev *pdev)
1214 static const struct dmi_system_id sysids[] = {
1216 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1217 * to the harddisk doesn't become online after
1218 * resuming from STR. Warn and fail suspend.
1220 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1222 * Use dates instead of versions to match as HP is
1223 * apparently recycling both product and version
1226 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1231 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1232 DMI_MATCH(DMI_PRODUCT_NAME,
1233 "HP Pavilion dv4 Notebook PC"),
1235 .driver_data = "20090105", /* F.30 */
1240 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1241 DMI_MATCH(DMI_PRODUCT_NAME,
1242 "HP Pavilion dv5 Notebook PC"),
1244 .driver_data = "20090506", /* F.16 */
1249 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1250 DMI_MATCH(DMI_PRODUCT_NAME,
1251 "HP Pavilion dv6 Notebook PC"),
1253 .driver_data = "20090423", /* F.21 */
1258 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1259 DMI_MATCH(DMI_PRODUCT_NAME,
1260 "HP HDX18 Notebook PC"),
1262 .driver_data = "20090430", /* F.23 */
1265 * Acer eMachines G725 has the same problem. BIOS
1266 * V1.03 is known to be broken. V3.04 is known to
1267 * work. Between, there are V1.06, V2.06 and V3.03
1268 * that we don't have much idea about. For now,
1269 * blacklist anything older than V3.04.
1271 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1276 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1277 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1279 .driver_data = "20091216", /* V3.04 */
1281 { } /* terminate list */
1283 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1284 int year, month, date;
1287 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1290 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1291 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1293 return strcmp(buf, dmi->driver_data) < 0;
1296 static bool ahci_broken_lpm(struct pci_dev *pdev)
1298 static const struct dmi_system_id sysids[] = {
1299 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1302 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1303 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1305 .driver_data = "20180406", /* 1.31 */
1309 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1310 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1312 .driver_data = "20180420", /* 1.28 */
1316 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1317 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1319 .driver_data = "20180315", /* 1.33 */
1323 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1324 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1327 * Note date based on release notes, 2.35 has been
1328 * reported to be good, but I've been unable to get
1329 * a hold of the reporter to get the DMI BIOS date.
1332 .driver_data = "20180310", /* 2.35 */
1334 { } /* terminate list */
1336 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1337 int year, month, date;
1343 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1344 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1346 return strcmp(buf, dmi->driver_data) < 0;
1349 static bool ahci_broken_online(struct pci_dev *pdev)
1351 #define ENCODE_BUSDEVFN(bus, slot, func) \
1352 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1353 static const struct dmi_system_id sysids[] = {
1355 * There are several gigabyte boards which use
1356 * SIMG5723s configured as hardware RAID. Certain
1357 * 5723 firmware revisions shipped there keep the link
1358 * online but fail to answer properly to SRST or
1359 * IDENTIFY when no device is attached downstream
1360 * causing libata to retry quite a few times leading
1361 * to excessive detection delay.
1363 * As these firmwares respond to the second reset try
1364 * with invalid device signature, considering unknown
1365 * sig as offline works around the problem acceptably.
1368 .ident = "EP45-DQ6",
1370 DMI_MATCH(DMI_BOARD_VENDOR,
1371 "Gigabyte Technology Co., Ltd."),
1372 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1374 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1377 .ident = "EP45-DS5",
1379 DMI_MATCH(DMI_BOARD_VENDOR,
1380 "Gigabyte Technology Co., Ltd."),
1381 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1383 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1385 { } /* terminate list */
1387 #undef ENCODE_BUSDEVFN
1388 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1394 val = (unsigned long)dmi->driver_data;
1396 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1399 static bool ahci_broken_devslp(struct pci_dev *pdev)
1401 /* device with broken DEVSLP but still showing SDS capability */
1402 static const struct pci_device_id ids[] = {
1403 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1407 return pci_match_id(ids, pdev);
1410 #ifdef CONFIG_ATA_ACPI
1411 static void ahci_gtf_filter_workaround(struct ata_host *host)
1413 static const struct dmi_system_id sysids[] = {
1415 * Aspire 3810T issues a bunch of SATA enable commands
1416 * via _GTF including an invalid one and one which is
1417 * rejected by the device. Among the successful ones
1418 * is FPDMA non-zero offset enable which when enabled
1419 * only on the drive side leads to NCQ command
1420 * failures. Filter it out.
1423 .ident = "Aspire 3810T",
1425 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1426 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1428 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1432 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1433 unsigned int filter;
1439 filter = (unsigned long)dmi->driver_data;
1440 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1441 filter, dmi->ident);
1443 for (i = 0; i < host->n_ports; i++) {
1444 struct ata_port *ap = host->ports[i];
1445 struct ata_link *link;
1446 struct ata_device *dev;
1448 ata_for_each_link(link, ap, EDGE)
1449 ata_for_each_dev(dev, link, ALL)
1450 dev->gtf_filter |= filter;
1454 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1459 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1460 * as DUMMY, or detected but eventually get a "link down" and never get up
1461 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1462 * port_map may hold a value of 0x00.
1464 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1465 * and can significantly reduce the occurrence of the problem.
1467 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1469 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1470 struct pci_dev *pdev)
1472 static const struct dmi_system_id sysids[] = {
1474 .ident = "Acer Switch Alpha 12",
1476 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1477 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1483 if (dmi_check_system(sysids)) {
1484 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1485 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1486 hpriv->port_map = 0x7;
1487 hpriv->cap = 0xC734FF02;
1494 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1495 * Workaround is to make sure all pending IRQs are served before leaving
1498 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1500 struct ata_host *host = dev_instance;
1501 struct ahci_host_priv *hpriv;
1502 unsigned int rc = 0;
1504 u32 irq_stat, irq_masked;
1505 unsigned int handled = 1;
1508 hpriv = host->private_data;
1510 irq_stat = readl(mmio + HOST_IRQ_STAT);
1515 irq_masked = irq_stat & hpriv->port_map;
1516 spin_lock(&host->lock);
1517 rc = ahci_handle_port_intr(host, irq_masked);
1520 writel(irq_stat, mmio + HOST_IRQ_STAT);
1521 irq_stat = readl(mmio + HOST_IRQ_STAT);
1522 spin_unlock(&host->lock);
1526 return IRQ_RETVAL(handled);
1530 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1531 struct ahci_host_priv *hpriv)
1537 * Check if this device might have remapped nvme devices.
1539 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1540 pci_resource_len(pdev, bar) < SZ_512K ||
1541 bar != AHCI_PCI_BAR_STANDARD ||
1542 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1545 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1546 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1547 if ((cap & (1 << i)) == 0)
1549 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1550 != PCI_CLASS_STORAGE_EXPRESS)
1553 /* We've found a remapped device */
1560 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1561 dev_warn(&pdev->dev,
1562 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1565 * Don't rely on the msi-x capability in the remap case,
1566 * share the legacy interrupt across ahci and remapped devices.
1568 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1571 static int ahci_get_irq_vector(struct ata_host *host, int port)
1573 return pci_irq_vector(to_pci_dev(host->dev), port);
1576 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1577 struct ahci_host_priv *hpriv)
1581 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1585 * If number of MSIs is less than number of ports then Sharing Last
1586 * Message mode could be enforced. In this case assume that advantage
1587 * of multipe MSIs is negated and use single MSI mode instead.
1590 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1591 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1593 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1594 hpriv->get_irq_vector = ahci_get_irq_vector;
1595 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1600 * Fallback to single MSI mode if the controller
1601 * enforced MRSM mode.
1604 "ahci: MRSM is on, fallback to single MSI\n");
1605 pci_free_irq_vectors(pdev);
1610 * If the host is not capable of supporting per-port vectors, fall
1611 * back to single MSI before finally attempting single MSI-X.
1613 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1616 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1619 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1620 struct ahci_host_priv *hpriv)
1622 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1625 /* Ignore processing for non mobile platforms */
1626 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1629 /* user modified policy via module param */
1630 if (mobile_lpm_policy != -1) {
1631 policy = mobile_lpm_policy;
1636 if (policy > ATA_LPM_MED_POWER &&
1637 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1638 if (hpriv->cap & HOST_CAP_PART)
1639 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1640 else if (hpriv->cap & HOST_CAP_SSC)
1641 policy = ATA_LPM_MIN_POWER;
1646 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1647 ap->target_lpm_policy = policy;
1650 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1652 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1656 * Only apply the 6-port PCS quirk for known legacy platforms.
1658 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1661 /* Skip applying the quirk on Denverton and beyond */
1662 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1666 * port_map is determined from PORTS_IMPL PCI register which is
1667 * implemented as write or write-once register. If the register
1668 * isn't programmed, ahci automatically generates it from number
1669 * of ports, which is good enough for PCS programming. It is
1670 * otherwise expected that platform firmware enables the ports
1671 * before the OS boots.
1673 pci_read_config_word(pdev, PCS_6, &tmp16);
1674 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1675 tmp16 |= hpriv->port_map;
1676 pci_write_config_word(pdev, PCS_6, tmp16);
1680 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1682 unsigned int board_id = ent->driver_data;
1683 struct ata_port_info pi = ahci_port_info[board_id];
1684 const struct ata_port_info *ppi[] = { &pi, NULL };
1685 struct device *dev = &pdev->dev;
1686 struct ahci_host_priv *hpriv;
1687 struct ata_host *host;
1689 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1693 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1695 ata_print_version_once(&pdev->dev, DRV_VERSION);
1697 /* The AHCI driver can only drive the SATA ports, the PATA driver
1698 can drive them all so if both drivers are selected make sure
1699 AHCI stays out of the way */
1700 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1703 /* Apple BIOS on MCP89 prevents us using AHCI */
1704 if (is_mcp89_apple(pdev))
1705 ahci_mcp89_apple_enable(pdev);
1707 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1708 * At the moment, we can only use the AHCI mode. Let the users know
1709 * that for SAS drives they're out of luck.
1711 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1712 dev_info(&pdev->dev,
1713 "PDC42819 can only drive SATA devices with this driver\n");
1715 /* Some devices use non-standard BARs */
1716 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1717 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1718 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1719 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1720 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1721 if (pdev->device == 0xa01c)
1722 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1723 if (pdev->device == 0xa084)
1724 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1727 /* acquire resources */
1728 rc = pcim_enable_device(pdev);
1732 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1733 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1736 /* ICH6s share the same PCI ID for both piix and ahci
1737 * modes. Enabling ahci mode while MAP indicates
1738 * combined mode is a bad idea. Yield to ata_piix.
1740 pci_read_config_byte(pdev, ICH_MAP, &map);
1742 dev_info(&pdev->dev,
1743 "controller is in combined mode, can't enable AHCI mode\n");
1748 /* AHCI controllers often implement SFF compatible interface.
1749 * Grab all PCI BARs just in case.
1751 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1753 pcim_pin_device(pdev);
1757 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1760 hpriv->flags |= (unsigned long)pi.private_data;
1762 /* MCP65 revision A1 and A2 can't do MSI */
1763 if (board_id == board_ahci_mcp65 &&
1764 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1765 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1767 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1768 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1769 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1771 /* only some SB600s can do 64bit DMA */
1772 if (ahci_sb600_enable_64bit(pdev))
1773 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1775 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1777 /* detect remapped nvme devices */
1778 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1780 /* must set flag prior to save config in order to take effect */
1781 if (ahci_broken_devslp(pdev))
1782 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1785 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1786 hpriv->irq_handler = ahci_thunderx_irq_handler;
1789 /* save initial config */
1790 ahci_pci_save_initial_config(pdev, hpriv);
1793 if (hpriv->cap & HOST_CAP_NCQ) {
1794 pi.flags |= ATA_FLAG_NCQ;
1796 * Auto-activate optimization is supposed to be
1797 * supported on all AHCI controllers indicating NCQ
1798 * capability, but it seems to be broken on some
1799 * chipsets including NVIDIAs.
1801 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1802 pi.flags |= ATA_FLAG_FPDMA_AA;
1805 * All AHCI controllers should be forward-compatible
1806 * with the new auxiliary field. This code should be
1807 * conditionalized if any buggy AHCI controllers are
1810 pi.flags |= ATA_FLAG_FPDMA_AUX;
1813 if (hpriv->cap & HOST_CAP_PMP)
1814 pi.flags |= ATA_FLAG_PMP;
1816 ahci_set_em_messages(hpriv, &pi);
1818 if (ahci_broken_system_poweroff(pdev)) {
1819 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1820 dev_info(&pdev->dev,
1821 "quirky BIOS, skipping spindown on poweroff\n");
1824 if (ahci_broken_lpm(pdev)) {
1825 pi.flags |= ATA_FLAG_NO_LPM;
1826 dev_warn(&pdev->dev,
1827 "BIOS update required for Link Power Management support\n");
1830 if (ahci_broken_suspend(pdev)) {
1831 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1832 dev_warn(&pdev->dev,
1833 "BIOS update required for suspend/resume\n");
1836 if (ahci_broken_online(pdev)) {
1837 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1838 dev_info(&pdev->dev,
1839 "online status unreliable, applying workaround\n");
1843 /* Acer SA5-271 workaround modifies private_data */
1844 acer_sa5_271_workaround(hpriv, pdev);
1846 /* CAP.NP sometimes indicate the index of the last enabled
1847 * port, at other times, that of the last possible port, so
1848 * determining the maximum port number requires looking at
1849 * both CAP.NP and port_map.
1851 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1853 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1856 host->private_data = hpriv;
1858 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1859 /* legacy intx interrupts */
1862 hpriv->irq = pci_irq_vector(pdev, 0);
1864 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1865 host->flags |= ATA_HOST_PARALLEL_SCAN;
1867 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1869 if (pi.flags & ATA_FLAG_EM)
1870 ahci_reset_em(host);
1872 for (i = 0; i < host->n_ports; i++) {
1873 struct ata_port *ap = host->ports[i];
1875 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1876 ata_port_pbar_desc(ap, ahci_pci_bar,
1877 0x100 + ap->port_no * 0x80, "port");
1879 /* set enclosure management message type */
1880 if (ap->flags & ATA_FLAG_EM)
1881 ap->em_message_type = hpriv->em_msg_type;
1883 ahci_update_initial_lpm_policy(ap, hpriv);
1885 /* disabled/not-implemented port */
1886 if (!(hpriv->port_map & (1 << i)))
1887 ap->ops = &ata_dummy_port_ops;
1890 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1891 ahci_p5wdh_workaround(host);
1893 /* apply gtf filter quirk */
1894 ahci_gtf_filter_workaround(host);
1896 /* initialize adapter */
1897 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1901 rc = ahci_pci_reset_controller(host);
1905 ahci_pci_init_controller(host);
1906 ahci_pci_print_info(host);
1908 pci_set_master(pdev);
1910 rc = ahci_host_activate(host, &ahci_sht);
1914 pm_runtime_put_noidle(&pdev->dev);
1918 static void ahci_shutdown_one(struct pci_dev *pdev)
1920 ata_pci_shutdown_one(pdev);
1923 static void ahci_remove_one(struct pci_dev *pdev)
1925 pm_runtime_get_noresume(&pdev->dev);
1926 ata_pci_remove_one(pdev);
1929 module_pci_driver(ahci_pci_driver);
1931 MODULE_AUTHOR("Jeff Garzik");
1932 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1933 MODULE_LICENSE("GPL");
1934 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1935 MODULE_VERSION(DRV_VERSION);