1 .. SPDX-License-Identifier: GPL-2.0
7 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
8 The plug and play ID of a Chrome OS ACPI device is GGL0001. GGL is a valid PNP ID of Google.
9 PNP ID can be used with the ACPI devices according to the guidelines. The following ACPI
10 objects are supported:
12 .. flat-table:: Supported ACPI Objects
20 - Chrome OS switch positions
23 - Chrome OS hardware ID
26 - Chrome OS firmware version
29 - Chrome OS read-only firmware version
32 - Chrome OS boot information
35 - Chrome OS GPIO assignments
38 - Chrome OS NVRAM locations
41 - Chrome OS verified boot data
44 - Chrome OS flashmap base address
47 - Chrome OS method list
49 CHSW (Chrome OS switch positions)
50 =================================
51 This control method returns the switch positions for Chrome OS specific hardware switches.
59 An integer containing the switch positions as bitfields:
65 - Recovery button was pressed when x86 firmware booted.
68 - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
69 rewritable; otherwise optional)
72 - Developer switch was enabled when x86 firmware booted.
75 - Firmware write protection was disabled when x86 firmware booted. (required if
76 firmware write protection is controlled through x86 BIOS; otherwise optional)
78 All other bits are reserved and should be set to 0.
80 HWID (Chrome OS hardware ID)
81 ============================
82 This control method returns the hardware ID for the Chromebook.
90 A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
93 Note that the hardware ID can be up to 256 characters long, including the terminating null.
95 FWID (Chrome OS firmware version)
96 =================================
97 This control method returns the firmware version for the rewritable portion of the main
106 A null-terminated ASCII string containing the complete firmware version for the rewritable
107 portion of the main processor firmware.
109 FRID (Chrome OS read-only firmware version)
110 ===========================================
111 This control method returns the firmware version for the read-only portion of the main
120 A null-terminated ASCII string containing the complete firmware version for the read-only
121 (bootstrap + recovery ) portion of the main processor firmware.
123 BINF (Chrome OS boot information)
124 =================================
125 This control method returns information about the current boot.
140 Active Main Firmware Type
154 - Set to 256 (0x100). This indicates this field is no longer used.
158 - Set to 256 (0x100). This indicates this field is no longer used.
160 * - Active EC firmware
162 - The EC firmware which was used during boot.
164 - 0 - Read-only (recovery) firmware
165 - 1 - Rewritable firmware.
167 Set to 0 if EC firmware is always read-only.
169 * - Active Main Firmware Type
171 - The main firmware type which was used during boot.
176 - 3 - netboot (factory installation only)
178 Other values are reserved.
182 - Set to 256 (0x100). This indicates this field is no longer used.
184 GPIO (Chrome OS GPIO assignments)
185 =================================
186 This control method returns information about Chrome OS specific GPIO assignments for
187 Chrome OS hardware, so the kernel can directly control that hardware.
199 // First GPIO assignment
202 Controller Offset //DWORD
203 Controller Name //ASCIIZ
207 // Last GPIO assignment
210 Controller Offset //DWORD
211 Controller Name //ASCIIZ
215 Where ASCIIZ means a null-terminated ASCII string.
227 - Type of GPIO signal
229 - 0x00000001 - Recovery button
230 - 0x00000002 - Developer mode switch
231 - 0x00000003 - Firmware write protection switch
232 - 0x00000100 - Debug header GPIO 0
234 - 0x000001FF - Debug header GPIO 255
236 Other values are reserved.
240 - Signal attributes as bitfields:
242 - 0x00000001 - Signal is active-high (for button, a GPIO value
243 of 1 means the button is pressed; for switches, a GPIO value
244 of 1 means the switch is enabled). If this bit is 0, the signal
245 is active low. Set to 0 for debug header GPIOs.
247 * - Controller Offset
249 - GPIO number on the specified controller.
253 - Name of the controller for the GPIO.
254 Currently supported names:
255 "NM10" - Intel NM10 chip
257 VBNV (Chrome OS NVRAM locations)
258 ================================
259 This control method returns information about the NVRAM (CMOS) locations used to
260 communicate with the BIOS.
271 NV Storage Block Offset //DWORD
272 NV Storage Block Size //DWORD
283 * - NV Storage Block Offset
285 - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
286 the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
289 * - NV Storage Block Size
291 - Size in bytes of the verified boot non-volatile storage block.
293 FMAP (Chrome OS flashmap address)
294 =================================
295 This control method returns the physical memory address of the start of the main processor
304 A DWORD containing the physical memory address of the start of the main processor firmware
307 VDTA (Chrome OS verified boot data)
308 ===================================
309 This control method returns the verified boot data block shared between the firmware
310 verification step and the kernel verification step.
318 A buffer containing the verified boot data block.
320 MECK (Management Engine Checksum)
321 =================================
322 This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
323 Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
324 the ME firmware has not changed. If Management Engine is not present, or if the firmware was
325 unable to read the extended registers, this buffer can be zero.
333 A buffer containing the ME hash.
335 MLST (Chrome OS method list)
336 ============================
337 This control method returns a list of the other control methods supported by the Chrome OS
346 A package containing a list of null-terminated ASCII strings, one for each control method
347 supported by the Chrome OS hardware device, not including the MLST method itself.
348 For this version of the specification, the result is: