4 //#include "hw/apb_map.h"
5 //#include "hw/rtc_reg.h"
6 //#include "hw/mbox_reg.h"
9 * Basic types, appropriate for both
10 * the 32-bit MIPS core on AR6000 and
11 * the 32-bit XTensa core on AR6002
13 typedef signed char A_CHAR;
14 typedef signed char A_INT8;
15 typedef unsigned char A_UINT8;
16 typedef unsigned char A_UCHAR;
17 typedef short A_INT16;
18 typedef unsigned short A_UINT16;
20 typedef unsigned int A_UINT32;
21 typedef long long A_INT64;
22 typedef unsigned long long A_UINT64;
24 typedef unsigned int ULONG;
25 typedef ULONG A_ULONG;
26 typedef A_ULONG A_ADDR;
29 //#include "targaddrs.h"
32 * Some platform-specific macros and constants that may needed
37 * AR6001/MIPS uses a cache line size of 16 Bytes.
38 * AR6002/Xtensa has no caches; but existing code assumes
39 * that this constant is non-zero. To avoid code complexity
40 * and possibly subtle bugs we define a bogus cache
41 * line size for Xtensa that matches MIPs'.
43 #define A_CACHE_LINE_SIZE 16
46 #define A_MIPS_KSEG_UNCACHED 0xa0000000
47 #define A_MIPS_KSEG_CACHED 0x80000000
48 #define A_MIPS_KSEG_MASK 0xe0000000
51 * Convert a cached virtual address or a CPU physical address into
52 * an uncached virtual address.
54 #define A_UNCACHED_ADDR(addr) \
55 ((void *)(((A_UINT32)(addr)) | A_MIPS_KSEG_UNCACHED))
58 * Convert an uncached or CPU physical address into
59 * a cached virtual address.
61 #define A_CACHED_ADDR(addr) \
62 ((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED))
64 /* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */
65 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr)))
67 #define A_SOC_ADDR_WRITE(addr, val) \
69 (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) = (A_UINT32)(val); \
72 #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(addr)
73 #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(addr)
74 #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(addr)
75 #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(addr)
76 #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(addr)
77 #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(addr)
78 #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(addr)
79 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(addr)
81 #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
82 #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
83 #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
84 #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
85 #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
86 #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
87 #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
88 #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
92 #define A_UNCACHED_ADDR(addr) (addr)
93 #define A_CACHED_ADDR(addr) (addr)
95 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr)))
97 #define A_SOC_ADDR_WRITE(addr, val) \
99 (*((volatile A_UINT32 *)(addr))) = (A_UINT32)(val); \
102 #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(RTC_BASE_ADDRESS|(A_UINT32)(addr))
103 #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(VMC_BASE_ADDRESS|(A_UINT32)(addr))
104 #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(UART_BASE_ADDRESS|(A_UINT32)(addr))
105 #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(SI_BASE_ADDRESS|(A_UINT32)(addr))
106 #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(GPIO_BASE_ADDRESS|(A_UINT32)(addr))
107 #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(MBOX_BASE_ADDRESS|(A_UINT32)(addr))
108 #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(MAC_BASE_ADDRESS|(A_UINT32)(addr))
109 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr))
111 #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(RTC_BASE_ADDRESS|(A_UINT32)(addr), (val))
112 #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(VMC_BASE_ADDRESS|(A_UINT32)(addr), (val))
113 #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(UART_BASE_ADDRESS|(A_UINT32)(addr), (val))
114 #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(SI_BASE_ADDRESS|(A_UINT32)(addr), (val))
115 #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(GPIO_BASE_ADDRESS|(A_UINT32)(addr), (val))
116 #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MBOX_BASE_ADDRESS|(A_UINT32)(addr), (val))
117 #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MAC_BASE_ADDRESS|(A_UINT32)(addr), (val))
118 #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr), (val))
123 * Sleep/stay awake control.
124 * It is the caller's responsibility to guarantee atomicity.
127 typedef A_UINT32 A_old_sleep_t;
129 #define A_SYSTEM_SLEEP_DISABLE(pOldSystemSleep) \
131 *(pOldSystemSleep) = A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); \
132 A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, \
133 *(pOldSystemSleep) | SYSTEM_SLEEP_DISABLE_MASK); \
134 (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \
137 #define A_SYSTEM_SLEEP_RESTORE(OldSystemSleep) \
139 A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, (OldSystemSleep)); \
140 (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \
145 * AR6K-specific High Frequency Timestamp support.
146 * This is intended for use as a performance tool, and
147 * is not to be used in normal operation.
150 A_UINT32 highfreq; /* ~40MHz resolution */
151 A_UINT32 lowfreq; /* ~32KHz resolution */
155 * Enable HighFrequency timer.
156 * Normally, we keep this OFF in order to save power.
158 #define HF_TIMER_CONTROL_START_MASK HF_TIMER_CONTROL_ON_MASK
159 #define A_TIMESTAMP_ENABLE() \
161 A_RTC_REG_WRITE(HF_TIMER_ADDRESS, (40000000/32768)<<12); \
162 A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, \
163 HF_TIMER_CONTROL_START_MASK | \
164 HF_TIMER_CONTROL_AUTO_RESTART_MASK | \
165 HF_TIMER_CONTROL_RESET_MASK); \
169 * Turn it OFF when you're done:
171 #define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0)
174 * Get a timestamp. It's the caller's responsibility to
175 * guarantee atomicity of the two reads, if needed.
177 #define A_TIMESTAMP(pTimestamp) \
179 (pTimestamp)->highfreq = A_RTC_REG_READ(HF_TIMER_COUNT_ADDRESS); \
180 (pTimestamp)->lowfreq = A_RTC_REG_READ(HF_LF_COUNT_ADDRESS); \
184 * Supported reference clock speeds.
186 * Note: MAC HAL code has multiple tables indexed by these values,
187 * so do not rearrange them. Add any new refclk values at the end.
190 AR6K_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
191 AR6K_REFCLK_19_2_MHZ = 0,
192 AR6K_REFCLK_26_MHZ = 1,
193 AR6K_REFCLK_40_MHZ = 2,
194 AR6K_REFCLK_52_MHZ = 3,
195 AR6K_REFCLK_38_4_MHZ = 4,
196 AR6K_REFCLK_24_MHZ = 5,
199 #define A_REFCLK_UNKNOWN AR6K_REFCLK_UNKNOWN
200 #define A_REFCLK_19_2_MHZ AR6K_REFCLK_19_2_MHZ
201 #define A_REFCLK_26_MHZ AR6K_REFCLK_26_MHZ
202 #define A_REFCLK_40_MHZ AR6K_REFCLK_40_MHZ
203 #define A_REFCLK_52_MHZ AR6K_REFCLK_52_MHZ
204 #define A_REFCLK_38_4_MHZ AR6K_REFCLK_38_4_MHZ
205 #define A_REFCLK_24_MHZ AR6K_REFCLK_24_MHZ
207 /* System defaults to 2.4GHz settings */
208 #define A_BAND_DEFAULT A_BAND_24GHZ
211 #define FLASH_ADDR(n) AR6000_FLASH_ADDR(n)
215 #define HOST_INTEREST ((struct host_interest_s *)AR6002_HOST_INTEREST_ADDRESS)
217 #define HOST_INTEREST ((struct host_interest_s *)AR6001_HOST_INTEREST_ADDRESS)
220 #define AR6K_OPTION_TEST(option) \
221 (A_MBOX_REG_READ(LOCAL_SCRATCH_ADDRESS) & (option))
225 #endif /* __AR6K_SOC_H__ */