3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_SUPPORTS_MEMORY_FAILURE
27 select ARCH_SUPPORTS_ATOMIC_RMW
28 select ARCH_SUPPORTS_NUMA_BALANCING
29 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
30 select ARCH_WANT_FRAME_POINTERS
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
35 select AUDIT_ARCH_COMPAT_GENERIC
36 select ARM_GIC_V2M if PCI
38 select ARM_GIC_V3_ITS if PCI
40 select BUILDTIME_EXTABLE_SORT
41 select CLONE_BACKWARDS
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select DCACHE_WORD_ACCESS
47 select GENERIC_ALLOCATOR
48 select GENERIC_ARCH_TOPOLOGY
49 select GENERIC_CLOCKEVENTS
50 select GENERIC_CLOCKEVENTS_BROADCAST
51 select GENERIC_CPU_AUTOPROBE
52 select GENERIC_CPU_VULNERABILITIES
53 select GENERIC_EARLY_IOREMAP
54 select GENERIC_IDLE_POLL_SETUP
55 select GENERIC_IRQ_PROBE
56 select GENERIC_IRQ_SHOW
57 select GENERIC_IRQ_SHOW_LEVEL
58 select GENERIC_PCI_IOMAP
59 select GENERIC_SCHED_CLOCK
60 select GENERIC_SMP_IDLE_THREAD
61 select GENERIC_STRNCPY_FROM_USER
62 select GENERIC_STRNLEN_USER
63 select GENERIC_TIME_VSYSCALL
64 select HANDLE_DOMAIN_IRQ
65 select HARDIRQS_SW_RESEND
66 select HAVE_ACPI_APEI if (ACPI && EFI)
67 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
68 select HAVE_ARCH_AUDITSYSCALL
69 select HAVE_ARCH_BITREVERSE
70 select HAVE_ARCH_HUGE_VMAP
71 select HAVE_ARCH_JUMP_LABEL
72 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
74 select HAVE_ARCH_MMAP_RND_BITS
75 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
76 select HAVE_ARCH_SECCOMP_FILTER
77 select HAVE_ARCH_TRACEHOOK
78 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
79 select HAVE_ARCH_VMAP_STACK
82 select HAVE_C_RECORDMCOUNT
83 select HAVE_CC_STACKPROTECTOR
84 select HAVE_CMPXCHG_DOUBLE
85 select HAVE_CMPXCHG_LOCAL
86 select HAVE_CONTEXT_TRACKING
87 select HAVE_DEBUG_BUGVERBOSE
88 select HAVE_DEBUG_KMEMLEAK
89 select HAVE_DMA_API_DEBUG
90 select HAVE_DMA_CONTIGUOUS
91 select HAVE_DYNAMIC_FTRACE
92 select HAVE_EFFICIENT_UNALIGNED_ACCESS
93 select HAVE_FTRACE_MCOUNT_RECORD
94 select HAVE_FUNCTION_TRACER
95 select HAVE_FUNCTION_GRAPH_TRACER
96 select HAVE_GCC_PLUGINS
97 select HAVE_GENERIC_DMA_COHERENT
98 select HAVE_HW_BREAKPOINT if PERF_EVENTS
99 select HAVE_IRQ_TIME_ACCOUNTING
101 select HAVE_MEMBLOCK_NODE_MAP if NUMA
102 select HAVE_NMI if ACPI_APEI_SEA
103 select HAVE_PATA_PLATFORM
104 select HAVE_PERF_EVENTS
105 select HAVE_PERF_REGS
106 select HAVE_PERF_USER_STACK_DUMP
107 select HAVE_REGS_AND_STACK_ACCESS_API
108 select HAVE_RCU_TABLE_FREE
109 select HAVE_SYSCALL_TRACEPOINTS
111 select HAVE_KRETPROBES
112 select IOMMU_DMA if IOMMU_SUPPORT
114 select IRQ_FORCED_THREADING
115 select MODULES_USE_ELF_RELA
118 select OF_EARLY_FLATTREE
119 select OF_RESERVED_MEM
120 select PCI_ECAM if ACPI
124 select SYSCTL_EXCEPTION_TRACE
125 select THREAD_INFO_IN_TASK
127 ARM 64-bit (AArch64) Linux support.
132 config ARCH_PHYS_ADDR_T_64BIT
138 config ARM64_PAGE_SHIFT
140 default 16 if ARM64_64K_PAGES
141 default 14 if ARM64_16K_PAGES
144 config ARM64_CONT_SHIFT
146 default 5 if ARM64_64K_PAGES
147 default 7 if ARM64_16K_PAGES
150 config ARCH_MMAP_RND_BITS_MIN
151 default 14 if ARM64_64K_PAGES
152 default 16 if ARM64_16K_PAGES
155 # max bits determined by the following formula:
156 # VA_BITS - PAGE_SHIFT - 3
157 config ARCH_MMAP_RND_BITS_MAX
158 default 19 if ARM64_VA_BITS=36
159 default 24 if ARM64_VA_BITS=39
160 default 27 if ARM64_VA_BITS=42
161 default 30 if ARM64_VA_BITS=47
162 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
163 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
164 default 33 if ARM64_VA_BITS=48
165 default 14 if ARM64_64K_PAGES
166 default 16 if ARM64_16K_PAGES
169 config ARCH_MMAP_RND_COMPAT_BITS_MIN
170 default 7 if ARM64_64K_PAGES
171 default 9 if ARM64_16K_PAGES
174 config ARCH_MMAP_RND_COMPAT_BITS_MAX
180 config STACKTRACE_SUPPORT
183 config ILLEGAL_POINTER_VALUE
185 default 0xdead000000000000
187 config LOCKDEP_SUPPORT
190 config TRACE_IRQFLAGS_SUPPORT
193 config RWSEM_XCHGADD_ALGORITHM
200 config GENERIC_BUG_RELATIVE_POINTERS
202 depends on GENERIC_BUG
204 config GENERIC_HWEIGHT
210 config GENERIC_CALIBRATE_DELAY
216 config HAVE_GENERIC_GUP
219 config ARCH_DMA_ADDR_T_64BIT
222 config NEED_DMA_MAP_STATE
225 config NEED_SG_DMA_LENGTH
237 config KERNEL_MODE_NEON
240 config FIX_EARLYCON_MEM
243 config PGTABLE_LEVELS
245 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
246 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
247 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
248 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
249 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
250 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
252 config ARCH_SUPPORTS_UPROBES
255 config ARCH_PROC_KCORE_TEXT
258 source "init/Kconfig"
260 source "kernel/Kconfig.freezer"
262 source "arch/arm64/Kconfig.platforms"
269 This feature enables support for PCI bus system. If you say Y
270 here, the kernel will include drivers and infrastructure code
271 to support PCI bus devices.
276 config PCI_DOMAINS_GENERIC
282 source "drivers/pci/Kconfig"
286 menu "Kernel Features"
288 menu "ARM errata workarounds via the alternatives framework"
290 config ARM64_ERRATUM_826319
291 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
294 This option adds an alternative code sequence to work around ARM
295 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
296 AXI master interface and an L2 cache.
298 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
299 and is unable to accept a certain write via this interface, it will
300 not progress on read data presented on the read data channel and the
303 The workaround promotes data cache clean instructions to
304 data cache clean-and-invalidate.
305 Please note that this does not necessarily enable the workaround,
306 as it depends on the alternative framework, which will only patch
307 the kernel if an affected CPU is detected.
311 config ARM64_ERRATUM_827319
312 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
315 This option adds an alternative code sequence to work around ARM
316 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
317 master interface and an L2 cache.
319 Under certain conditions this erratum can cause a clean line eviction
320 to occur at the same time as another transaction to the same address
321 on the AMBA 5 CHI interface, which can cause data corruption if the
322 interconnect reorders the two transactions.
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
332 config ARM64_ERRATUM_824069
333 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
336 This option adds an alternative code sequence to work around ARM
337 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
338 to a coherent interconnect.
340 If a Cortex-A53 processor is executing a store or prefetch for
341 write instruction at the same time as a processor in another
342 cluster is executing a cache maintenance operation to the same
343 address, then this erratum might cause a clean cache line to be
344 incorrectly marked as dirty.
346 The workaround promotes data cache clean instructions to
347 data cache clean-and-invalidate.
348 Please note that this option does not necessarily enable the
349 workaround, as it depends on the alternative framework, which will
350 only patch the kernel if an affected CPU is detected.
354 config ARM64_ERRATUM_819472
355 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
358 This option adds an alternative code sequence to work around ARM
359 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
360 present when it is connected to a coherent interconnect.
362 If the processor is executing a load and store exclusive sequence at
363 the same time as a processor in another cluster is executing a cache
364 maintenance operation to the same address, then this erratum might
365 cause data corruption.
367 The workaround promotes data cache clean instructions to
368 data cache clean-and-invalidate.
369 Please note that this does not necessarily enable the workaround,
370 as it depends on the alternative framework, which will only patch
371 the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_832075
376 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
379 This option adds an alternative code sequence to work around ARM
380 erratum 832075 on Cortex-A57 parts up to r1p2.
382 Affected Cortex-A57 parts might deadlock when exclusive load/store
383 instructions to Write-Back memory are mixed with Device loads.
385 The workaround is to promote device loads to use Load-Acquire
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_834220
394 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
398 This option adds an alternative code sequence to work around ARM
399 erratum 834220 on Cortex-A57 parts up to r1p2.
401 Affected Cortex-A57 parts might report a Stage 2 translation
402 fault as the result of a Stage 1 fault for load crossing a
403 page boundary when there is a permission or device memory
404 alignment fault at Stage 1 and a translation fault at Stage 2.
406 The workaround is to verify that the Stage 1 translation
407 doesn't generate a fault before handling the Stage 2 fault.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
414 config ARM64_ERRATUM_845719
415 bool "Cortex-A53: 845719: a load might read incorrect data"
419 This option adds an alternative code sequence to work around ARM
420 erratum 845719 on Cortex-A53 parts up to r0p4.
422 When running a compat (AArch32) userspace on an affected Cortex-A53
423 part, a load at EL0 from a virtual address that matches the bottom 32
424 bits of the virtual address used by a recent load at (AArch64) EL1
425 might return incorrect data.
427 The workaround is to write the contextidr_el1 register on exception
428 return to a 32-bit task.
429 Please note that this does not necessarily enable the workaround,
430 as it depends on the alternative framework, which will only patch
431 the kernel if an affected CPU is detected.
435 config ARM64_ERRATUM_843419
436 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
438 select ARM64_MODULE_CMODEL_LARGE if MODULES
440 This option links the kernel with '--fix-cortex-a53-843419' and
441 builds modules using the large memory model in order to avoid the use
442 of the ADRP instruction, which can cause a subsequent memory access
443 to use an incorrect address on Cortex-A53 parts up to r0p4.
447 config ARM64_ERRATUM_1024718
448 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
451 This option adds work around for Arm Cortex-A55 Erratum 1024718.
453 Affected Cortex-A55 cores (all revisions) could cause incorrect
454 update of the hardware dirty bit when the DBM/AP bits are updated
455 without a break-before-make. The work around is to disable the usage
456 of hardware DBM locally on the affected cores. CPUs not affected by
457 erratum will continue to use the feature.
461 config CAVIUM_ERRATUM_22375
462 bool "Cavium erratum 22375, 24313"
465 Enable workaround for erratum 22375, 24313.
467 This implements two gicv3-its errata workarounds for ThunderX. Both
468 with small impact affecting only ITS table allocation.
470 erratum 22375: only alloc 8MB table size
471 erratum 24313: ignore memory access type
473 The fixes are in ITS initialization and basically ignore memory access
474 type and table size provided by the TYPER and BASER registers.
478 config CAVIUM_ERRATUM_23144
479 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
483 ITS SYNC command hang for cross node io and collections/cpu mapping.
487 config CAVIUM_ERRATUM_23154
488 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
491 The gicv3 of ThunderX requires a modified version for
492 reading the IAR status to ensure data synchronization
493 (access to icc_iar1_el1 is not sync'ed before and after).
497 config CAVIUM_ERRATUM_27456
498 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
501 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
502 instructions may cause the icache to become corrupted if it
503 contains data for a non-current ASID. The fix is to
504 invalidate the icache when changing the mm context.
508 config CAVIUM_ERRATUM_30115
509 bool "Cavium erratum 30115: Guest may disable interrupts in host"
512 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
513 1.2, and T83 Pass 1.0, KVM guest execution may disable
514 interrupts in host. Trapping both GICv3 group-0 and group-1
515 accesses sidesteps the issue.
519 config QCOM_FALKOR_ERRATUM_1003
520 bool "Falkor E1003: Incorrect translation due to ASID change"
523 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
524 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
525 in TTBR1_EL1, this situation only occurs in the entry trampoline and
526 then only for entries in the walk cache, since the leaf translation
527 is unchanged. Work around the erratum by invalidating the walk cache
528 entries for the trampoline before entering the kernel proper.
530 config QCOM_FALKOR_ERRATUM_1009
531 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
534 On Falkor v1, the CPU may prematurely complete a DSB following a
535 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
536 one more time to fix the issue.
540 config QCOM_QDF2400_ERRATUM_0065
541 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
544 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
545 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
546 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
550 config QCOM_FALKOR_ERRATUM_E1041
551 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
554 Falkor CPU may speculatively fetch instructions from an improper
555 memory location when MMU translation is changed from SCTLR_ELn[M]=1
556 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
565 default ARM64_4K_PAGES
567 Page size (translation granule) configuration.
569 config ARM64_4K_PAGES
572 This feature enables 4KB pages support.
574 config ARM64_16K_PAGES
577 The system will use 16KB pages support. AArch32 emulation
578 requires applications compiled with 16K (or a multiple of 16K)
581 config ARM64_64K_PAGES
584 This feature enables 64KB pages support (4KB by default)
585 allowing only two levels of page tables and faster TLB
586 look-up. AArch32 emulation requires applications compiled
587 with 64K aligned segments.
592 prompt "Virtual address space size"
593 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
594 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
595 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
597 Allows choosing one of multiple possible virtual address
598 space sizes. The level of translation table is determined by
599 a combination of page size and virtual address space size.
601 config ARM64_VA_BITS_36
602 bool "36-bit" if EXPERT
603 depends on ARM64_16K_PAGES
605 config ARM64_VA_BITS_39
607 depends on ARM64_4K_PAGES
609 config ARM64_VA_BITS_42
611 depends on ARM64_64K_PAGES
613 config ARM64_VA_BITS_47
615 depends on ARM64_16K_PAGES
617 config ARM64_VA_BITS_48
624 default 36 if ARM64_VA_BITS_36
625 default 39 if ARM64_VA_BITS_39
626 default 42 if ARM64_VA_BITS_42
627 default 47 if ARM64_VA_BITS_47
628 default 48 if ARM64_VA_BITS_48
630 config CPU_BIG_ENDIAN
631 bool "Build big-endian kernel"
633 Say Y if you plan on running a kernel in big-endian mode.
636 bool "Multi-core scheduler support"
638 Multi-core scheduler support improves the CPU scheduler's decision
639 making when dealing with multi-core CPU chips at a cost of slightly
640 increased overhead in some places. If unsure say N here.
643 bool "SMT scheduler support"
645 Improves the CPU scheduler's decision making when dealing with
646 MultiThreading at a cost of slightly increased overhead in some
647 places. If unsure say N here.
650 int "Maximum number of CPUs (2-4096)"
652 # These have to remain sorted largest to smallest
656 bool "Support for hot-pluggable CPUs"
657 select GENERIC_IRQ_MIGRATION
659 Say Y here to experiment with turning CPUs off and on. CPUs
660 can be controlled through /sys/devices/system/cpu.
662 # Common NUMA Features
664 bool "Numa Memory Allocation and Scheduler Support"
665 select ACPI_NUMA if ACPI
668 Enable NUMA (Non Uniform Memory Access) support.
670 The kernel will try to allocate memory used by a CPU on the
671 local memory of the CPU and add some more
672 NUMA awareness to the kernel.
675 int "Maximum NUMA Nodes (as a power of 2)"
678 depends on NEED_MULTIPLE_NODES
680 Specify the maximum number of NUMA Nodes available on the target
681 system. Increases memory reserved to accommodate various tables.
683 config USE_PERCPU_NUMA_NODE_ID
687 config HAVE_SETUP_PER_CPU_AREA
691 config NEED_PER_CPU_EMBED_FIRST_CHUNK
698 source kernel/Kconfig.preempt
699 source kernel/Kconfig.hz
701 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
704 config ARCH_HAS_HOLES_MEMORYMODEL
705 def_bool y if SPARSEMEM
707 config ARCH_SPARSEMEM_ENABLE
709 select SPARSEMEM_VMEMMAP_ENABLE
711 config ARCH_SPARSEMEM_DEFAULT
712 def_bool ARCH_SPARSEMEM_ENABLE
714 config ARCH_SELECT_MEMORY_MODEL
715 def_bool ARCH_SPARSEMEM_ENABLE
717 config HAVE_ARCH_PFN_VALID
718 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
720 config HW_PERF_EVENTS
724 config SYS_SUPPORTS_HUGETLBFS
727 config ARCH_WANT_HUGE_PMD_SHARE
728 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
730 config ARCH_HAS_CACHE_LINE_SIZE
736 bool "Enable seccomp to safely compute untrusted bytecode"
738 This kernel feature is useful for number crunching applications
739 that may need to compute untrusted bytecode during their
740 execution. By using pipes or other transports made available to
741 the process as file descriptors supporting the read/write
742 syscalls, it's possible to isolate those applications in
743 their own address space using seccomp. Once seccomp is
744 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
745 and the task is only allowed to execute a few safe syscalls
746 defined by each seccomp mode.
749 bool "Enable paravirtualization code"
751 This changes the kernel so it can modify itself when it is run
752 under a hypervisor, potentially improving performance significantly
753 over full virtualization.
755 config PARAVIRT_TIME_ACCOUNTING
756 bool "Paravirtual steal time accounting"
760 Select this option to enable fine granularity task steal time
761 accounting. Time spent executing other tasks in parallel with
762 the current vCPU is discounted from the vCPU power. To account for
763 that, there can be a small performance impact.
765 If in doubt, say N here.
768 depends on PM_SLEEP_SMP
770 bool "kexec system call"
772 kexec is a system call that implements the ability to shutdown your
773 current kernel, and to start another kernel. It is like a reboot
774 but it is independent of the system firmware. And like a reboot
775 you can start any kernel with it, not just Linux.
778 bool "Build kdump crash kernel"
780 Generate crash dump after being started by kexec. This should
781 be normally only set in special crash dump kernels which are
782 loaded in the main kernel with kexec-tools into a specially
783 reserved region and then later executed after a crash by
786 For more details see Documentation/kdump/kdump.txt
793 bool "Xen guest support on ARM64"
794 depends on ARM64 && OF
798 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
800 config FORCE_MAX_ZONEORDER
802 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
803 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
806 The kernel memory allocator divides physically contiguous memory
807 blocks into "zones", where each zone is a power of two number of
808 pages. This option selects the largest power of two that the kernel
809 keeps in the memory allocator. If you need to allocate very large
810 blocks of physically contiguous memory, then you may need to
813 This config option is actually maximum order plus one. For example,
814 a value of 11 means that the largest free memory block is 2^10 pages.
816 We make sure that we can allocate upto a HugePage size for each configuration.
818 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
820 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
821 4M allocations matching the default size used by generic code.
823 config UNMAP_KERNEL_AT_EL0
824 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
827 Speculation attacks against some high-performance processors can
828 be used to bypass MMU permission checks and leak kernel data to
829 userspace. This can be defended against by unmapping the kernel
830 when running in userspace, mapping it back in on exception entry
831 via a trampoline page in the vector table.
835 config HARDEN_BRANCH_PREDICTOR
836 bool "Harden the branch predictor against aliasing attacks" if EXPERT
839 Speculation attacks against some high-performance processors rely on
840 being able to manipulate the branch predictor for a victim context by
841 executing aliasing branches in the attacker context. Such attacks
842 can be partially mitigated against by clearing internal branch
843 predictor state and limiting the prediction logic in some situations.
845 This config option will take CPU-specific actions to harden the
846 branch predictor against aliasing attacks and may rely on specific
847 instruction sequences or control bits being set by the system
853 bool "Speculative Store Bypass Disable" if EXPERT
856 This enables mitigation of the bypassing of previous stores
857 by speculative loads.
861 menuconfig ARMV8_DEPRECATED
862 bool "Emulate deprecated/obsolete ARMv8 instructions"
865 Legacy software support may require certain instructions
866 that have been deprecated or obsoleted in the architecture.
868 Enable this config to enable selective emulation of these
876 bool "Emulate SWP/SWPB instructions"
878 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
879 they are always undefined. Say Y here to enable software
880 emulation of these instructions for userspace using LDXR/STXR.
882 In some older versions of glibc [<=2.8] SWP is used during futex
883 trylock() operations with the assumption that the code will not
884 be preempted. This invalid assumption may be more likely to fail
885 with SWP emulation enabled, leading to deadlock of the user
888 NOTE: when accessing uncached shared regions, LDXR/STXR rely
889 on an external transaction monitoring block called a global
890 monitor to maintain update atomicity. If your system does not
891 implement a global monitor, this option can cause programs that
892 perform SWP operations to uncached memory to deadlock.
896 config CP15_BARRIER_EMULATION
897 bool "Emulate CP15 Barrier instructions"
899 The CP15 barrier instructions - CP15ISB, CP15DSB, and
900 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
901 strongly recommended to use the ISB, DSB, and DMB
902 instructions instead.
904 Say Y here to enable software emulation of these
905 instructions for AArch32 userspace code. When this option is
906 enabled, CP15 barrier usage is traced which can help
907 identify software that needs updating.
911 config SETEND_EMULATION
912 bool "Emulate SETEND instruction"
914 The SETEND instruction alters the data-endianness of the
915 AArch32 EL0, and is deprecated in ARMv8.
917 Say Y here to enable software emulation of the instruction
918 for AArch32 userspace code.
920 Note: All the cpus on the system must have mixed endian support at EL0
921 for this feature to be enabled. If a new CPU - which doesn't support mixed
922 endian - is hotplugged in after this feature has been enabled, there could
923 be unexpected results in the applications.
928 config ARM64_SW_TTBR0_PAN
929 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
931 Enabling this option prevents the kernel from accessing
932 user-space memory directly by pointing TTBR0_EL1 to a reserved
933 zeroed area and reserved ASID. The user access routines
934 restore the valid TTBR0_EL1 temporarily.
936 menu "ARMv8.1 architectural features"
938 config ARM64_HW_AFDBM
939 bool "Support for hardware updates of the Access and Dirty page flags"
942 The ARMv8.1 architecture extensions introduce support for
943 hardware updates of the access and dirty information in page
944 table entries. When enabled in TCR_EL1 (HA and HD bits) on
945 capable processors, accesses to pages with PTE_AF cleared will
946 set this bit instead of raising an access flag fault.
947 Similarly, writes to read-only pages with the DBM bit set will
948 clear the read-only bit (AP[2]) instead of raising a
951 Kernels built with this configuration option enabled continue
952 to work on pre-ARMv8.1 hardware and the performance impact is
953 minimal. If unsure, say Y.
956 bool "Enable support for Privileged Access Never (PAN)"
959 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
960 prevents the kernel or hypervisor from accessing user-space (EL0)
963 Choosing this option will cause any unprotected (not using
964 copy_to_user et al) memory access to fail with a permission fault.
966 The feature is detected at runtime, and will remain as a 'nop'
967 instruction if the cpu does not implement the feature.
969 config ARM64_LSE_ATOMICS
970 bool "Atomic instructions"
972 As part of the Large System Extensions, ARMv8.1 introduces new
973 atomic instructions that are designed specifically to scale in
976 Say Y here to make use of these instructions for the in-kernel
977 atomic routines. This incurs a small overhead on CPUs that do
978 not support these instructions and requires the kernel to be
979 built with binutils >= 2.25.
982 bool "Enable support for Virtualization Host Extensions (VHE)"
985 Virtualization Host Extensions (VHE) allow the kernel to run
986 directly at EL2 (instead of EL1) on processors that support
987 it. This leads to better performance for KVM, as they reduce
988 the cost of the world switch.
990 Selecting this option allows the VHE feature to be detected
991 at runtime, and does not affect processors that do not
992 implement this feature.
996 menu "ARMv8.2 architectural features"
999 bool "Enable support for User Access Override (UAO)"
1002 User Access Override (UAO; part of the ARMv8.2 Extensions)
1003 causes the 'unprivileged' variant of the load/store instructions to
1004 be overriden to be privileged.
1006 This option changes get_user() and friends to use the 'unprivileged'
1007 variant of the load/store instructions. This ensures that user-space
1008 really did have access to the supplied memory. When addr_limit is
1009 set to kernel memory the UAO bit will be set, allowing privileged
1010 access to kernel memory.
1012 Choosing this option will cause copy_to_user() et al to use user-space
1015 The feature is detected at runtime, the kernel will use the
1016 regular load/store instructions if the cpu does not implement the
1020 bool "Enable support for persistent memory"
1021 select ARCH_HAS_PMEM_API
1022 select ARCH_HAS_UACCESS_FLUSHCACHE
1024 Say Y to enable support for the persistent memory API based on the
1025 ARMv8.2 DCPoP feature.
1027 The feature is detected at runtime, and the kernel will use DC CVAC
1028 operations if DC CVAP is not supported (following the behaviour of
1029 DC CVAP itself if the system does not define a point of persistence).
1033 config ARM64_MODULE_CMODEL_LARGE
1036 config ARM64_MODULE_PLTS
1038 select ARM64_MODULE_CMODEL_LARGE
1039 select HAVE_MOD_ARCH_SPECIFIC
1044 This builds the kernel as a Position Independent Executable (PIE),
1045 which retains all relocation metadata required to relocate the
1046 kernel binary at runtime to a different virtual address than the
1047 address it was linked at.
1048 Since AArch64 uses the RELA relocation format, this requires a
1049 relocation pass at runtime even if the kernel is loaded at the
1050 same address it was linked at.
1052 config RANDOMIZE_BASE
1053 bool "Randomize the address of the kernel image"
1054 select ARM64_MODULE_PLTS if MODULES
1057 Randomizes the virtual address at which the kernel image is
1058 loaded, as a security feature that deters exploit attempts
1059 relying on knowledge of the location of kernel internals.
1061 It is the bootloader's job to provide entropy, by passing a
1062 random u64 value in /chosen/kaslr-seed at kernel entry.
1064 When booting via the UEFI stub, it will invoke the firmware's
1065 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1066 to the kernel proper. In addition, it will randomise the physical
1067 location of the kernel Image as well.
1071 config RANDOMIZE_MODULE_REGION_FULL
1072 bool "Randomize the module region independently from the core kernel"
1073 depends on RANDOMIZE_BASE
1076 Randomizes the location of the module region without considering the
1077 location of the core kernel. This way, it is impossible for modules
1078 to leak information about the location of core kernel data structures
1079 but it does imply that function calls between modules and the core
1080 kernel will need to be resolved via veneers in the module PLT.
1082 When this option is not set, the module region will be randomized over
1083 a limited range that contains the [_stext, _etext] interval of the
1084 core kernel, so branch relocations are always in range.
1090 config ARM64_ACPI_PARKING_PROTOCOL
1091 bool "Enable support for the ARM64 ACPI parking protocol"
1094 Enable support for the ARM64 ACPI parking protocol. If disabled
1095 the kernel will not allow booting through the ARM64 ACPI parking
1096 protocol even if the corresponding data is present in the ACPI
1100 string "Default kernel command string"
1103 Provide a set of default command-line options at build time by
1104 entering them here. As a minimum, you should specify the the
1105 root device (e.g. root=/dev/nfs).
1107 config CMDLINE_FORCE
1108 bool "Always use the default kernel command string"
1110 Always use the default kernel command string, even if the boot
1111 loader passes other arguments to the kernel.
1112 This is useful if you cannot or don't want to change the
1113 command-line options your boot loader passes to the kernel.
1119 bool "UEFI runtime support"
1120 depends on OF && !CPU_BIG_ENDIAN
1123 select EFI_PARAMS_FROM_FDT
1124 select EFI_RUNTIME_WRAPPERS
1129 This option provides support for runtime services provided
1130 by UEFI firmware (such as non-volatile variables, realtime
1131 clock, and platform reset). A UEFI stub is also provided to
1132 allow the kernel to be booted as an EFI application. This
1133 is only useful on systems that have UEFI firmware.
1136 bool "Enable support for SMBIOS (DMI) tables"
1140 This enables SMBIOS/DMI feature for systems.
1142 This option is only useful on systems that have UEFI firmware.
1143 However, even with this option, the resultant kernel should
1144 continue to boot on existing non-UEFI platforms.
1148 menu "Userspace binary formats"
1150 source "fs/Kconfig.binfmt"
1153 bool "Kernel support for 32-bit EL0"
1154 depends on ARM64_4K_PAGES || EXPERT
1155 select COMPAT_BINFMT_ELF if BINFMT_ELF
1157 select OLD_SIGSUSPEND3
1158 select COMPAT_OLD_SIGACTION
1160 This option enables support for a 32-bit EL0 running under a 64-bit
1161 kernel at EL1. AArch32-specific components such as system calls,
1162 the user helper functions, VFP support and the ptrace interface are
1163 handled appropriately by the kernel.
1165 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1166 that you will only be able to execute AArch32 binaries that were compiled
1167 with page size aligned segments.
1169 If you want to execute 32-bit userspace applications, say Y.
1171 config SYSVIPC_COMPAT
1173 depends on COMPAT && SYSVIPC
1177 menu "Power management options"
1179 source "kernel/power/Kconfig"
1181 config ARCH_HIBERNATION_POSSIBLE
1185 config ARCH_HIBERNATION_HEADER
1187 depends on HIBERNATION
1189 config ARCH_SUSPEND_POSSIBLE
1194 menu "CPU Power Management"
1196 source "drivers/cpuidle/Kconfig"
1198 source "drivers/cpufreq/Kconfig"
1202 source "net/Kconfig"
1204 source "drivers/Kconfig"
1206 source "drivers/firmware/Kconfig"
1208 source "drivers/acpi/Kconfig"
1212 source "arch/arm64/kvm/Kconfig"
1214 source "arch/arm64/Kconfig.debug"
1216 source "security/Kconfig"
1218 source "crypto/Kconfig"
1220 source "arch/arm64/crypto/Kconfig"
1223 source "lib/Kconfig"