1 # SPDX-License-Identifier: GPL-2.0
7 prompt "8xx Machine Type"
18 MPC86x Application Development System by Freescale Semiconductor.
19 The MPC86xADS is meant to serve as a platform for s/w and h/w
20 development around the MPC86X processor families.
27 Freescale Semiconductor MPC885 Application Development System (ADS).
29 The MPC885ADS is meant to serve as a platform for s/w and h/w
30 development around the MPC885 processor family.
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
36 This enables support for the Embedded Planet EP88xC board.
38 This board is also resold by Freescale as the QUICCStart
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
52 support for the mpc8xx based boards from TQM.
56 menu "Freescale Ethernet driver platform-specific options"
57 depends on (FS_ENET && MPC885ADS)
59 config MPC8xx_SECOND_ETH
60 bool "Second Ethernet channel"
64 This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
65 The latter will use SCC1, for 885ADS you can select it below.
68 prompt "Second Ethernet channel"
69 depends on MPC8xx_SECOND_ETH
70 default MPC8xx_SECOND_ETH_FEC2
72 config MPC8xx_SECOND_ETH_FEC2
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
79 config MPC8xx_SECOND_ETH_SCC3
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
91 # MPC8xx Communication options
94 menu "MPC8xx CPM Options"
97 # This doesn't really belong here, but it is convenient to ask
98 # 8xx specific questions.
99 comment "Generic MPC8xx Options"
102 bool "GPIO API Support"
104 select OF_GPIO_MM_GPIOCHIP
106 Saying Y here will cause the ports on an MPC8xx processor to be used
107 with the GPIO API. If you say N here, the kernel needs less memory.
109 If in doubt, say Y here.
112 bool "CPU15 Silicon Errata"
113 depends on !HUGETLB_PAGE
116 This enables a workaround for erratum CPU15 on MPC8xx chips.
117 This bug can cause incorrect code execution under certain
118 circumstances. This workaround adds some overhead (a TLB miss
119 every time execution crosses a page boundary), and you may wish
120 to disable it if you have worked around the bug in the compiler
121 (by not placing conditional branches or branches to LR or CTR
122 in the last word of a page, with a target of the last cache
123 line in the next page), or if you have used some other
126 If in doubt, say Y here.
129 prompt "Microcode patch selection"
130 default NO_UCODE_PATCH
132 Help not implemented yet, coming soon.
134 config NO_UCODE_PATCH
137 config USB_SOF_UCODE_PATCH
140 Help not implemented yet, coming soon.
142 config I2C_SPI_UCODE_PATCH
143 bool "I2C/SPI relocation patch"
145 Help not implemented yet, coming soon.
147 config I2C_SPI_SMC1_UCODE_PATCH
148 bool "I2C/SPI/SMC1 relocation patch"
150 Help not implemented yet, coming soon.
152 config SMC_UCODE_PATCH
153 bool "SMC relocation patch"
155 This microcode relocates SMC1 and SMC2 parameter RAMs at
156 offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM
164 depends on !NO_UCODE_PATCH
166 menu "8xx advanced setup"
170 bool "Pinned Kernel TLBs"
171 depends on ADVANCED_OPTIONS
173 On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
174 table 4 TLBs can be pinned.
176 It reduces the amount of usable TLBs to 28 (ie by 12%). That's the
177 reason why we make it selectable.
179 This option does nothing, it just activate the selection of what
183 bool "Pinned TLB for DATA"
187 This pins the first 32 Mbytes of memory with 8M pages.
190 bool "Pinned TLB for IMMR"
194 This pins the IMMR area with a 512kbytes page. In case
195 CONFIG_PIN_TLB_DATA is also selected, it will reduce
196 CONFIG_PIN_TLB_DATA to 24 Mbytes.